decoder.isa (8588:ef28ed90449d) | decoder.isa (8607:5fb918115c07) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 483 unchanged lines hidden (view full) --- 492 }}); 493 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); 494 default: CP0Unimpl::unknown(); 495 496 } 497 0x2: mttc1({{ 498 uint64_t data = xc->readRegOtherThread(RD + 499 FP_Base_DepTag); | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 483 unchanged lines hidden (view full) --- 492 }}); 493 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); 494 default: CP0Unimpl::unknown(); 495 496 } 497 0x2: mttc1({{ 498 uint64_t data = xc->readRegOtherThread(RD + 499 FP_Base_DepTag); |
500 data = insertBits(data, top_bit, 501 bottom_bit, Rt); | 500 data = insertBits(data, MT_H ? 63 : 31, 501 MT_H ? 32 : 0, Rt); |
502 xc->setRegOtherThread(RD + FP_Base_DepTag, 503 data); 504 }}); 505 0x3: cttc1({{ 506 uint32_t data; 507 switch (RD) { 508 case 25: 509 data = (Rt_uw<7:1> << 25) | // move 31-25 --- 17 unchanged lines hidden (view full) --- 527 break; 528 case 31: 529 data = Rt_uw; 530 break; 531 default: 532 panic("FP Control Value (%d) " 533 "Not Available. Ignoring " 534 "Access to Floating Control " | 502 xc->setRegOtherThread(RD + FP_Base_DepTag, 503 data); 504 }}); 505 0x3: cttc1({{ 506 uint32_t data; 507 switch (RD) { 508 case 25: 509 data = (Rt_uw<7:1> << 25) | // move 31-25 --- 17 unchanged lines hidden (view full) --- 527 break; 528 case 31: 529 data = Rt_uw; 530 break; 531 default: 532 panic("FP Control Value (%d) " 533 "Not Available. Ignoring " 534 "Access to Floating Control " |
535 "Status Register", FS); | 535 "S""tatus Register", FS); |
536 } 537 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); 538 }}); 539 default: CP0Unimpl::unknown(); 540 } 541 } 542 } 543 0xB: decode RD { --- 227 unchanged lines hidden (view full) --- 771 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 772 Config3Reg config3 = Config3; 773 PageGrainReg pageGrain = PageGrain; 774 int SP = 0; 775 if (bits(config3, config3.sp) == 1 && 776 bits(pageGrain, pageGrain.esp) == 1) { 777 SP = 1; 778 } | 536 } 537 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); 538 }}); 539 default: CP0Unimpl::unknown(); 540 } 541 } 542 } 543 0xB: decode RD { --- 227 unchanged lines hidden (view full) --- 771 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 772 Config3Reg config3 = Config3; 773 PageGrainReg pageGrain = PageGrain; 774 int SP = 0; 775 if (bits(config3, config3.sp) == 1 && 776 bits(pageGrain, pageGrain.esp) == 1) { 777 SP = 1; 778 } |
779 IndexReg index = Index; | |
780 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 781 }}); 782 0x06: tlbwr({{ 783 //Create PTE 784 MipsISA::PTE newEntry; 785 //Write PTE 786 newEntry.Mask = (Addr)(PageMask >> 11); 787 newEntry.VPN = (Addr)(EntryHi >> 11); --- 49 unchanged lines hidden (view full) --- 837 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 838 Config3Reg config3 = Config3; 839 PageGrainReg pageGrain = PageGrain; 840 int SP = 0; 841 if (bits(config3, config3.sp) == 1 && 842 bits(pageGrain, pageGrain.esp) == 1) { 843 SP = 1; 844 } | 779 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 780 }}); 781 0x06: tlbwr({{ 782 //Create PTE 783 MipsISA::PTE newEntry; 784 //Write PTE 785 newEntry.Mask = (Addr)(PageMask >> 11); 786 newEntry.VPN = (Addr)(EntryHi >> 11); --- 49 unchanged lines hidden (view full) --- 836 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 837 Config3Reg config3 = Config3; 838 PageGrainReg pageGrain = PageGrain; 839 int SP = 0; 840 if (bits(config3, config3.sp) == 1 && 841 bits(pageGrain, pageGrain.esp) == 1) { 842 SP = 1; 843 } |
845 IndexReg index = Index; | |
846 Ptr->insertAt(newEntry, Random, SP); 847 }}); 848 849 0x08: tlbp({{ 850 Config3Reg config3 = Config3; 851 PageGrainReg pageGrain = PageGrain; 852 EntryHiReg entryHi = EntryHi; 853 int tlbIndex; --- 1670 unchanged lines hidden --- | 844 Ptr->insertAt(newEntry, Random, SP); 845 }}); 846 847 0x08: tlbp({{ 848 Config3Reg config3 = Config3; 849 PageGrainReg pageGrain = PageGrain; 850 EntryHiReg entryHi = EntryHi; 851 int tlbIndex; --- 1670 unchanged lines hidden --- |