decoder.isa (7720:65d338a8dba4) | decoder.isa (7792:8ac74e34c6f4) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 119 unchanged lines hidden (view full) --- 128 0x1: decode FUNCTION_LO { 129 //Table A-3 Note: "Specific encodings of the hint field are 130 //used to distinguish JR from JR.HB and JALR from JALR.HB" 131 format Jump { 132 0x0: decode HINT { 133 0x1: jr_hb({{ 134 Config1Reg config1 = Config1; 135 if (config1.ca == 0) { | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 119 unchanged lines hidden (view full) --- 128 0x1: decode FUNCTION_LO { 129 //Table A-3 Note: "Specific encodings of the hint field are 130 //used to distinguish JR from JR.HB and JALR from JALR.HB" 131 format Jump { 132 0x0: decode HINT { 133 0x1: jr_hb({{ 134 Config1Reg config1 = Config1; 135 if (config1.ca == 0) { |
136 pc.nnpc(Rs); | 136 NNPC = Rs; |
137 } else { 138 panic("MIPS16e not supported\n"); 139 } | 137 } else { 138 panic("MIPS16e not supported\n"); 139 } |
140 PCS = pc; | |
141 }}, IsReturn, ClearHazards); 142 default: jr({{ 143 Config1Reg config1 = Config1; 144 if (config1.ca == 0) { | 140 }}, IsReturn, ClearHazards); 141 default: jr({{ 142 Config1Reg config1 = Config1; 143 if (config1.ca == 0) { |
145 pc.nnpc(Rs); | 144 NNPC = Rs; |
146 } else { 147 panic("MIPS16e not supported\n"); 148 } | 145 } else { 146 panic("MIPS16e not supported\n"); 147 } |
149 PCS = pc; | |
150 }}, IsReturn); 151 } 152 153 0x1: decode HINT { 154 0x1: jalr_hb({{ | 148 }}, IsReturn); 149 } 150 151 0x1: decode HINT { 152 0x1: jalr_hb({{ |
155 Rd = pc.nnpc(); 156 pc.nnpc(Rs); 157 PCS = pc; | 153 Rd = NNPC; 154 NNPC = Rs; |
158 }}, IsCall, ClearHazards); 159 default: jalr({{ | 155 }}, IsCall, ClearHazards); 156 default: jalr({{ |
160 Rd = pc.nnpc(); 161 pc.nnpc(Rs); 162 PCS = pc; | 157 Rd = NNPC; 158 NNPC = Rs; |
163 }}, IsCall); 164 } 165 } 166 167 format BasicOp { 168 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 169 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 170#if FULL_SYSTEM --- 156 unchanged lines hidden (view full) --- 327 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 328 format WarnUnimpl { 329 0x7: synci(); 330 } 331 } 332 } 333 334 format Jump { | 159 }}, IsCall); 160 } 161 } 162 163 format BasicOp { 164 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 165 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 166#if FULL_SYSTEM --- 156 unchanged lines hidden (view full) --- 323 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 324 format WarnUnimpl { 325 0x7: synci(); 326 } 327 } 328 } 329 330 format Jump { |
335 0x2: j({{ 336 pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2)); 337 PCS = pc; 338 }}); 339 0x3: jal({{ 340 pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2)); 341 PCS = pc; 342 }}, IsCall, Link); | 331 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}); 332 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, 333 IsCall, Link); |
343 } 344 345 format Branch { 346 0x4: decode RS_RT { 347 0x0: b({{ cond = 1; }}); 348 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 349 } 350 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); --- 352 unchanged lines hidden (view full) --- 703 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 704 0x1: decode FUNCTION { 705 format CP0Control { 706 0x18: eret({{ 707 StatusReg status = Status; 708 ConfigReg config = Config; 709 SRSCtlReg srsCtl = SRSCtl; 710 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); | 334 } 335 336 format Branch { 337 0x4: decode RS_RT { 338 0x0: b({{ cond = 1; }}); 339 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 340 } 341 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); --- 352 unchanged lines hidden (view full) --- 694 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 695 0x1: decode FUNCTION { 696 format CP0Control { 697 0x18: eret({{ 698 StatusReg status = Status; 699 ConfigReg config = Config; 700 SRSCtlReg srsCtl = SRSCtl; 701 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); |
711 MipsISA::PCState pc = PCS; | |
712 if (status.erl == 1) { 713 status.erl = 0; | 702 if (status.erl == 1) { 703 status.erl = 0; |
714 pc.npc(ErrorEPC); | 704 NPC = ErrorEPC; |
715 // Need to adjust NNPC, otherwise things break | 705 // Need to adjust NNPC, otherwise things break |
716 pc.nnpc(ErrorEPC + sizeof(MachInst)); | 706 NNPC = ErrorEPC + sizeof(MachInst); |
717 } else { | 707 } else { |
718 pc.npc(EPC); | 708 NPC = EPC; |
719 // Need to adjust NNPC, otherwise things break | 709 // Need to adjust NNPC, otherwise things break |
720 pc.nnpc(EPC + sizeof(MachInst)); | 710 NNPC = EPC + sizeof(MachInst); |
721 status.exl = 0; 722 if (config.ar >=1 && 723 srsCtl.hss > 0 && 724 status.bev == 0) { 725 srsCtl.css = srsCtl.pss; 726 //xc->setShadowSet(srsCtl.pss); 727 } 728 } | 711 status.exl = 0; 712 if (config.ar >=1 && 713 srsCtl.hss > 0 && 714 status.bev == 0) { 715 srsCtl.css = srsCtl.pss; 716 //xc->setShadowSet(srsCtl.pss); 717 } 718 } |
729 PCS = pc; | |
730 LLFlag = 0; 731 Status = status; 732 SRSCtl = srsCtl; 733 }}, IsReturn, IsSerializing, IsERET); 734 735 0x1F: deret({{ 736 DebugReg debug = Debug; | 719 LLFlag = 0; 720 Status = status; 721 SRSCtl = srsCtl; 722 }}, IsReturn, IsSerializing, IsERET); 723 724 0x1F: deret({{ 725 DebugReg debug = Debug; |
737 MipsISA::PCState pc = PCS; | |
738 if (debug.dm == 1) { 739 debug.dm = 1; 740 debug.iexi = 0; | 726 if (debug.dm == 1) { 727 debug.dm = 1; 728 debug.iexi = 0; |
741 pc.npc(DEPC); | 729 NPC = DEPC; |
742 } else { | 730 } else { |
731 NPC = NPC; |
|
743 // Undefined; 744 } | 732 // Undefined; 733 } |
745 PCS = pc; | |
746 Debug = debug; 747 }}, IsReturn, IsSerializing, IsERET); 748 } 749 format CP0TLB { 750 0x01: tlbr({{ 751 MipsISA::PTE *PTEntry = 752 xc->tcBase()->getITBPtr()-> 753 getEntry(Index & 0x7FFFFFFF); --- 1834 unchanged lines hidden --- | 734 Debug = debug; 735 }}, IsReturn, IsSerializing, IsERET); 736 } 737 format CP0TLB { 738 0x01: tlbr({{ 739 MipsISA::PTE *PTEntry = 740 xc->tcBase()->getITBPtr()-> 741 getEntry(Index & 0x7FFFFFFF); --- 1834 unchanged lines hidden --- |