decoder.isa (6810:4fc450d6a54e) decoder.isa (7708:956ac83b0a58)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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2486#endif
2487 }
2488 }
2489 }
2490 }
2491
2492 0x4: decode OPCODE_LO {
2493 format LoadMemory {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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2486#endif
2487 }
2488 }
2489 }
2490 }
2491
2492 0x4: decode OPCODE_LO {
2493 format LoadMemory {
2494 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);
2495 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
2494 0x0: lb({{ Rt.sw = Mem.sb; }});
2495 0x1: lh({{ Rt.sw = Mem.sh; }});
2496 0x3: lw({{ Rt.sw = Mem.sw; }});
2496 0x3: lw({{ Rt.sw = Mem.sw; }});
2497 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT);
2498 0x5: lhu({{ Rt.uw = Mem.uh; }},
2499 mem_flags = NO_HALF_WORD_ALIGN_FAULT);
2497 0x4: lbu({{ Rt.uw = Mem.ub;}});
2498 0x5: lhu({{ Rt.uw = Mem.uh; }});
2500 }
2501
2502 format LoadUnalignedMemory {
2503 0x2: lwl({{
2504 uint32_t mem_shift = 24 - (8 * byte_offset);
2505 Rt.uw = mem_word << mem_shift | (Rt.uw & mask(mem_shift));
2506 }});
2507 0x6: lwr({{
2508 uint32_t mem_shift = 8 * byte_offset;
2509 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) |
2510 (mem_word >> mem_shift);
2511 }});
2512 }
2513 }
2514
2515 0x5: decode OPCODE_LO {
2516 format StoreMemory {
2499 }
2500
2501 format LoadUnalignedMemory {
2502 0x2: lwl({{
2503 uint32_t mem_shift = 24 - (8 * byte_offset);
2504 Rt.uw = mem_word << mem_shift | (Rt.uw & mask(mem_shift));
2505 }});
2506 0x6: lwr({{
2507 uint32_t mem_shift = 8 * byte_offset;
2508 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) |
2509 (mem_word >> mem_shift);
2510 }});
2511 }
2512 }
2513
2514 0x5: decode OPCODE_LO {
2515 format StoreMemory {
2517 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT);
2518 0x1: sh({{ Mem.uh = Rt<15:0>; }},
2519 mem_flags = NO_HALF_WORD_ALIGN_FAULT);
2516 0x0: sb({{ Mem.ub = Rt<7:0>; }});
2517 0x1: sh({{ Mem.uh = Rt<15:0>; }});
2520 0x3: sw({{ Mem.uw = Rt<31:0>; }});
2521 }
2522
2523 format StoreUnalignedMemory {
2524 0x2: swl({{
2525 uint32_t reg_shift = 24 - (8 * byte_offset);
2526 uint32_t mem_shift = 32 - reg_shift;
2527 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |

--- 44 unchanged lines hidden --- 		2518 0x3: sw({{ Mem.uw = Rt<31:0>; }});
2519 }
2520
2521 format StoreUnalignedMemory {
2522 0x2: swl({{
2523 uint32_t reg_shift = 24 - (8 * byte_offset);
2524 uint32_t mem_shift = 32 - reg_shift;
2525 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |

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