decoder.isa (6809:d99f7b0ac614) decoder.isa (6810:4fc450d6a54e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 2463 unchanged lines hidden (view full) ---

2472 dspac |= Rs.uw;
2473 dspctl = insertBits(dspctl, 5, 0,
2474 dspctl<5:0> + 32);
2475 }});
2476 }
2477 }
2478 }
2479 0x3: decode OP {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 2463 unchanged lines hidden (view full) ---

2472 dspac |= Rs.uw;
2473 dspctl = insertBits(dspctl, 5, 0,
2474 dspctl<5:0> + 32);
2475 }});
2476 }
2477 }
2478 }
2479 0x3: decode OP {
2480#if FULL_SYSTEM
2480 0x0: FailUnimpl::rdhwr();
2481 0x0: FailUnimpl::rdhwr();
2482#else
2483 0x0: decode RD {
2484 29: BasicOp::rdhwr({{ Rt = TpValue; }});
2485 }
2486#endif
2481 }
2482 }
2483 }
2484 }
2485
2486 0x4: decode OPCODE_LO {
2487 format LoadMemory {
2488 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);

--- 77 unchanged lines hidden --- 		2487 }
2488 }
2489 }
2490 }
2491
2492 0x4: decode OPCODE_LO {
2493 format LoadMemory {
2494 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);

--- 77 unchanged lines hidden ---