decoder.isa (6385:743ddf69eeed) decoder.isa (6809:d99f7b0ac614)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 2462 unchanged lines hidden (view full) ---

2471 dspac = dspac << 32;
2472 dspac |= Rs.uw;
2473 dspctl = insertBits(dspctl, 5, 0,
2474 dspctl<5:0> + 32);
2475 }});
2476 }
2477 }
2478 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 2462 unchanged lines hidden (view full) ---

2471 dspac = dspac << 32;
2472 dspac |= Rs.uw;
2473 dspctl = insertBits(dspctl, 5, 0,
2474 dspctl<5:0> + 32);
2475 }});
2476 }
2477 }
2478 }
2479 0x3: decode OP_HI {
2480 0x2: decode OP_LO {
2481 0x3: FailUnimpl::rdhwr();
2482 }
2479 0x3: decode OP {
2480 0x0: FailUnimpl::rdhwr();
2483 }
2484 }
2485 }
2486 }
2487
2488 0x4: decode OPCODE_LO {
2489 format LoadMemory {
2490 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);

--- 77 unchanged lines hidden --- 		2481 }
2482 }
2483 }
2484 }
2485
2486 0x4: decode OPCODE_LO {
2487 format LoadMemory {
2488 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);

--- 77 unchanged lines hidden ---