decoder.isa (6383:31c067ae3331) | decoder.isa (6384:5209002cb6d5) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 32 unchanged lines hidden (view full) --- 41// 42decode OPCODE_HI default Unknown::unknown() { 43 //Table A-2 44 0x0: decode OPCODE_LO { 45 0x0: decode FUNCTION_HI { 46 0x0: decode FUNCTION_LO { 47 0x1: decode MOVCI { 48 format BasicOp { | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 32 unchanged lines hidden (view full) --- 41// 42decode OPCODE_HI default Unknown::unknown() { 43 //Table A-2 44 0x0: decode OPCODE_LO { 45 0x0: decode FUNCTION_HI { 46 0x0: decode FUNCTION_LO { 47 0x1: decode MOVCI { 48 format BasicOp { |
49 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }}); 50 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }}); | 49 0: movf({{ 50 Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; 51 }}); 52 1: movt({{ 53 Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; 54 }}); |
51 } 52 } 53 54 format BasicOp { 55 //Table A-3 Note: "Specific encodings of the rd, rs, and 56 //rt fields are used to distinguish SLL, SSNOP, and EHB 57 //functions 58 0x0: decode RS { --- 5 unchanged lines hidden (view full) --- 64 default: sll({{ Rd = Rt.uw << SA; }}); 65 } 66 } 67 68 0x2: decode RS_SRL { 69 0x0:decode SRL { 70 0: srl({{ Rd = Rt.uw >> SA; }}); 71 | 55 } 56 } 57 58 format BasicOp { 59 //Table A-3 Note: "Specific encodings of the rd, rs, and 60 //rt fields are used to distinguish SLL, SSNOP, and EHB 61 //functions 62 0x0: decode RS { --- 5 unchanged lines hidden (view full) --- 68 default: sll({{ Rd = Rt.uw << SA; }}); 69 } 70 } 71 72 0x2: decode RS_SRL { 73 0x0:decode SRL { 74 0: srl({{ Rd = Rt.uw >> SA; }}); 75 |
72 //Hardcoded assuming 32-bit ISA, probably need parameter here 73 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); | 76 //Hardcoded assuming 32-bit ISA, 77 //probably need parameter here 78 1: rotr({{ 79 Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA); 80 }}); |
74 } 75 } 76 77 0x3: decode RS { 78 0x0: sra({{ 79 uint32_t temp = Rt >> SA; 80 if ( (Rt & 0x80000000) > 0 ) { 81 uint32_t mask = 0x80000000; --- 6 unchanged lines hidden (view full) --- 88 }}); 89 } 90 91 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 92 93 0x6: decode SRLV { 94 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 95 | 81 } 82 } 83 84 0x3: decode RS { 85 0x0: sra({{ 86 uint32_t temp = Rt >> SA; 87 if ( (Rt & 0x80000000) > 0 ) { 88 uint32_t mask = 0x80000000; --- 6 unchanged lines hidden (view full) --- 95 }}); 96 } 97 98 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 99 100 0x6: decode SRLV { 101 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 102 |
96 //Hardcoded assuming 32-bit ISA, probably need parameter here 97 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); | 103 //Hardcoded assuming 32-bit ISA, 104 //probably need parameter here 105 1: rotrv({{ 106 Rd = (Rt.uw << (32 - Rs<4:0>)) | 107 (Rt.uw >> Rs<4:0>); 108 }}); |
98 } 99 100 0x7: srav({{ 101 int shift_amt = Rs<4:0>; 102 103 uint32_t temp = Rt >> shift_amt; 104 | 109 } 110 111 0x7: srav({{ 112 int shift_amt = Rs<4:0>; 113 114 uint32_t temp = Rt >> shift_amt; 115 |
105 if ( (Rt & 0x80000000) > 0 ) { 106 uint32_t mask = 0x80000000; 107 for(int i=0; i < shift_amt; i++) { 108 temp |= mask; 109 mask = mask >> 1; 110 } | 116 if ((Rt & 0x80000000) > 0) { 117 uint32_t mask = 0x80000000; 118 for (int i = 0; i < shift_amt; i++) { 119 temp |= mask; 120 mask = mask >> 1; |
111 } | 121 } |
112 | 122 } |
113 Rd = temp; 114 }}); 115 } 116 } 117 118 0x1: decode FUNCTION_LO { 119 //Table A-3 Note: "Specific encodings of the hint field are 120 //used to distinguish JR from JR.HB and JALR from JALR.HB" --- 23 unchanged lines hidden (view full) --- 144 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall); 145 } 146 } 147 148 format BasicOp { 149 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 150 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 151#if FULL_SYSTEM | 123 Rd = temp; 124 }}); 125 } 126 } 127 128 0x1: decode FUNCTION_LO { 129 //Table A-3 Note: "Specific encodings of the hint field are 130 //used to distinguish JR from JR.HB and JALR from JALR.HB" --- 23 unchanged lines hidden (view full) --- 154 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall); 155 } 156 } 157 158 format BasicOp { 159 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 160 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 161#if FULL_SYSTEM |
152 0x4: syscall({{ 153 fault = new SystemCallFault(); 154 }}); | 162 0x4: syscall({{ fault = new SystemCallFault(); }}); |
155#else 156 0x4: syscall({{ xc->syscall(R2); }}, 157 IsSerializeAfter, IsNonSpeculative); 158#endif 159 0x7: sync({{ ; }}, IsMemBarrier); 160 0x5: break({{fault = new BreakpointFault();}}); 161 } 162 163 } 164 165 0x2: decode FUNCTION_LO { | 163#else 164 0x4: syscall({{ xc->syscall(R2); }}, 165 IsSerializeAfter, IsNonSpeculative); 166#endif 167 0x7: sync({{ ; }}, IsMemBarrier); 168 0x5: break({{fault = new BreakpointFault();}}); 169 } 170 171 } 172 173 0x2: decode FUNCTION_LO { |
166 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess); | 174 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, 175 IntMultOp, IsIprAccess); |
167 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); | 176 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); |
168 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess); | 177 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, 178 IntMultOp, IsIprAccess); |
169 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 170 } 171 172 0x3: decode FUNCTION_LO { 173 format HiLoRdSelValOp { 174 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp); 175 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp); 176 } 177 178 format HiLoOp { | 179 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 180 } 181 182 0x3: decode FUNCTION_LO { 183 format HiLoRdSelValOp { 184 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp); 185 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp); 186 } 187 188 format HiLoOp { |
179 0x2: div({{ if (Rt.sd != 0) { 180 HI0 = Rs.sd % Rt.sd; 181 LO0 = Rs.sd / Rt.sd; 182 } | 189 0x2: div({{ 190 if (Rt.sd != 0) { 191 HI0 = Rs.sd % Rt.sd; 192 LO0 = Rs.sd / Rt.sd; 193 } |
183 }}, IntDivOp); 184 | 194 }}, IntDivOp); 195 |
185 0x3: divu({{ if (Rt.ud != 0) { 186 HI0 = Rs.ud % Rt.ud; 187 LO0 = Rs.ud / Rt.ud; 188 } | 196 0x3: divu({{ 197 if (Rt.ud != 0) { 198 HI0 = Rs.ud % Rt.ud; 199 LO0 = Rs.ud / Rt.ud; 200 } |
189 }}, IntDivOp); 190 } 191 } 192 193 0x4: decode HINT { 194 0x0: decode FUNCTION_LO { 195 format IntOp { | 201 }}, IntDivOp); 202 } 203 } 204 205 0x4: decode HINT { 206 0x0: decode FUNCTION_LO { 207 format IntOp { |
196 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */ 197 int64_t Src1 = Rs.sw; 198 int64_t Src2 = Rt.sw; 199 int64_t temp_result; 200#if FULL_SYSTEM 201 if(((Src1 >> 31) & 1) == 1) 202 Src1 |= 0x100000000LL; | 208 0x0: add({{ 209 /* More complicated since an ADD can cause 210 an arithmetic overflow exception */ 211 int64_t Src1 = Rs.sw; 212 int64_t Src2 = Rt.sw; 213 int64_t temp_result; 214#if FULL_SYSTEM 215 if (((Src1 >> 31) & 1) == 1) 216 Src1 |= 0x100000000LL; |
203#endif | 217#endif |
204 temp_result = Src1 + Src2; 205#if FULL_SYSTEM 206 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ | 218 temp_result = Src1 + Src2; 219#if FULL_SYSTEM 220 if (bits(temp_result, 31) == 221 bits(temp_result, 32)) { |
207#endif | 222#endif |
208 Rd.sw = temp_result; 209#if FULL_SYSTEM 210 } else{ 211 fault = new ArithmeticFault(); 212 } | 223 Rd.sw = temp_result; 224#if FULL_SYSTEM 225 } else { 226 fault = new ArithmeticFault(); 227 } |
213#endif | 228#endif |
214 215 }}); | 229 }}); |
216 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 217 0x2: sub({{ | 230 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 231 0x2: sub({{ |
218 /* More complicated since an SUB can cause an arithmetic overflow exception */ 219 int64_t Src1 = Rs.sw; 220 int64_t Src2 = Rt.sw; 221 int64_t temp_result = Src1 - Src2; | 232 /* More complicated since an SUB can cause 233 an arithmetic overflow exception */ 234 int64_t Src1 = Rs.sw; 235 int64_t Src2 = Rt.sw; 236 int64_t temp_result = Src1 - Src2; |
222#if FULL_SYSTEM | 237#if FULL_SYSTEM |
223 if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){ | 238 if (bits(temp_result, 31) == 239 bits(temp_result, 32)) { |
224#endif | 240#endif |
225 Rd.sw = temp_result; | 241 Rd.sw = temp_result; |
226#if FULL_SYSTEM | 242#if FULL_SYSTEM |
227 } else{ 228 fault = new ArithmeticFault(); 229 } | 243 } else { 244 fault = new ArithmeticFault(); 245 } |
230#endif | 246#endif |
231 }}); 232 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 233 0x4: and({{ Rd = Rs & Rt;}}); 234 0x5: or({{ Rd = Rs | Rt;}}); 235 0x6: xor({{ Rd = Rs ^ Rt;}}); 236 0x7: nor({{ Rd = ~(Rs | Rt);}}); | 247 }}); 248 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw; }}); 249 0x4: and({{ Rd = Rs & Rt; }}); 250 0x5: or({{ Rd = Rs | Rt; }}); 251 0x6: xor({{ Rd = Rs ^ Rt; }}); 252 0x7: nor({{ Rd = ~(Rs | Rt); }}); |
237 } 238 } 239 } 240 241 0x5: decode HINT { 242 0x0: decode FUNCTION_LO { 243 format IntOp{ | 253 } 254 } 255 } 256 257 0x5: decode HINT { 258 0x0: decode FUNCTION_LO { 259 format IntOp{ |
244 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 245 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); | 260 0x2: slt({{ Rd.sw = (Rs.sw < Rt.sw) ? 1 : 0 }}); 261 0x3: sltu({{ Rd.uw = (Rs.uw < Rt.uw) ? 1 : 0 }}); |
246 } 247 } 248 } 249 250 0x6: decode FUNCTION_LO { 251 format Trap { 252 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 253 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); --- 13 unchanged lines hidden (view full) --- 267 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 268 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 269 } 270 } 271 272 0x1: decode REGIMM_LO { 273 format TrapImm { 274 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }}); | 262 } 263 } 264 } 265 266 0x6: decode FUNCTION_LO { 267 format Trap { 268 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 269 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); --- 13 unchanged lines hidden (view full) --- 283 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 284 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 285 } 286 } 287 288 0x1: decode REGIMM_LO { 289 format TrapImm { 290 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }}); |
275 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }}); | 291 0x1: tgeiu({{ 292 cond = (Rs.uw >= (uint32_t)(int32_t)(int16_t)INTIMM); 293 }}); |
276 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }}); | 294 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }}); |
277 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }}); 278 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}}); 279 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}}); | 295 0x3: tltiu({{ 296 cond = (Rs.uw < (uint32_t)(int32_t)(int16_t)INTIMM); 297 }}); 298 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM); }}); 299 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM); }}); |
280 } 281 } 282 283 0x2: decode REGIMM_LO { 284 format Branch { 285 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 286 0x1: decode RS { 287 0x0: bal ({{ cond = 1; }}, IsCall, Link); 288 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 289 } 290 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 291 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 292 } 293 } 294 295 0x3: decode REGIMM_LO { | 300 } 301 } 302 303 0x2: decode REGIMM_LO { 304 format Branch { 305 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 306 0x1: decode RS { 307 0x0: bal ({{ cond = 1; }}, IsCall, Link); 308 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 309 } 310 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 311 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 312 } 313 } 314 315 0x3: decode REGIMM_LO { |
296 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL) | 316 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field 317 // (DSP ASE MANUAL) |
297 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 298 format WarnUnimpl { 299 0x7: synci(); 300 } 301 } 302 } 303 304 format Jump { | 318 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 319 format WarnUnimpl { 320 0x7: synci(); 321 } 322 } 323 } 324 325 format Jump { |
305 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 306 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall, 307 Link); | 326 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}); 327 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, 328 IsCall, Link); |
308 } 309 310 format Branch { 311 0x4: decode RS_RT { 312 0x0: b({{ cond = 1; }}); 313 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 314 } 315 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 316 0x6: blez({{ cond = (Rs.sw <= 0); }}); 317 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 318 } 319 } 320 321 0x1: decode OPCODE_LO { 322 format IntImmOp { 323 0x0: addi({{ | 329 } 330 331 format Branch { 332 0x4: decode RS_RT { 333 0x0: b({{ cond = 1; }}); 334 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 335 } 336 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 337 0x6: blez({{ cond = (Rs.sw <= 0); }}); 338 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 339 } 340 } 341 342 0x1: decode OPCODE_LO { 343 format IntImmOp { 344 0x0: addi({{ |
324 int64_t Src1 = Rs.sw; 325 int64_t Src2 = imm; 326 int64_t temp_result; | 345 int64_t Src1 = Rs.sw; 346 int64_t Src2 = imm; 347 int64_t temp_result; |
327#if FULL_SYSTEM | 348#if FULL_SYSTEM |
328 if(((Src1 >> 31) & 1) == 1) 329 Src1 |= 0x100000000LL; | 349 if (((Src1 >> 31) & 1) == 1) 350 Src1 |= 0x100000000LL; |
330#endif | 351#endif |
331 temp_result = Src1 + Src2; | 352 temp_result = Src1 + Src2; |
332#if FULL_SYSTEM | 353#if FULL_SYSTEM |
333 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ | 354 if (bits(temp_result, 31) == bits(temp_result, 32)) { |
334#endif | 355#endif |
335 Rt.sw = temp_result; | 356 Rt.sw = temp_result; |
336#if FULL_SYSTEM | 357#if FULL_SYSTEM |
337 } else{ 338 fault = new ArithmeticFault(); 339 } | 358 } else { 359 fault = new ArithmeticFault(); 360 } |
340#endif | 361#endif |
341 }}); 342 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 343 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); | 362 }}); 363 0x1: addiu({{ Rt.sw = Rs.sw + imm; }}); 364 0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }}); |
344 345 //Edited to include MIPS AVP Pass/Fail instructions and 346 //default to the sltiu instruction 347 0x3: decode RS_RT_INTIMM { | 365 366 //Edited to include MIPS AVP Pass/Fail instructions and 367 //default to the sltiu instruction 368 0x3: decode RS_RT_INTIMM { |
348 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }}); 349 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }}); 350 default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); | 369 0xabc1: BasicOp::fail({{ 370 exitSimLoop("AVP/SRVP Test Failed"); 371 }}); 372 0xabc2: BasicOp::pass({{ 373 exitSimLoop("AVP/SRVP Test Passed"); 374 }}); 375 default: sltiu({{ 376 Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0; 377 }}); |
351 } 352 | 378 } 379 |
353 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 354 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 355 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); | 380 0x4: andi({{ Rt.sw = Rs.sw & zextImm; }}); 381 0x5: ori({{ Rt.sw = Rs.sw | zextImm; }}); 382 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm; }}); |
356 357 0x7: decode RS { | 383 384 0x7: decode RS { |
358 0x0: lui({{ Rt = imm << 16}}); | 385 0x0: lui({{ Rt = imm << 16; }}); |
359 } 360 } 361 } 362 363 0x2: decode OPCODE_LO { 364 //Table A-11 MIPS32 COP0 Encoding of rs Field 365 0x0: decode RS_MSB { 366 0x0: decode RS { | 386 } 387 } 388 } 389 390 0x2: decode OPCODE_LO { 391 //Table A-11 MIPS32 COP0 Encoding of rs Field 392 0x0: decode RS_MSB { 393 0x0: decode RS { |
367 format CP0Control { 368 0x0: mfc0({{ 369 Config3Reg config3 = Config3; 370 PageGrainReg pageGrain = PageGrain; 371 Rt = CP0_RD_SEL; 372 /* Hack for PageMask */ 373 if (RD == 5) { 374 // PageMask 375 if(config3.sp == 0 || pageGrain.esp == 0) 376 Rt &= 0xFFFFE7FF; 377 } 378 }}); 379 0x4: mtc0({{ 380 CP0_RD_SEL = Rt; 381 CauseReg cause = Cause; 382 IntCtlReg intCtl = IntCtl; 383 if (RD == 11) { 384 // Compare 385 if (cause.ti == 1) { 386 cause.ti = 0; 387 int offset = 10; // corresponding to cause.ip0 388 offset += intCtl.ipti - 2; 389 replaceBits(cause, offset, offset, 0); 390 } 391 } 392 Cause = cause; 393 }}); 394 } 395 format CP0Unimpl { 396 0x1: dmfc0(); 397 0x5: dmtc0(); 398 default: unknown(); 399 } 400 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions | 394 format CP0Control { 395 0x0: mfc0({{ 396 Config3Reg config3 = Config3; 397 PageGrainReg pageGrain = PageGrain; 398 Rt = CP0_RD_SEL; 399 /* Hack for PageMask */ 400 if (RD == 5) { 401 // PageMask 402 if (config3.sp == 0 || pageGrain.esp == 0) 403 Rt &= 0xFFFFE7FF; 404 } 405 }}); 406 0x4: mtc0({{ 407 CP0_RD_SEL = Rt; 408 CauseReg cause = Cause; 409 IntCtlReg intCtl = IntCtl; 410 if (RD == 11) { 411 // Compare 412 if (cause.ti == 1) { 413 cause.ti = 0; 414 int offset = 10; // corresponding to cause.ip0 415 offset += intCtl.ipti - 2; 416 replaceBits(cause, offset, offset, 0); 417 } 418 } 419 Cause = cause; 420 }}); 421 } 422 format CP0Unimpl { 423 0x1: dmfc0(); 424 0x5: dmtc0(); 425 default: unknown(); 426 } 427 format MT_MFTR { 428 // Decode MIPS MT MFTR instruction into sub-instructions |
401 0x8: decode MT_U { 402 0x0: mftc0({{ 403 data = xc->readRegOtherThread((RT << 3 | SEL) + 404 Ctrl_Base_DepTag); 405 }}); 406 0x1: decode SEL { | 429 0x8: decode MT_U { 430 0x0: mftc0({{ 431 data = xc->readRegOtherThread((RT << 3 | SEL) + 432 Ctrl_Base_DepTag); 433 }}); 434 0x1: decode SEL { |
407 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }}); | 435 0x0: mftgpr({{ 436 data = xc->readRegOtherThread(RT); 437 }}); |
408 0x1: decode RT { 409 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }}); 410 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }}); 411 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }}); 412 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }}); 413 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }}); 414 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }}); 415 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }}); 416 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }}); 417 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }}); 418 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }}); 419 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }}); 420 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }}); 421 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }}); | 438 0x1: decode RT { 439 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }}); 440 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }}); 441 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }}); 442 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }}); 443 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }}); 444 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }}); 445 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }}); 446 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }}); 447 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }}); 448 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }}); 449 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }}); 450 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }}); 451 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }}); |
422 default: CP0Unimpl::unknown(); | 452 default: CP0Unimpl::unknown(); |
423 } 424 0x2: decode MT_H { 425 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 426 FP_Base_DepTag); | 453 } 454 0x2: decode MT_H { 455 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 456 FP_Base_DepTag); |
427 }}); | 457 }}); |
428 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 429 FP_Base_DepTag); | 458 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 459 FP_Base_DepTag); |
430 }}); 431 } 432 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR + | 460 }}); 461 } 462 0x3: cftc1({{ 463 uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR + |
433 FP_Base_DepTag); | 464 FP_Base_DepTag); |
434 switch (RT) 435 { 436 case 0: 437 data = xc->readRegOtherThread(FLOATREG_FIR + 438 Ctrl_Base_DepTag); 439 break; 440 case 25: 441 data = (fcsr_val & 0xFE000000 >> 24) 442 | (fcsr_val & 0x00800000 >> 23); 443 break; 444 case 26: 445 data = fcsr_val & 0x0003F07C; 446 break; 447 case 28: 448 data = (fcsr_val & 0x00000F80) 449 | (fcsr_val & 0x01000000 >> 21) 450 | (fcsr_val & 0x00000003); 451 break; 452 case 31: 453 data = fcsr_val; 454 break; 455 default: 456 fatal("FP Control Value (%d) Not Valid"); 457 } 458 }}); 459 default: CP0Unimpl::unknown(); | 465 switch (RT) { 466 case 0: 467 data = xc->readRegOtherThread(FLOATREG_FIR + 468 Ctrl_Base_DepTag); 469 break; 470 case 25: 471 data = (fcsr_val & 0xFE000000 >> 24) | 472 (fcsr_val & 0x00800000 >> 23); 473 break; 474 case 26: 475 data = fcsr_val & 0x0003F07C; 476 break; 477 case 28: 478 data = (fcsr_val & 0x00000F80) | 479 (fcsr_val & 0x01000000 >> 21) | 480 (fcsr_val & 0x00000003); 481 break; 482 case 31: 483 data = fcsr_val; 484 break; 485 default: 486 fatal("FP Control Value (%d) Not Valid"); 487 } 488 }}); 489 default: CP0Unimpl::unknown(); |
460 } | 490 } |
461 } | 491 } |
462 } 463 | 492 } 493 |
464 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions | 494 format MT_MTTR { 495 // Decode MIPS MT MTTR instruction into sub-instructions |
465 0xC: decode MT_U { 466 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, 467 Rt); 468 }}); 469 0x1: decode SEL { 470 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 471 0x1: decode RT { 472 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt); --- 26 unchanged lines hidden (view full) --- 499 Rt); 500 }}); 501 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3, 502 Rt); 503 }}); 504 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt); 505 }}); 506 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); | 496 0xC: decode MT_U { 497 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, 498 Rt); 499 }}); 500 0x1: decode SEL { 501 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 502 0x1: decode RT { 503 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt); --- 26 unchanged lines hidden (view full) --- 530 Rt); 531 }}); 532 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3, 533 Rt); 534 }}); 535 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt); 536 }}); 537 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); |
507 default: CP0Unimpl::unknown(); | 538 default: CP0Unimpl::unknown(); |
508 509 } | 539 540 } |
510 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + 511 FP_Base_DepTag); 512 data = insertBits(data, top_bit, bottom_bit, Rt); 513 xc->setRegOtherThread(RD + FP_Base_DepTag, data); 514 }}); 515 0x3: cttc1({{ uint32_t data; 516 switch (RD) 517 { 518 case 25: 519 data = 0 | (Rt.uw<7:1> << 25) // move 31...25 520 | (FCSR & 0x01000000) // bit 24 521 | (FCSR & 0x004FFFFF);// bit 22...0 522 break; 523 524 case 26: 525 data = 0 | (FCSR & 0xFFFC0000) // move 31...18 526 | Rt.uw<17:12> << 12 // bit 17...12 527 | (FCSR & 0x00000F80) << 7// bit 11...7 528 | Rt.uw<6:2> << 2 // bit 6...2 529 | (FCSR & 0x00000002); // bit 1...0 530 break; 531 532 case 28: 533 data = 0 | (FCSR & 0xFE000000) // move 31...25 534 | Rt.uw<2:2> << 24 // bit 24 535 | (FCSR & 0x00FFF000) << 23// bit 23...12 536 | Rt.uw<11:7> << 7 // bit 24 537 | (FCSR & 0x000007E) 538 | Rt.uw<1:0>;// bit 22...0 539 break; 540 541 case 31: 542 data = Rt.uw; 543 break; 544 545 default: 546 panic("FP Control Value (%d) Not Available. Ignoring Access to" 547 "Floating Control Status Register", FS); 548 } 549 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); 550 }}); 551 default: CP0Unimpl::unknown(); | 541 0x2: mttc1({{ 542 uint64_t data = xc->readRegOtherThread(RD + 543 FP_Base_DepTag); 544 data = insertBits(data, top_bit, 545 bottom_bit, Rt); 546 xc->setRegOtherThread(RD + FP_Base_DepTag, 547 data); 548 }}); 549 0x3: cttc1({{ 550 uint32_t data; 551 switch (RD) { 552 case 25: 553 data = (Rt.uw<7:1> << 25) | // move 31-25 554 (FCSR & 0x01000000) | // bit 24 555 (FCSR & 0x004FFFFF); // bit 22-0 556 break; 557 case 26: 558 data = (FCSR & 0xFFFC0000) | // move 31-18 559 Rt.uw<17:12> << 12 | // bit 17-12 560 (FCSR & 0x00000F80) << 7 | // bit 11-7 561 Rt.uw<6:2> << 2 | // bit 6-2 562 (FCSR & 0x00000002); // bit 1...0 563 break; 564 case 28: 565 data = (FCSR & 0xFE000000) | // move 31-25 566 Rt.uw<2:2> << 24 | // bit 24 567 (FCSR & 0x00FFF000) << 23 | // bit 23-12 568 Rt.uw<11:7> << 7 | // bit 24 569 (FCSR & 0x000007E) | 570 Rt.uw<1:0>; // bit 22-0 571 break; 572 case 31: 573 data = Rt.uw; 574 break; 575 default: 576 panic("FP Control Value (%d) " 577 "Not Available. Ignoring " 578 "Access to Floating Control " 579 "Status Register", FS); 580 } 581 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); 582 }}); 583 default: CP0Unimpl::unknown(); |
552 } 553 } 554 } | 584 } 585 } 586 } |
555 556 | |
557 0xB: decode RD { 558 format MT_Control { 559 0x0: decode POS { 560 0x0: decode SEL { 561 0x1: decode SC { 562 0x0: dvpe({{ 563 MVPControlReg mvpControl = MVPControl; 564 VPEConf0Reg vpeConf0 = VPEConf0; --- 7 unchanged lines hidden (view full) --- 572 VPEConf0Reg vpeConf0 = VPEConf0; 573 Rt = MVPControl; 574 if (vpeConf0.mvp == 1) 575 mvpControl.evp = 1; 576 MVPControl = mvpControl; 577 }}); 578 default:CP0Unimpl::unknown(); 579 } | 587 0xB: decode RD { 588 format MT_Control { 589 0x0: decode POS { 590 0x0: decode SEL { 591 0x1: decode SC { 592 0x0: dvpe({{ 593 MVPControlReg mvpControl = MVPControl; 594 VPEConf0Reg vpeConf0 = VPEConf0; --- 7 unchanged lines hidden (view full) --- 602 VPEConf0Reg vpeConf0 = VPEConf0; 603 Rt = MVPControl; 604 if (vpeConf0.mvp == 1) 605 mvpControl.evp = 1; 606 MVPControl = mvpControl; 607 }}); 608 default:CP0Unimpl::unknown(); 609 } |
580 default:CP0Unimpl::unknown(); | 610 default:CP0Unimpl::unknown(); |
581 } | 611 } |
582 default:CP0Unimpl::unknown(); 583 } 584 | 612 default:CP0Unimpl::unknown(); 613 } |
585 0x1: decode POS { 586 0xF: decode SEL { 587 0x1: decode SC { 588 0x0: dmt({{ 589 VPEControlReg vpeControl = VPEControl; 590 Rt = vpeControl; 591 vpeControl.te = 0; 592 VPEControl = vpeControl; 593 }}); 594 0x1: emt({{ 595 VPEControlReg vpeControl = VPEControl; 596 Rt = vpeControl; 597 vpeControl.te = 1; 598 VPEControl = vpeControl; 599 }}); 600 default:CP0Unimpl::unknown(); 601 } | 614 0x1: decode POS { 615 0xF: decode SEL { 616 0x1: decode SC { 617 0x0: dmt({{ 618 VPEControlReg vpeControl = VPEControl; 619 Rt = vpeControl; 620 vpeControl.te = 0; 621 VPEControl = vpeControl; 622 }}); 623 0x1: emt({{ 624 VPEControlReg vpeControl = VPEControl; 625 Rt = vpeControl; 626 vpeControl.te = 1; 627 VPEControl = vpeControl; 628 }}); 629 default:CP0Unimpl::unknown(); 630 } |
602 default:CP0Unimpl::unknown(); | 631 default:CP0Unimpl::unknown(); |
603 } 604 default:CP0Unimpl::unknown(); 605 } 606 } 607 0xC: decode POS { | 632 } 633 default:CP0Unimpl::unknown(); 634 } 635 } 636 0xC: decode POS { |
608 0x0: decode SC { 609 0x0: CP0Control::di({{ 610 StatusReg status = Status; 611 ConfigReg config = Config; 612 // Rev 2.0 or beyond? 613 if (config.ar >= 1) { 614 Rt = status; 615 status.ie = 0; 616 } else { 617 // Enable this else branch once we 618 // actually set values for Config on init 619 fault = new ReservedInstructionFault(); 620 } 621 Status = status; 622 }}); 623 0x1: CP0Control::ei({{ 624 StatusReg status = Status; 625 ConfigReg config = Config; 626 if (config.ar >= 1) { 627 Rt = status; 628 status.ie = 1; 629 } else { 630 fault = new ReservedInstructionFault(); 631 } 632 }}); 633 default:CP0Unimpl::unknown(); 634 } | 637 0x0: decode SC { 638 0x0: CP0Control::di({{ 639 StatusReg status = Status; 640 ConfigReg config = Config; 641 // Rev 2.0 or beyond? 642 if (config.ar >= 1) { 643 Rt = status; 644 status.ie = 0; 645 } else { 646 // Enable this else branch once we 647 // actually set values for Config on init 648 fault = new ReservedInstructionFault(); 649 } 650 Status = status; 651 }}); 652 0x1: CP0Control::ei({{ 653 StatusReg status = Status; 654 ConfigReg config = Config; 655 if (config.ar >= 1) { 656 Rt = status; 657 status.ie = 1; 658 } else { 659 fault = new ReservedInstructionFault(); 660 } 661 }}); 662 default:CP0Unimpl::unknown(); 663 } |
635 } | 664 } |
636 default: CP0Unimpl::unknown(); | 665 default: CP0Unimpl::unknown(); |
637 } 638 format CP0Control { 639 0xA: rdpgpr({{ 640 ConfigReg config = Config; 641 if (config.ar >= 1) { 642 // Rev 2 of the architecture 643 panic("Shadow Sets Not Fully Implemented.\n"); 644 } else { --- 5 unchanged lines hidden (view full) --- 650 if (config.ar >= 1) { 651 // Rev 2 of the architecture 652 panic("Shadow Sets Not Fully Implemented.\n"); 653 } else { 654 fault = new ReservedInstructionFault(); 655 } 656 }}); 657 } | 666 } 667 format CP0Control { 668 0xA: rdpgpr({{ 669 ConfigReg config = Config; 670 if (config.ar >= 1) { 671 // Rev 2 of the architecture 672 panic("Shadow Sets Not Fully Implemented.\n"); 673 } else { --- 5 unchanged lines hidden (view full) --- 679 if (config.ar >= 1) { 680 // Rev 2 of the architecture 681 panic("Shadow Sets Not Fully Implemented.\n"); 682 } else { 683 fault = new ReservedInstructionFault(); 684 } 685 }}); 686 } |
687 } |
|
658 | 688 |
659 } 660 | |
661 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 662 0x1: decode FUNCTION { | 689 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 690 0x1: decode FUNCTION { |
663 format CP0Control { 664 0x18: eret({{ 665 StatusReg status = Status; 666 ConfigReg config = Config; 667 SRSCtlReg srsCtl = SRSCtl; 668 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 669 if (status.erl == 1) { 670 status.erl = 0; 671 NPC = ErrorEPC; 672 // Need to adjust NNPC, otherwise things break 673 NNPC = ErrorEPC + sizeof(MachInst); 674 } else { 675 NPC = EPC; 676 // Need to adjust NNPC, otherwise things break 677 NNPC = EPC + sizeof(MachInst); 678 status.exl = 0; 679 if (config.ar >=1 && 680 srsCtl.hss > 0 && 681 status.bev == 0) { 682 srsCtl.css = srsCtl.pss; 683 //xc->setShadowSet(srsCtl.pss); | 691 format CP0Control { 692 0x18: eret({{ 693 StatusReg status = Status; 694 ConfigReg config = Config; 695 SRSCtlReg srsCtl = SRSCtl; 696 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 697 if (status.erl == 1) { 698 status.erl = 0; 699 NPC = ErrorEPC; 700 // Need to adjust NNPC, otherwise things break 701 NNPC = ErrorEPC + sizeof(MachInst); 702 } else { 703 NPC = EPC; 704 // Need to adjust NNPC, otherwise things break 705 NNPC = EPC + sizeof(MachInst); 706 status.exl = 0; 707 if (config.ar >=1 && 708 srsCtl.hss > 0 && 709 status.bev == 0) { 710 srsCtl.css = srsCtl.pss; 711 //xc->setShadowSet(srsCtl.pss); 712 } |
684 } | 713 } |
685 } 686 LLFlag = 0; 687 Status = status; 688 SRSCtl = srsCtl; 689 }},IsReturn,IsSerializing,IsERET); | 714 LLFlag = 0; 715 Status = status; 716 SRSCtl = srsCtl; 717 }}, IsReturn, IsSerializing, IsERET); |
690 | 718 |
691 0x1F: deret({{ 692 DebugReg debug = Debug; 693 if (debug.dm == 1) { 694 debug.dm = 1; 695 debug.iexi = 0; 696 NPC = DEPC; 697 } else { 698 // Undefined; 699 } 700 Debug = debug; 701 }}, IsReturn, IsSerializing, IsERET); 702 } 703 format CP0TLB { 704 0x01: tlbr({{ 705 MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF); 706 if(PTEntry == NULL) 707 { 708 fatal("Invalid PTE Entry received on a TLBR instruction\n"); 709 } 710 /* Setup PageMask */ 711 PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11 712 /* Setup EntryHi */ 713 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 714 /* Setup Entry Lo0 */ 715 EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G); 716 /* Setup Entry Lo1 */ 717 EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G); 718 }}); // Need to hook up to TLB | 719 0x1F: deret({{ 720 DebugReg debug = Debug; 721 if (debug.dm == 1) { 722 debug.dm = 1; 723 debug.iexi = 0; 724 NPC = DEPC; 725 } else { 726 // Undefined; 727 } 728 Debug = debug; 729 }}, IsReturn, IsSerializing, IsERET); 730 } 731 format CP0TLB { 732 0x01: tlbr({{ 733 MipsISA::PTE *PTEntry = 734 xc->tcBase()->getITBPtr()-> 735 getEntry(Index & 0x7FFFFFFF); 736 if (PTEntry == NULL) { 737 fatal("Invalid PTE Entry received on " 738 "a TLBR instruction\n"); 739 } 740 /* Setup PageMask */ 741 // If 1KB pages are not enabled, a read of PageMask 742 // must return 0b00 in bits 12, 11 743 PageMask = (PTEntry->Mask << 11); 744 /* Setup EntryHi */ 745 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 746 /* Setup Entry Lo0 */ 747 EntryLo0 = ((PTEntry->PFN0 << 6) | 748 (PTEntry->C0 << 3) | 749 (PTEntry->D0 << 2) | 750 (PTEntry->V0 << 1) | 751 PTEntry->G); 752 /* Setup Entry Lo1 */ 753 EntryLo1 = ((PTEntry->PFN1 << 6) | 754 (PTEntry->C1 << 3) | 755 (PTEntry->D1 << 2) | 756 (PTEntry->V1 << 1) | 757 PTEntry->G); 758 }}); // Need to hook up to TLB |
719 | 759 |
720 0x02: tlbwi({{ 721 //Create PTE 722 MipsISA::PTE NewEntry; 723 //Write PTE 724 NewEntry.Mask = (Addr)(PageMask >> 11); 725 NewEntry.VPN = (Addr)(EntryHi >> 11); 726 /* PageGrain _ ESP Config3 _ SP */ 727 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) { 728 // If 1KB pages are *NOT* enabled, lowest bits of the 729 // mask are 0b11 for TLB writes 730 NewEntry.Mask |= 0x3; 731 // Reset bits 0 and 1 if 1KB pages are not enabled 732 NewEntry.VPN &= 0xFFFFFFFC; 733 } 734 NewEntry.asid = (uint8_t)(EntryHi & 0xFF); | 760 0x02: tlbwi({{ 761 //Create PTE 762 MipsISA::PTE newEntry; 763 //Write PTE 764 newEntry.Mask = (Addr)(PageMask >> 11); 765 newEntry.VPN = (Addr)(EntryHi >> 11); 766 /* PageGrain _ ESP Config3 _ SP */ 767 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 768 // If 1KB pages are *NOT* enabled, lowest bits of 769 // the mask are 0b11 for TLB writes 770 newEntry.Mask |= 0x3; 771 // Reset bits 0 and 1 if 1KB pages are not enabled 772 newEntry.VPN &= 0xFFFFFFFC; 773 } 774 newEntry.asid = (uint8_t)(EntryHi & 0xFF); |
735 | 775 |
736 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 737 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 738 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 739 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 740 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 741 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 742 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 743 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 744 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 745 /* Now, compute the AddrShiftAmount and OffsetMask - TLB 746 optimizations */ 747 /* Addr Shift Amount for 1KB or larger pages */ 748 if ((NewEntry.Mask & 0xFFFF) == 3) { 749 NewEntry.AddrShiftAmount = 12; 750 } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) { 751 NewEntry.AddrShiftAmount = 10; 752 } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) { 753 NewEntry.AddrShiftAmount = 14; 754 } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) { 755 NewEntry.AddrShiftAmount = 16; 756 } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) { 757 NewEntry.AddrShiftAmount = 18; 758 } else if ((NewEntry.Mask & 0xFF00) == 0x0300) { 759 NewEntry.AddrShiftAmount = 20; 760 } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) { 761 NewEntry.AddrShiftAmount = 22; 762 } else if ((NewEntry.Mask & 0xF000) == 0x3000) { 763 NewEntry.AddrShiftAmount = 24; 764 } else if ((NewEntry.Mask & 0xC000) == 0xC000) { 765 NewEntry.AddrShiftAmount = 26; 766 } else if ((NewEntry.Mask & 0x30000) == 0x30000) { 767 NewEntry.AddrShiftAmount = 28; 768 } else { 769 fatal("Invalid Mask Pattern Detected!\n"); 770 } 771 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1); | 776 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 777 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 778 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 779 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 780 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 781 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 782 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 783 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 784 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 785 /* Now, compute the AddrShiftAmount and OffsetMask - 786 TLB optimizations */ 787 /* Addr Shift Amount for 1KB or larger pages */ 788 if ((newEntry.Mask & 0xFFFF) == 3) { 789 newEntry.AddrShiftAmount = 12; 790 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 791 newEntry.AddrShiftAmount = 10; 792 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 793 newEntry.AddrShiftAmount = 14; 794 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 795 newEntry.AddrShiftAmount = 16; 796 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 797 newEntry.AddrShiftAmount = 18; 798 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 799 newEntry.AddrShiftAmount = 20; 800 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 801 newEntry.AddrShiftAmount = 22; 802 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 803 newEntry.AddrShiftAmount = 24; 804 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 805 newEntry.AddrShiftAmount = 26; 806 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 807 newEntry.AddrShiftAmount = 28; 808 } else { 809 fatal("Invalid Mask Pattern Detected!\n"); 810 } 811 newEntry.OffsetMask = 812 (1 << newEntry.AddrShiftAmount) - 1; |
772 | 813 |
773 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 774 Config3Reg config3 = Config3; 775 PageGrainReg pageGrain = PageGrain; 776 int SP = 0; 777 if (bits(config3, config3.sp) == 1 && 778 bits(pageGrain, pageGrain.esp) == 1) { 779 SP = 1; 780 } 781 IndexReg index = Index; 782 Ptr->insertAt(NewEntry, Index & 0x7FFFFFFF, SP); 783 }}); 784 0x06: tlbwr({{ 785 //Create PTE 786 MipsISA::PTE NewEntry; 787 //Write PTE 788 NewEntry.Mask = (Addr)(PageMask >> 11); 789 NewEntry.VPN = (Addr)(EntryHi >> 11); 790 /* PageGrain _ ESP Config3 _ SP */ 791 if (((PageGrain >> 28) & 1) == 0 || 792 (( Config3 >> 4) & 1) ==0) { 793 // If 1KB pages are *NOT* enabled, lowest bits of 794 // the mask are 0b11 for TLB writes 795 NewEntry.Mask |= 0x3; 796 // Reset bits 0 and 1 if 1KB pages are not enabled 797 NewEntry.VPN &= 0xFFFFFFFC; 798 } 799 NewEntry.asid = (uint8_t)(EntryHi & 0xFF); | 814 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 815 Config3Reg config3 = Config3; 816 PageGrainReg pageGrain = PageGrain; 817 int SP = 0; 818 if (bits(config3, config3.sp) == 1 && 819 bits(pageGrain, pageGrain.esp) == 1) { 820 SP = 1; 821 } 822 IndexReg index = Index; 823 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 824 }}); 825 0x06: tlbwr({{ 826 //Create PTE 827 MipsISA::PTE newEntry; 828 //Write PTE 829 newEntry.Mask = (Addr)(PageMask >> 11); 830 newEntry.VPN = (Addr)(EntryHi >> 11); 831 /* PageGrain _ ESP Config3 _ SP */ 832 if (bits(PageGrain, 28) == 0 || 833 bits(Config3, 4) == 0) { 834 // If 1KB pages are *NOT* enabled, lowest bits of 835 // the mask are 0b11 for TLB writes 836 newEntry.Mask |= 0x3; 837 // Reset bits 0 and 1 if 1KB pages are not enabled 838 newEntry.VPN &= 0xFFFFFFFC; 839 } 840 newEntry.asid = (uint8_t)(EntryHi & 0xFF); |
800 | 841 |
801 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 802 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 803 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 804 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 805 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 806 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 807 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 808 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 809 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 810 /* Now, compute the AddrShiftAmount and OffsetMask - 811 TLB optimizations */ 812 /* Addr Shift Amount for 1KB or larger pages */ 813 if ((NewEntry.Mask & 0xFFFF) == 3){ 814 NewEntry.AddrShiftAmount = 12; 815 } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) { 816 NewEntry.AddrShiftAmount = 10; 817 } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) { 818 NewEntry.AddrShiftAmount = 14; 819 } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) { 820 NewEntry.AddrShiftAmount = 16; 821 } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) { 822 NewEntry.AddrShiftAmount = 18; 823 } else if ((NewEntry.Mask & 0xFF00) == 0x0300) { 824 NewEntry.AddrShiftAmount = 20; 825 } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) { 826 NewEntry.AddrShiftAmount = 22; 827 } else if ((NewEntry.Mask & 0xF000) == 0x3000) { 828 NewEntry.AddrShiftAmount = 24; 829 } else if ((NewEntry.Mask & 0xC000) == 0xC000) { 830 NewEntry.AddrShiftAmount = 26; 831 } else if ((NewEntry.Mask & 0x30000) == 0x30000) { 832 NewEntry.AddrShiftAmount = 28; 833 } else { 834 fatal("Invalid Mask Pattern Detected!\n"); 835 } 836 NewEntry.OffsetMask = ((1 << NewEntry.AddrShiftAmount) - 1); | 842 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 843 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 844 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 845 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 846 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 847 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 848 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 849 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 850 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 851 /* Now, compute the AddrShiftAmount and OffsetMask - 852 TLB optimizations */ 853 /* Addr Shift Amount for 1KB or larger pages */ 854 if ((newEntry.Mask & 0xFFFF) == 3){ 855 newEntry.AddrShiftAmount = 12; 856 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 857 newEntry.AddrShiftAmount = 10; 858 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 859 newEntry.AddrShiftAmount = 14; 860 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 861 newEntry.AddrShiftAmount = 16; 862 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 863 newEntry.AddrShiftAmount = 18; 864 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 865 newEntry.AddrShiftAmount = 20; 866 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 867 newEntry.AddrShiftAmount = 22; 868 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 869 newEntry.AddrShiftAmount = 24; 870 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 871 newEntry.AddrShiftAmount = 26; 872 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 873 newEntry.AddrShiftAmount = 28; 874 } else { 875 fatal("Invalid Mask Pattern Detected!\n"); 876 } 877 newEntry.OffsetMask = 878 (1 << newEntry.AddrShiftAmount) - 1; |
837 | 879 |
838 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 839 Config3Reg config3 = Config3; 840 PageGrainReg pageGrain = PageGrain; 841 int SP = 0; 842 if (bits(config3, config3.sp) == 1 && 843 bits(pageGrain, pageGrain.esp) == 1) { 844 SP = 1; 845 } 846 IndexReg index = Index; 847 Ptr->insertAt(NewEntry, Random, SP); 848 }}); | 880 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 881 Config3Reg config3 = Config3; 882 PageGrainReg pageGrain = PageGrain; 883 int SP = 0; 884 if (bits(config3, config3.sp) == 1 && 885 bits(pageGrain, pageGrain.esp) == 1) { 886 SP = 1; 887 } 888 IndexReg index = Index; 889 Ptr->insertAt(newEntry, Random, SP); 890 }}); |
849 | 891 |
850 0x08: tlbp({{ 851 Config3Reg config3 = Config3; 852 PageGrainReg pageGrain = PageGrain; 853 EntryHiReg entryHi = EntryHi; 854 int TLB_Index; 855 Addr VPN; 856 if (pageGrain.esp == 1 && config3.sp ==1) { 857 VPN = EntryHi >> 11; 858 } else { 859 // Mask off lower 2 bits 860 VPN = ((EntryHi >> 11) & 0xFFFFFFFC); 861 } 862 TLB_Index = xc->tcBase()->getITBPtr()-> 863 probeEntry(VPN, entryHi.asid); 864 // Check TLB for entry matching EntryHi 865 if (TLB_Index != -1) { 866 Index = TLB_Index; 867 } else { 868 // else, set Index = 1 << 31 869 Index = (1 << 31); 870 } 871 }}); 872 } 873 format CP0Unimpl { 874 0x20: wait(); 875 } 876 default: CP0Unimpl::unknown(); 877 | 892 0x08: tlbp({{ 893 Config3Reg config3 = Config3; 894 PageGrainReg pageGrain = PageGrain; 895 EntryHiReg entryHi = EntryHi; 896 int tlbIndex; 897 Addr vpn; 898 if (pageGrain.esp == 1 && config3.sp ==1) { 899 vpn = EntryHi >> 11; 900 } else { 901 // Mask off lower 2 bits 902 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 903 } 904 tlbIndex = xc->tcBase()->getITBPtr()-> 905 probeEntry(VPN, entryHi.asid); 906 // Check TLB for entry matching EntryHi 907 if (tlbIndex != -1) { 908 Index = tlbIndex; 909 } else { 910 // else, set Index = 1 << 31 911 Index = (1 << 31); 912 } 913 }}); 914 } 915 format CP0Unimpl { 916 0x20: wait(); 917 } 918 default: CP0Unimpl::unknown(); |
878 } 879 } 880 881 //Table A-13 MIPS32 COP1 Encoding of rs Field 882 0x1: decode RS_MSB { | 919 } 920 } 921 922 //Table A-13 MIPS32 COP1 Encoding of rs Field 923 0x1: decode RS_MSB { |
883 | |
884 0x0: decode RS_HI { 885 0x0: decode RS_LO { 886 format CP1Control { 887 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 888 889 0x2: cfc1({{ | 924 0x0: decode RS_HI { 925 0x0: decode RS_LO { 926 format CP1Control { 927 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 928 929 0x2: cfc1({{ |
890 switch (FS) 891 { | 930 switch (FS) { |
892 case 0: 893 Rt = FIR; 894 break; 895 case 25: | 931 case 0: 932 Rt = FIR; 933 break; 934 case 25: |
896 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; | 935 Rt = (FCSR & 0xFE000000) >> 24 | 936 (FCSR & 0x00800000) >> 23; |
897 break; 898 case 26: | 937 break; 938 case 26: |
899 Rt = 0 | (FCSR & 0x0003F07C); | 939 Rt = (FCSR & 0x0003F07C); |
900 break; 901 case 28: | 940 break; 941 case 28: |
902 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); | 942 Rt = (FCSR & 0x00000F80) | 943 (FCSR & 0x01000000) >> 21 | 944 (FCSR & 0x00000003); |
903 break; 904 case 31: 905 Rt = FCSR; 906 break; 907 default: 908 warn("FP Control Value (%d) Not Valid"); 909 } | 945 break; 946 case 31: 947 Rt = FCSR; 948 break; 949 default: 950 warn("FP Control Value (%d) Not Valid"); 951 } |
910 // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt); | |
911 }}); 912 | 952 }}); 953 |
913 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); | 954 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>; }}); |
914 | 955 |
915 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); | 956 0x4: mtc1({{ Fs.uw = Rt.uw; }}); |
916 917 0x6: ctc1({{ | 957 958 0x6: ctc1({{ |
918 switch (FS) 919 { | 959 switch (FS) { |
920 case 25: | 960 case 25: |
921 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 922 | (FCSR & 0x01000000) // bit 24 923 | (FCSR & 0x004FFFFF);// bit 22...0 | 961 FCSR = (Rt.uw<7:1> << 25) | // move 31-25 962 (FCSR & 0x01000000) | // bit 24 963 (FCSR & 0x004FFFFF); // bit 22-0 |
924 break; | 964 break; |
925 | |
926 case 26: | 965 case 26: |
927 FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 928 | Rt.uw<17:12> << 12 // bit 17...12 929 | (FCSR & 0x00000F80) << 7// bit 11...7 930 | Rt.uw<6:2> << 2 // bit 6...2 931 | (FCSR & 0x00000002); // bit 1...0 | 966 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 967 Rt.uw<17:12> << 12 | // bit 17-12 968 (FCSR & 0x00000F80) << 7 | // bit 11-7 969 Rt.uw<6:2> << 2 | // bit 6-2 970 (FCSR & 0x00000002); // bit 1-0 |
932 break; | 971 break; |
933 | |
934 case 28: | 972 case 28: |
935 FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 936 | Rt.uw<2:2> << 24 // bit 24 937 | (FCSR & 0x00FFF000) << 23// bit 23...12 938 | Rt.uw<11:7> << 7 // bit 24 939 | (FCSR & 0x000007E) 940 | Rt.uw<1:0>;// bit 22...0 | 973 FCSR = (FCSR & 0xFE000000) | // move 31-25 974 Rt.uw<2:2> << 24 | // bit 24 975 (FCSR & 0x00FFF000) << 23 | // bit 23-12 976 Rt.uw<11:7> << 7 | // bit 24 977 (FCSR & 0x000007E) | 978 Rt.uw<1:0>; // bit 22-0 |
941 break; | 979 break; |
942 | |
943 case 31: | 980 case 31: |
944 FCSR = Rt.uw; | 981 FCSR = Rt.uw; |
945 break; 946 947 default: | 982 break; 983 984 default: |
948 panic("FP Control Value (%d) Not Available. Ignoring Access to" 949 "Floating Control Status Register", FS); | 985 panic("FP Control Value (%d) " 986 "Not Available. Ignoring Access " 987 "to Floating Control Status " 988 "Register", FS); |
950 } 951 }}); 952 953 0x7: mthc1({{ 954 uint64_t fs_hi = Rt.uw; 955 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 956 Fs.ud = (fs_hi << 32) | fs_lo; 957 }}); 958 959 } 960 format CP1Unimpl { 961 0x1: dmfc1(); 962 0x5: dmtc1(); 963 } | 989 } 990 }}); 991 992 0x7: mthc1({{ 993 uint64_t fs_hi = Rt.uw; 994 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 995 Fs.ud = (fs_hi << 32) | fs_lo; 996 }}); 997 998 } 999 format CP1Unimpl { 1000 0x1: dmfc1(); 1001 0x5: dmtc1(); 1002 } |
964 } | 1003 } |
965 | 1004 |
966 0x1: 967 decode RS_LO { 968 0x0: 969 decode ND { 970 format Branch { 971 0x0: decode TF { 972 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 973 }}); 974 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 975 }}); 976 } 977 0x1: decode TF { 978 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 979 }}, Likely); 980 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 981 }}, Likely); 982 } 983 } 984 } 985 format CP1Unimpl { 986 0x1: bc1any2(); 987 0x2: bc1any4(); 988 default: unknown(); 989 } 990 } | 1005 0x1: decode RS_LO { 1006 0x0: decode ND { 1007 format Branch { 1008 0x0: decode TF { 1009 0x0: bc1f({{ 1010 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1011 }}); 1012 0x1: bc1t({{ 1013 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1014 }}); 1015 } 1016 0x1: decode TF { 1017 0x0: bc1fl({{ 1018 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1019 }}, Likely); 1020 0x1: bc1tl({{ 1021 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1022 }}, Likely); 1023 } 1024 } 1025 } 1026 format CP1Unimpl { 1027 0x1: bc1any2(); 1028 0x2: bc1any4(); 1029 default: unknown(); 1030 } 1031 } |
991 } 992 993 0x1: decode RS_HI { 994 0x2: decode RS_LO { | 1032 } 1033 1034 0x1: decode RS_HI { 1035 0x2: decode RS_LO { |
995 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 996 //(( single-precision floating point)) | 1036 //Table A-14 MIPS32 COP1 Encoding of Function Field When 1037 //rs=S (( single-precision floating point)) |
997 0x0: decode FUNCTION_HI { 998 0x0: decode FUNCTION_LO { 999 format FloatOp { | 1038 0x0: decode FUNCTION_HI { 1039 0x0: decode FUNCTION_LO { 1040 format FloatOp { |
1000 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 1001 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 1002 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 1003 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 1004 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 1005 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 1006 0x7: neg_s({{ Fd.sf = -Fs.sf;}}); | 1041 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf; }}); 1042 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf; }}); 1043 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf; }}); 1044 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf; }}); 1045 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf); }}); 1046 0x5: abs_s({{ Fd.sf = fabs(Fs.sf); }}); 1047 0x7: neg_s({{ Fd.sf = -Fs.sf; }}); |
1007 } | 1048 } |
1008 1009 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}}); | 1049 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf; }}); |
1010 } | 1050 } |
1011 | |
1012 0x1: decode FUNCTION_LO { 1013 format FloatConvertOp { | 1051 0x1: decode FUNCTION_LO { 1052 format FloatConvertOp { |
1014 0x0: round_l_s({{ val = Fs.sf; }}, ToLong, 1015 Round); 1016 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong, 1017 Trunc); 1018 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong, 1019 Ceil); 1020 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong, 1021 Floor); 1022 0x4: round_w_s({{ val = Fs.sf; }}, ToWord, 1023 Round); 1024 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord, 1025 Trunc); 1026 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord, 1027 Ceil); 1028 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord, 1029 Floor); | 1053 0x0: round_l_s({{ val = Fs.sf; }}, 1054 ToLong, Round); 1055 0x1: trunc_l_s({{ val = Fs.sf; }}, 1056 ToLong, Trunc); 1057 0x2: ceil_l_s({{ val = Fs.sf;}}, 1058 ToLong, Ceil); 1059 0x3: floor_l_s({{ val = Fs.sf; }}, 1060 ToLong, Floor); 1061 0x4: round_w_s({{ val = Fs.sf; }}, 1062 ToWord, Round); 1063 0x5: trunc_w_s({{ val = Fs.sf; }}, 1064 ToWord, Trunc); 1065 0x6: ceil_w_s({{ val = Fs.sf; }}, 1066 ToWord, Ceil); 1067 0x7: floor_w_s({{ val = Fs.sf; }}, 1068 ToWord, Floor); |
1030 } 1031 } 1032 1033 0x2: decode FUNCTION_LO { 1034 0x1: decode MOVCF { 1035 format BasicOp { | 1069 } 1070 } 1071 1072 0x2: decode FUNCTION_LO { 1073 0x1: decode MOVCF { 1074 format BasicOp { |
1036 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }}); 1037 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }}); | 1075 0x0: movf_s({{ 1076 Fd = (getCondCode(FCSR,CC) == 0) ? 1077 Fs : Fd; 1078 }}); 1079 0x1: movt_s({{ 1080 Fd = (getCondCode(FCSR,CC) == 1) ? 1081 Fs : Fd; 1082 }}); |
1038 } 1039 } 1040 1041 format BasicOp { 1042 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1043 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1044 } 1045 1046 format FloatOp { 1047 0x5: recip_s({{ Fd = 1 / Fs; }}); | 1083 } 1084 } 1085 1086 format BasicOp { 1087 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1088 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1089 } 1090 1091 format FloatOp { 1092 0x5: recip_s({{ Fd = 1 / Fs; }}); |
1048 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); | 1093 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); |
1049 } 1050 format CP1Unimpl { | 1094 } 1095 format CP1Unimpl { |
1051 default: unknown(); | 1096 default: unknown(); |
1052 } 1053 } 1054 0x3: CP1Unimpl::unknown(); 1055 1056 0x4: decode FUNCTION_LO { 1057 format FloatConvertOp { 1058 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 1059 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 1060 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 1061 } 1062 1063 0x6: FloatOp::cvt_ps_s({{ | 1097 } 1098 } 1099 0x3: CP1Unimpl::unknown(); 1100 1101 0x4: decode FUNCTION_LO { 1102 format FloatConvertOp { 1103 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 1104 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 1105 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 1106 } 1107 1108 0x6: FloatOp::cvt_ps_s({{ |
1064 Fd.ud = (uint64_t) Fs.uw << 32 | 1065 (uint64_t) Ft.uw; 1066 }}); | 1109 Fd.ud = (uint64_t) Fs.uw << 32 | 1110 (uint64_t) Ft.uw; 1111 }}); |
1067 format CP1Unimpl { | 1112 format CP1Unimpl { |
1068 default: unknown(); | 1113 default: unknown(); |
1069 } 1070 } 1071 0x5: CP1Unimpl::unknown(); 1072 1073 0x6: decode FUNCTION_LO { 1074 format FloatCompareOp { | 1114 } 1115 } 1116 0x5: CP1Unimpl::unknown(); 1117 1118 0x6: decode FUNCTION_LO { 1119 format FloatCompareOp { |
1075 0x0: c_f_s({{ cond = 0; }}, SinglePrecision, 1076 UnorderedFalse); 1077 0x1: c_un_s({{ cond = 0; }}, SinglePrecision, 1078 UnorderedTrue); | 1120 0x0: c_f_s({{ cond = 0; }}, 1121 SinglePrecision, UnorderedFalse); 1122 0x1: c_un_s({{ cond = 0; }}, 1123 SinglePrecision, UnorderedTrue); |
1079 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 1080 UnorderedFalse); 1081 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 1082 UnorderedTrue); 1083 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 1084 UnorderedFalse); 1085 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 1086 UnorderedTrue); --- 5 unchanged lines hidden (view full) --- 1092 } 1093 1094 0x7: decode FUNCTION_LO { 1095 format FloatCompareOp { 1096 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1097 UnorderedFalse, QnanException); 1098 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1099 UnorderedTrue, QnanException); | 1124 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 1125 UnorderedFalse); 1126 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 1127 UnorderedTrue); 1128 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 1129 UnorderedFalse); 1130 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 1131 UnorderedTrue); --- 5 unchanged lines hidden (view full) --- 1137 } 1138 1139 0x7: decode FUNCTION_LO { 1140 format FloatCompareOp { 1141 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1142 UnorderedFalse, QnanException); 1143 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1144 UnorderedTrue, QnanException); |
1100 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}}, | 1145 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf); }}, |
1101 UnorderedFalse, QnanException); 1102 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 1103 UnorderedTrue, QnanException); 1104 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 1105 UnorderedFalse, QnanException); 1106 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 1107 UnorderedTrue, QnanException); 1108 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 1109 UnorderedFalse, QnanException); 1110 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 1111 UnorderedTrue, QnanException); 1112 } 1113 } 1114 } 1115 | 1146 UnorderedFalse, QnanException); 1147 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 1148 UnorderedTrue, QnanException); 1149 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 1150 UnorderedFalse, QnanException); 1151 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 1152 UnorderedTrue, QnanException); 1153 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 1154 UnorderedFalse, QnanException); 1155 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 1156 UnorderedTrue, QnanException); 1157 } 1158 } 1159 } 1160 |
1116 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D | 1161 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1162 //rs=D |
1117 0x1: decode FUNCTION_HI { 1118 0x0: decode FUNCTION_LO { 1119 format FloatOp { 1120 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 1121 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 1122 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 1123 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); | 1163 0x1: decode FUNCTION_HI { 1164 0x0: decode FUNCTION_LO { 1165 format FloatOp { 1166 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 1167 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 1168 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 1169 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); |
1124 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 1125 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 1126 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); | 1170 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 1171 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 1172 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); |
1127 } | 1173 } |
1128 1129 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); | 1174 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); |
1130 } 1131 1132 0x1: decode FUNCTION_LO { 1133 format FloatConvertOp { | 1175 } 1176 1177 0x1: decode FUNCTION_LO { 1178 format FloatConvertOp { |
1134 0x0: round_l_d({{ val = Fs.df; }}, ToLong, 1135 Round); 1136 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong, 1137 Trunc); 1138 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong, 1139 Ceil); 1140 0x3: floor_l_d({{ val = Fs.df; }}, ToLong, 1141 Floor); 1142 0x4: round_w_d({{ val = Fs.df; }}, ToWord, 1143 Round); 1144 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord, 1145 Trunc); 1146 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord, 1147 Ceil); 1148 0x7: floor_w_d({{ val = Fs.df; }}, ToWord, 1149 Floor); | 1179 0x0: round_l_d({{ val = Fs.df; }}, 1180 ToLong, Round); 1181 0x1: trunc_l_d({{ val = Fs.df; }}, 1182 ToLong, Trunc); 1183 0x2: ceil_l_d({{ val = Fs.df; }}, 1184 ToLong, Ceil); 1185 0x3: floor_l_d({{ val = Fs.df; }}, 1186 ToLong, Floor); 1187 0x4: round_w_d({{ val = Fs.df; }}, 1188 ToWord, Round); 1189 0x5: trunc_w_d({{ val = Fs.df; }}, 1190 ToWord, Trunc); 1191 0x6: ceil_w_d({{ val = Fs.df; }}, 1192 ToWord, Ceil); 1193 0x7: floor_w_d({{ val = Fs.df; }}, 1194 ToWord, Floor); |
1150 } 1151 } 1152 1153 0x2: decode FUNCTION_LO { 1154 0x1: decode MOVCF { 1155 format BasicOp { | 1195 } 1196 } 1197 1198 0x2: decode FUNCTION_LO { 1199 0x1: decode MOVCF { 1200 format BasicOp { |
1156 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ? | 1201 0x0: movf_d({{ 1202 Fd.df = (getCondCode(FCSR,CC) == 0) ? |
1157 Fs.df : Fd.df; | 1203 Fs.df : Fd.df; |
1158 }}); 1159 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ? | 1204 }}); 1205 0x1: movt_d({{ 1206 Fd.df = (getCondCode(FCSR,CC) == 1) ? |
1160 Fs.df : Fd.df; | 1207 Fs.df : Fd.df; |
1161 }}); | 1208 }}); |
1162 } 1163 } 1164 1165 format BasicOp { | 1209 } 1210 } 1211 1212 format BasicOp { |
1166 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }}); 1167 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }}); | 1213 0x2: movz_d({{ 1214 Fd.df = (Rt == 0) ? Fs.df : Fd.df; 1215 }}); 1216 0x3: movn_d({{ 1217 Fd.df = (Rt != 0) ? Fs.df : Fd.df; 1218 }}); |
1168 } 1169 1170 format FloatOp { | 1219 } 1220 1221 format FloatOp { |
1171 0x5: recip_d({{ Fd.df = 1 / Fs.df }}); 1172 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); | 1222 0x5: recip_d({{ Fd.df = 1 / Fs.df; }}); 1223 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df); }}); |
1173 } 1174 format CP1Unimpl { | 1224 } 1225 format CP1Unimpl { |
1175 default: unknown(); | 1226 default: unknown(); |
1176 } 1177 1178 } 1179 0x4: decode FUNCTION_LO { 1180 format FloatConvertOp { 1181 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 1182 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 1183 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 1184 } | 1227 } 1228 1229 } 1230 0x4: decode FUNCTION_LO { 1231 format FloatConvertOp { 1232 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 1233 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 1234 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 1235 } |
1185 default: CP1Unimpl::unknown(); | 1236 default: CP1Unimpl::unknown(); |
1186 } 1187 1188 0x6: decode FUNCTION_LO { 1189 format FloatCompareOp { | 1237 } 1238 1239 0x6: decode FUNCTION_LO { 1240 format FloatCompareOp { |
1190 0x0: c_f_d({{ cond = 0; }}, DoublePrecision, 1191 UnorderedFalse); 1192 0x1: c_un_d({{ cond = 0; }}, DoublePrecision, 1193 UnorderedTrue); | 1241 0x0: c_f_d({{ cond = 0; }}, 1242 DoublePrecision, UnorderedFalse); 1243 0x1: c_un_d({{ cond = 0; }}, 1244 DoublePrecision, UnorderedTrue); |
1194 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 1195 UnorderedFalse); 1196 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 1197 UnorderedTrue); 1198 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 1199 UnorderedFalse); 1200 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 1201 UnorderedTrue); --- 19 unchanged lines hidden (view full) --- 1221 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 1222 UnorderedTrue, QnanException); 1223 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 1224 UnorderedFalse, QnanException); 1225 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 1226 UnorderedTrue, QnanException); 1227 } 1228 } | 1245 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 1246 UnorderedFalse); 1247 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 1248 UnorderedTrue); 1249 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 1250 UnorderedFalse); 1251 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 1252 UnorderedTrue); --- 19 unchanged lines hidden (view full) --- 1272 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 1273 UnorderedTrue, QnanException); 1274 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 1275 UnorderedFalse, QnanException); 1276 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 1277 UnorderedTrue, QnanException); 1278 } 1279 } |
1229 default: CP1Unimpl::unknown(); | 1280 default: CP1Unimpl::unknown(); |
1230 } 1231 0x2: CP1Unimpl::unknown(); 1232 0x3: CP1Unimpl::unknown(); 1233 0x7: CP1Unimpl::unknown(); 1234 | 1281 } 1282 0x2: CP1Unimpl::unknown(); 1283 0x3: CP1Unimpl::unknown(); 1284 0x7: CP1Unimpl::unknown(); 1285 |
1235 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W | 1286 //Table A-16 MIPS32 COP1 Encoding of Function 1287 //Field When rs=W |
1236 0x4: decode FUNCTION { 1237 format FloatConvertOp { 1238 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 1239 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 1240 0x26: CP1Unimpl::cvt_ps_w(); 1241 } | 1288 0x4: decode FUNCTION { 1289 format FloatConvertOp { 1290 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 1291 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 1292 0x26: CP1Unimpl::cvt_ps_w(); 1293 } |
1242 default: CP1Unimpl::unknown(); | 1294 default: CP1Unimpl::unknown(); |
1243 } 1244 | 1295 } 1296 |
1245 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 1246 //Note: "1. Format type L is legal only if 64-bit floating point operations 1247 //are enabled." | 1297 //Table A-16 MIPS32 COP1 Encoding of Function Field 1298 //When rs=L1 1299 //Note: "1. Format type L is legal only if 64-bit 1300 //floating point operations are enabled." |
1248 0x5: decode FUNCTION_HI { 1249 format FloatConvertOp { 1250 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 1251 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 1252 0x26: CP1Unimpl::cvt_ps_l(); 1253 } | 1301 0x5: decode FUNCTION_HI { 1302 format FloatConvertOp { 1303 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 1304 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 1305 0x26: CP1Unimpl::cvt_ps_l(); 1306 } |
1254 default: CP1Unimpl::unknown(); | 1307 default: CP1Unimpl::unknown(); |
1255 } 1256 | 1308 } 1309 |
1257 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 1258 //Note: "1. Format type PS is legal only if 64-bit floating point operations 1259 //are enabled. " | 1310 //Table A-17 MIPS64 COP1 Encoding of Function Field 1311 //When rs=PS1 1312 //Note: "1. Format type PS is legal only if 64-bit 1313 //floating point operations are enabled. " |
1260 0x6: decode FUNCTION_HI { 1261 0x0: decode FUNCTION_LO { 1262 format Float64Op { 1263 0x0: add_ps({{ 1264 Fd1.sf = Fs1.sf + Ft2.sf; 1265 Fd2.sf = Fs2.sf + Ft2.sf; 1266 }}); 1267 0x1: sub_ps({{ --- 11 unchanged lines hidden (view full) --- 1279 0x6: mov_ps({{ 1280 Fd1.sf = Fs1.sf; 1281 Fd2.sf = Fs2.sf; 1282 }}); 1283 0x7: neg_ps({{ 1284 Fd1.sf = -(Fs1.sf); 1285 Fd2.sf = -(Fs2.sf); 1286 }}); | 1314 0x6: decode FUNCTION_HI { 1315 0x0: decode FUNCTION_LO { 1316 format Float64Op { 1317 0x0: add_ps({{ 1318 Fd1.sf = Fs1.sf + Ft2.sf; 1319 Fd2.sf = Fs2.sf + Ft2.sf; 1320 }}); 1321 0x1: sub_ps({{ --- 11 unchanged lines hidden (view full) --- 1333 0x6: mov_ps({{ 1334 Fd1.sf = Fs1.sf; 1335 Fd2.sf = Fs2.sf; 1336 }}); 1337 0x7: neg_ps({{ 1338 Fd1.sf = -(Fs1.sf); 1339 Fd2.sf = -(Fs2.sf); 1340 }}); |
1287 default: CP1Unimpl::unknown(); | 1341 default: CP1Unimpl::unknown(); |
1288 } 1289 } 1290 0x1: CP1Unimpl::unknown(); 1291 0x2: decode FUNCTION_LO { 1292 0x1: decode MOVCF { 1293 format Float64Op { 1294 0x0: movf_ps({{ 1295 Fd1 = (getCondCode(FCSR, CC) == 0) ? --- 19 unchanged lines hidden (view full) --- 1315 }}); 1316 0x3: movn_ps({{ 1317 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1318 Fs1 : Fd1; 1319 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1320 Fs2 : Fd2; 1321 }}); 1322 } | 1342 } 1343 } 1344 0x1: CP1Unimpl::unknown(); 1345 0x2: decode FUNCTION_LO { 1346 0x1: decode MOVCF { 1347 format Float64Op { 1348 0x0: movf_ps({{ 1349 Fd1 = (getCondCode(FCSR, CC) == 0) ? --- 19 unchanged lines hidden (view full) --- 1369 }}); 1370 0x3: movn_ps({{ 1371 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1372 Fs1 : Fd1; 1373 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1374 Fs2 : Fd2; 1375 }}); 1376 } |
1323 default: CP1Unimpl::unknown(); 1324 | 1377 default: CP1Unimpl::unknown(); |
1325 } 1326 0x3: CP1Unimpl::unknown(); 1327 0x4: decode FUNCTION_LO { 1328 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 1329 default: CP1Unimpl::unknown(); 1330 } 1331 1332 0x5: decode FUNCTION_LO { 1333 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); | 1378 } 1379 0x3: CP1Unimpl::unknown(); 1380 0x4: decode FUNCTION_LO { 1381 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 1382 default: CP1Unimpl::unknown(); 1383 } 1384 1385 0x5: decode FUNCTION_LO { 1386 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); |
1334 | |
1335 format Float64Op { | 1387 format Float64Op { |
1336 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 1337 Ft1.uw; 1338 }}); 1339 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 1340 Ft2.uw; 1341 }}); 1342 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 1343 Ft1.uw; 1344 }}); 1345 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 1346 Ft2.uw; 1347 }}); | 1388 0x4: pll({{ 1389 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft1.uw; 1390 }}); 1391 0x5: plu({{ 1392 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft2.uw; 1393 }}); 1394 0x6: pul({{ 1395 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft1.uw; 1396 }}); 1397 0x7: puu({{ 1398 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft2.uw; 1399 }}); |
1348 } 1349 default: CP1Unimpl::unknown(); 1350 } 1351 1352 0x6: decode FUNCTION_LO { 1353 format FloatPSCompareOp { 1354 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1355 UnorderedFalse); --- 44 unchanged lines hidden (view full) --- 1400 UnorderedFalse, QnanException); 1401 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1402 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1403 UnorderedTrue, QnanException); 1404 } 1405 } 1406 } 1407 } | 1400 } 1401 default: CP1Unimpl::unknown(); 1402 } 1403 1404 0x6: decode FUNCTION_LO { 1405 format FloatPSCompareOp { 1406 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1407 UnorderedFalse); --- 44 unchanged lines hidden (view full) --- 1452 UnorderedFalse, QnanException); 1453 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1454 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1455 UnorderedTrue, QnanException); 1456 } 1457 } 1458 } 1459 } |
1408 default: CP1Unimpl::unknown(); | 1460 default: CP1Unimpl::unknown(); |
1409 } 1410 } 1411 1412 //Table A-19 MIPS32 COP2 Encoding of rs Field 1413 0x2: decode RS_MSB { 1414 format CP2Unimpl { 1415 0x0: decode RS_HI { 1416 0x0: decode RS_LO { 1417 0x0: mfc2(); 1418 0x2: cfc2(); 1419 0x3: mfhc2(); 1420 0x4: mtc2(); 1421 0x6: ctc2(); 1422 0x7: mftc2(); | 1461 } 1462 } 1463 1464 //Table A-19 MIPS32 COP2 Encoding of rs Field 1465 0x2: decode RS_MSB { 1466 format CP2Unimpl { 1467 0x0: decode RS_HI { 1468 0x0: decode RS_LO { 1469 0x0: mfc2(); 1470 0x2: cfc2(); 1471 0x3: mfhc2(); 1472 0x4: mtc2(); 1473 0x6: ctc2(); 1474 0x7: mftc2(); |
1423 default: unknown(); | 1475 default: unknown(); |
1424 } 1425 1426 0x1: decode ND { 1427 0x0: decode TF { 1428 0x0: bc2f(); 1429 0x1: bc2t(); | 1476 } 1477 1478 0x1: decode ND { 1479 0x0: decode TF { 1480 0x0: bc2f(); 1481 0x1: bc2t(); |
1430 default: unknown(); | 1482 default: unknown(); |
1431 } 1432 1433 0x1: decode TF { 1434 0x0: bc2fl(); 1435 0x1: bc2tl(); | 1483 } 1484 1485 0x1: decode TF { 1486 0x0: bc2fl(); 1487 0x1: bc2tl(); |
1436 default: unknown(); | 1488 default: unknown(); |
1437 } | 1489 } |
1438 default: unknown(); | 1490 default: unknown(); |
1439 | 1491 |
1440 } 1441 default: unknown(); 1442 1443 } 1444 default: unknown(); | 1492 } 1493 default: unknown(); 1494 } 1495 default: unknown(); |
1445 } 1446 } 1447 1448 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1449 //Note: "COP1X instructions are legal only if 64-bit floating point 1450 //operations are enabled." 1451 0x3: decode FUNCTION_HI { 1452 0x0: decode FUNCTION_LO { 1453 format LoadIndexedMemory { | 1496 } 1497 } 1498 1499 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1500 //Note: "COP1X instructions are legal only if 64-bit floating point 1501 //operations are enabled." 1502 0x3: decode FUNCTION_HI { 1503 0x0: decode FUNCTION_LO { 1504 format LoadIndexedMemory { |
1454 0x0: lwxc1({{ Fd.uw = Mem.uw;}}); 1455 0x1: ldxc1({{ Fd.ud = Mem.ud;}}); 1456 0x5: luxc1({{ Fd.ud = Mem.ud;}}, | 1505 0x0: lwxc1({{ Fd.uw = Mem.uw; }}); 1506 0x1: ldxc1({{ Fd.ud = Mem.ud; }}); 1507 0x5: luxc1({{ Fd.ud = Mem.ud; }}, |
1457 {{ EA = (Rs + Rt) & ~7; }}); 1458 } 1459 } 1460 1461 0x1: decode FUNCTION_LO { 1462 format StoreIndexedMemory { | 1508 {{ EA = (Rs + Rt) & ~7; }}); 1509 } 1510 } 1511 1512 0x1: decode FUNCTION_LO { 1513 format StoreIndexedMemory { |
1463 0x0: swxc1({{ Mem.uw = Fs.uw;}}); 1464 0x1: sdxc1({{ Mem.ud = Fs.ud;}}); 1465 0x5: suxc1({{ Mem.ud = Fs.ud;}}, | 1514 0x0: swxc1({{ Mem.uw = Fs.uw; }}); 1515 0x1: sdxc1({{ Mem.ud = Fs.ud; }}); 1516 0x5: suxc1({{ Mem.ud = Fs.ud; }}, |
1466 {{ EA = (Rs + Rt) & ~7; }}); 1467 } | 1517 {{ EA = (Rs + Rt) & ~7; }}); 1518 } |
1468 | |
1469 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1470 } 1471 1472 0x3: decode FUNCTION_LO { | 1519 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1520 } 1521 1522 0x3: decode FUNCTION_LO { |
1473 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) { 1474 Fd.ud = Fs.ud; 1475 } else if (Rs<2:0> == 4) { 1476 #if BYTE_ORDER == BIG_ENDIAN 1477 Fd.ud = Fs.ud<31:0> << 32 | 1478 Ft.ud<63:32>; 1479 #elif BYTE_ORDER == LITTLE_ENDIAN 1480 Fd.ud = Ft.ud<31:0> << 32 | 1481 Fs.ud<63:32>; 1482 #endif 1483 } else { 1484 Fd.ud = Fd.ud; 1485 } 1486 }}); | 1523 0x6: Float64Op::alnv_ps({{ 1524 if (Rs<2:0> == 0) { 1525 Fd.ud = Fs.ud; 1526 } else if (Rs<2:0> == 4) { 1527#if BYTE_ORDER == BIG_ENDIAN 1528 Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>; 1529#elif BYTE_ORDER == LITTLE_ENDIAN 1530 Fd.ud = Ft.ud<31:0> << 32 | Fs.ud<63:32>; 1531#endif 1532 } else { 1533 Fd.ud = Fd.ud; 1534 } 1535 }}); |
1487 } 1488 1489 format FloatAccOp { 1490 0x4: decode FUNCTION_LO { 1491 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 1492 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 1493 0x6: madd_ps({{ 1494 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; --- 22 unchanged lines hidden (view full) --- 1517 0x7: decode FUNCTION_LO { 1518 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1519 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 1520 0x6: nmsub_ps({{ 1521 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 1522 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 1523 }}); 1524 } | 1536 } 1537 1538 format FloatAccOp { 1539 0x4: decode FUNCTION_LO { 1540 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 1541 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 1542 0x6: madd_ps({{ 1543 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; --- 22 unchanged lines hidden (view full) --- 1566 0x7: decode FUNCTION_LO { 1567 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1568 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 1569 0x6: nmsub_ps({{ 1570 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 1571 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 1572 }}); 1573 } |
1525 | |
1526 } 1527 } 1528 1529 format Branch { 1530 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 1531 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 1532 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 1533 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 1534 } 1535 } 1536 1537 0x3: decode OPCODE_LO { 1538 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1539 0x4: decode FUNCTION_HI { 1540 0x0: decode FUNCTION_LO { | 1574 } 1575 } 1576 1577 format Branch { 1578 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 1579 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 1580 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 1581 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 1582 } 1583 } 1584 1585 0x3: decode OPCODE_LO { 1586 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1587 0x4: decode FUNCTION_HI { 1588 0x0: decode FUNCTION_LO { |
1541 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; 1542 Rd.sw = temp1<31:0>; 1543 }}, IntMultOp); | 1589 0x2: IntOp::mul({{ 1590 int64_t temp1 = Rs.sd * Rt.sd; 1591 Rd.sw = temp1<31:0>; 1592 }}, IntMultOp); |
1544 1545 format HiLoRdSelValOp { | 1593 1594 format HiLoRdSelValOp { |
1546 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp); 1547 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp); 1548 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp); 1549 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp); | 1595 0x0: madd({{ 1596 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1597 (Rs.sd * Rt.sd); 1598 }}, IntMultOp); 1599 0x1: maddu({{ 1600 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1601 (Rs.ud * Rt.ud); 1602 }}, IntMultOp); 1603 0x4: msub({{ 1604 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1605 (Rs.sd * Rt.sd); 1606 }}, IntMultOp); 1607 0x5: msubu({{ 1608 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1609 (Rs.ud * Rt.ud); 1610 }}, IntMultOp); |
1550 } 1551 } 1552 1553 0x4: decode FUNCTION_LO { 1554 format BasicOp { | 1611 } 1612 } 1613 1614 0x4: decode FUNCTION_LO { 1615 format BasicOp { |
1555 0x0: clz({{ int cnt = 32; 1556 for (int idx = 31; idx >= 0; idx--) { 1557 if( Rs<idx:idx> == 1) { 1558 cnt = 31 - idx; 1559 break; 1560 } 1561 } 1562 Rd.uw = cnt; 1563 }}); 1564 0x1: clo({{ int cnt = 32; 1565 for (int idx = 31; idx >= 0; idx--) { 1566 if( Rs<idx:idx> == 0) { 1567 cnt = 31 - idx; 1568 break; 1569 } 1570 } 1571 Rd.uw = cnt; 1572 }}); | 1616 0x0: clz({{ 1617 int cnt = 32; 1618 for (int idx = 31; idx >= 0; idx--) { 1619 if (Rs<idx:idx> == 1) { 1620 cnt = 31 - idx; 1621 break; 1622 } 1623 } 1624 Rd.uw = cnt; 1625 }}); 1626 0x1: clo({{ 1627 int cnt = 32; 1628 for (int idx = 31; idx >= 0; idx--) { 1629 if (Rs<idx:idx> == 0) { 1630 cnt = 31 - idx; 1631 break; 1632 } 1633 } 1634 Rd.uw = cnt; 1635 }}); |
1573 } 1574 } 1575 1576 0x7: decode FUNCTION_LO { 1577 0x7: FailUnimpl::sdbbp(); 1578 } 1579 } 1580 1581 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1582 //of the Architecture 1583 0x7: decode FUNCTION_HI { 1584 0x0: decode FUNCTION_LO { 1585 format BasicOp { 1586 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); | 1636 } 1637 } 1638 1639 0x7: decode FUNCTION_LO { 1640 0x7: FailUnimpl::sdbbp(); 1641 } 1642 } 1643 1644 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1645 //of the Architecture 1646 0x7: decode FUNCTION_HI { 1647 0x0: decode FUNCTION_LO { 1648 format BasicOp { 1649 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); |
1587 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1588 bits(Rs.uw, MSB-LSB, 0) << LSB | 1589 bits(Rt.uw, LSB-1, 0); 1590 }}); | 1650 0x4: ins({{ 1651 Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1652 bits(Rs.uw, MSB-LSB, 0) << LSB | 1653 bits(Rt.uw, LSB-1, 0); 1654 }}); |
1591 } 1592 } 1593 1594 0x1: decode FUNCTION_LO { 1595 format MT_Control { | 1655 } 1656 } 1657 1658 0x1: decode FUNCTION_LO { 1659 format MT_Control { |
1596 0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }}, 1597 UserMode); 1598 0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }}, 1599 UserMode); | 1660 0x0: fork({{ 1661 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1662 }}, UserMode); 1663 0x1: yield({{ 1664 Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, 1665 YQMask); 1666 }}, UserMode); |
1600 } 1601 1602 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1603 0x2: decode OP_HI { 1604 0x0: decode OP_LO { 1605 format LoadIndexedMemory { 1606 0x0: lwx({{ Rd.sw = Mem.sw; }}); 1607 0x4: lhx({{ Rd.sw = Mem.sh; }}); 1608 0x6: lbux({{ Rd.uw = Mem.ub; }}); 1609 } 1610 } 1611 } | 1667 } 1668 1669 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1670 0x2: decode OP_HI { 1671 0x0: decode OP_LO { 1672 format LoadIndexedMemory { 1673 0x0: lwx({{ Rd.sw = Mem.sw; }}); 1674 0x4: lhx({{ Rd.sw = Mem.sh; }}); 1675 0x6: lbux({{ Rd.uw = Mem.ub; }}); 1676 } 1677 } 1678 } |
1612 0x4: DspIntOp::insv({{ int pos = dspctl<5:0>; 1613 int size = dspctl<12:7>-1; 1614 Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }}); | 1679 0x4: DspIntOp::insv({{ 1680 int pos = dspctl<5:0>; 1681 int size = dspctl<12:7> - 1; 1682 Rt.uw = insertBits(Rt.uw, pos+size, 1683 pos, Rs.uw<size:0>); 1684 }}); |
1615 } 1616 1617 0x2: decode FUNCTION_LO { 1618 | 1685 } 1686 1687 0x2: decode FUNCTION_LO { 1688 |
1619 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL) | 1689 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1690 //(DSP ASE MANUAL) |
1620 0x0: decode OP_HI { 1621 0x0: decode OP_LO { 1622 format DspIntOp { | 1691 0x0: decode OP_HI { 1692 0x0: decode OP_LO { 1693 format DspIntOp { |
1623 0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1624 NOSATURATE, UNSIGNED, &dspctl ); }}); 1625 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 1626 NOSATURATE, UNSIGNED, &dspctl ); }}); 1627 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1628 SATURATE, UNSIGNED, &dspctl ); }}); 1629 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 1630 SATURATE, UNSIGNED, &dspctl ); }}); 1631 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 1632 MODE_L, &dspctl ); }}, IntMultOp); 1633 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 1634 MODE_R, &dspctl ); }}, IntMultOp); | 1694 0x0: addu_qb({{ 1695 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1696 NOSATURATE, UNSIGNED, &dspctl); 1697 }}); 1698 0x1: subu_qb({{ 1699 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1700 NOSATURATE, UNSIGNED, &dspctl); 1701 }}); 1702 0x4: addu_s_qb({{ 1703 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1704 SATURATE, UNSIGNED, &dspctl); 1705 }}); 1706 0x5: subu_s_qb({{ 1707 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1708 SATURATE, UNSIGNED, &dspctl); 1709 }}); 1710 0x6: muleu_s_ph_qbl({{ 1711 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1712 MODE_L, &dspctl); 1713 }}, IntMultOp); 1714 0x7: muleu_s_ph_qbr({{ 1715 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1716 MODE_R, &dspctl); 1717 }}, IntMultOp); |
1635 } 1636 } 1637 0x1: decode OP_LO { 1638 format DspIntOp { | 1718 } 1719 } 1720 0x1: decode OP_LO { 1721 format DspIntOp { |
1639 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1640 NOSATURATE, UNSIGNED, &dspctl ); }}); 1641 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1642 NOSATURATE, UNSIGNED, &dspctl ); }}); 1643 0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1644 NOSATURATE, SIGNED, &dspctl ); }}); 1645 0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1646 NOSATURATE, SIGNED, &dspctl ); }}); 1647 0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1648 SATURATE, UNSIGNED, &dspctl ); }}); 1649 0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1650 SATURATE, UNSIGNED, &dspctl ); }}); 1651 0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1652 SATURATE, SIGNED, &dspctl ); }}); 1653 0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1654 SATURATE, SIGNED, &dspctl ); }}); | 1722 0x0: addu_ph({{ 1723 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1724 NOSATURATE, UNSIGNED, &dspctl); 1725 }}); 1726 0x1: subu_ph({{ 1727 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1728 NOSATURATE, UNSIGNED, &dspctl); 1729 }}); 1730 0x2: addq_ph({{ 1731 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1732 NOSATURATE, SIGNED, &dspctl); 1733 }}); 1734 0x3: subq_ph({{ 1735 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1736 NOSATURATE, SIGNED, &dspctl); 1737 }}); 1738 0x4: addu_s_ph({{ 1739 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1740 SATURATE, UNSIGNED, &dspctl); 1741 }}); 1742 0x5: subu_s_ph({{ 1743 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1744 SATURATE, UNSIGNED, &dspctl); 1745 }}); 1746 0x6: addq_s_ph({{ 1747 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1748 SATURATE, SIGNED, &dspctl); 1749 }}); 1750 0x7: subq_s_ph({{ 1751 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1752 SATURATE, SIGNED, &dspctl); 1753 }}); |
1655 } 1656 } 1657 0x2: decode OP_LO { 1658 format DspIntOp { | 1754 } 1755 } 1756 0x2: decode OP_LO { 1757 format DspIntOp { |
1659 0x0: addsc({{ int64_t dresult; 1660 dresult = Rs.ud + Rt.ud; 1661 Rd.sw = dresult<31:0>; 1662 dspctl = insertBits( dspctl, 13, 13, 1663 dresult<32:32> ); }}); 1664 0x1: addwc({{ int64_t dresult; 1665 dresult = Rs.sd + Rt.sd + dspctl<13:13>; 1666 Rd.sw = dresult<31:0>; 1667 if( dresult<32:32> != dresult<31:31> ) 1668 dspctl = insertBits( dspctl, 20, 20, 1 ); }}); 1669 0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }}); 1670 0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 1671 Rs.uw<15:8> + Rs.uw<7:0>; }}); 1672 0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W, 1673 SATURATE, SIGNED, &dspctl ); }}); 1674 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W, 1675 SATURATE, SIGNED, &dspctl ); }}); | 1758 0x0: addsc({{ 1759 int64_t dresult; 1760 dresult = Rs.ud + Rt.ud; 1761 Rd.sw = dresult<31:0>; 1762 dspctl = insertBits(dspctl, 13, 13, 1763 dresult<32:32>); 1764 }}); 1765 0x1: addwc({{ 1766 int64_t dresult; 1767 dresult = Rs.sd + Rt.sd + dspctl<13:13>; 1768 Rd.sw = dresult<31:0>; 1769 if (dresult<32:32> != dresult<31:31>) 1770 dspctl = insertBits(dspctl, 20, 20, 1); 1771 }}); 1772 0x2: modsub({{ 1773 Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : 1774 Rs.sw - Rt.sw<7:0>; 1775 }}); 1776 0x4: raddu_w_qb({{ 1777 Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 1778 Rs.uw<15:8> + Rs.uw<7:0>; 1779 }}); 1780 0x6: addq_s_w({{ 1781 Rd.sw = dspAdd(Rs.sw, Rt.sw, SIMD_FMT_W, 1782 SATURATE, SIGNED, &dspctl); 1783 }}); 1784 0x7: subq_s_w({{ 1785 Rd.sw = dspSub(Rs.sw, Rt.sw, SIMD_FMT_W, 1786 SATURATE, SIGNED, &dspctl); 1787 }}); |
1676 } 1677 } 1678 0x3: decode OP_LO { 1679 format DspIntOp { | 1788 } 1789 } 1790 0x3: decode OP_LO { 1791 format DspIntOp { |
1680 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 1681 MODE_L, &dspctl ); }}, IntMultOp); 1682 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 1683 MODE_R, &dspctl ); }}, IntMultOp); 1684 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 1685 SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 1686 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 1687 SATURATE, ROUND, &dspctl ); }}, IntMultOp); | 1792 0x4: muleq_s_w_phl({{ 1793 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1794 MODE_L, &dspctl); 1795 }}, IntMultOp); 1796 0x5: muleq_s_w_phr({{ 1797 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1798 MODE_R, &dspctl); 1799 }}, IntMultOp); 1800 0x6: mulq_s_ph({{ 1801 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1802 SATURATE, NOROUND, &dspctl); 1803 }}, IntMultOp); 1804 0x7: mulq_rs_ph({{ 1805 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1806 SATURATE, ROUND, &dspctl); 1807 }}, IntMultOp); |
1688 } 1689 } 1690 } 1691 | 1808 } 1809 } 1810 } 1811 |
1692 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL) | 1812 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1813 //(DSP ASE MANUAL) |
1693 0x1: decode OP_HI { 1694 0x0: decode OP_LO { 1695 format DspIntOp { | 1814 0x1: decode OP_HI { 1815 0x0: decode OP_LO { 1816 format DspIntOp { |
1696 0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1697 UNSIGNED, CMP_EQ, &dspctl ); }}); 1698 0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1699 UNSIGNED, CMP_LT, &dspctl ); }}); 1700 0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1701 UNSIGNED, CMP_LE, &dspctl ); }}); 1702 0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 1703 SIMD_FMT_QB, &dspctl ); }}); 1704 0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1705 UNSIGNED, CMP_EQ ); }}); 1706 0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1707 UNSIGNED, CMP_LT ); }}); 1708 0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1709 UNSIGNED, CMP_LE ); }}); | 1817 0x0: cmpu_eq_qb({{ 1818 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1819 UNSIGNED, CMP_EQ, &dspctl); 1820 }}); 1821 0x1: cmpu_lt_qb({{ 1822 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1823 UNSIGNED, CMP_LT, &dspctl); 1824 }}); 1825 0x2: cmpu_le_qb({{ 1826 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1827 UNSIGNED, CMP_LE, &dspctl); 1828 }}); 1829 0x3: pick_qb({{ 1830 Rd.uw = dspPick(Rs.uw, Rt.uw, 1831 SIMD_FMT_QB, &dspctl); 1832 }}); 1833 0x4: cmpgu_eq_qb({{ 1834 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1835 UNSIGNED, CMP_EQ ); 1836 }}); 1837 0x5: cmpgu_lt_qb({{ 1838 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1839 UNSIGNED, CMP_LT); 1840 }}); 1841 0x6: cmpgu_le_qb({{ 1842 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1843 UNSIGNED, CMP_LE); 1844 }}); |
1710 } 1711 } 1712 0x1: decode OP_LO { 1713 format DspIntOp { | 1845 } 1846 } 1847 0x1: decode OP_LO { 1848 format DspIntOp { |
1714 0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1715 SIGNED, CMP_EQ, &dspctl ); }}); 1716 0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1717 SIGNED, CMP_LT, &dspctl ); }}); 1718 0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1719 SIGNED, CMP_LE, &dspctl ); }}); 1720 0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 1721 SIMD_FMT_PH, &dspctl ); }}); 1722 0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 | 1723 Rs.uw<15:8> << 16 | 1724 Rt.uw<31:24> << 8 | 1725 Rt.uw<15:8>; }}); 1726 0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 | 1727 Rs.uw<7:0> << 16 | 1728 Rt.uw<23:16> << 8 | 1729 Rt.uw<7:0>; }}); 1730 0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw, 1731 SIMD_FMT_PH ); }}); 1732 0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }}); | 1849 0x0: cmp_eq_ph({{ 1850 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1851 SIGNED, CMP_EQ, &dspctl); 1852 }}); 1853 0x1: cmp_lt_ph({{ 1854 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1855 SIGNED, CMP_LT, &dspctl); 1856 }}); 1857 0x2: cmp_le_ph({{ 1858 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1859 SIGNED, CMP_LE, &dspctl); 1860 }}); 1861 0x3: pick_ph({{ 1862 Rd.uw = dspPick(Rs.uw, Rt.uw, 1863 SIMD_FMT_PH, &dspctl); 1864 }}); 1865 0x4: precrq_qb_ph({{ 1866 Rd.uw = Rs.uw<31:24> << 24 | 1867 Rs.uw<15:8> << 16 | 1868 Rt.uw<31:24> << 8 | 1869 Rt.uw<15:8>; 1870 }}); 1871 0x5: precr_qb_ph({{ 1872 Rd.uw = Rs.uw<23:16> << 24 | 1873 Rs.uw<7:0> << 16 | 1874 Rt.uw<23:16> << 8 | 1875 Rt.uw<7:0>; 1876 }}); 1877 0x6: packrl_ph({{ 1878 Rd.uw = dspPack(Rs.uw, Rt.uw, SIMD_FMT_PH); 1879 }}); 1880 0x7: precrqu_s_qb_ph({{ 1881 Rd.uw = dspPrecrqu(Rs.uw, Rt.uw, &dspctl); 1882 }}); |
1733 } 1734 } 1735 0x2: decode OP_LO { 1736 format DspIntOp { | 1883 } 1884 } 1885 0x2: decode OP_LO { 1886 format DspIntOp { |
1737 0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }}); 1738 0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }}); | 1887 0x4: precrq_ph_w({{ 1888 Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; 1889 }}); 1890 0x5: precrq_rs_ph_w({{ 1891 Rd.uw = dspPrecrq(Rs.uw, Rt.uw, 1892 SIMD_FMT_W, &dspctl); 1893 }}); |
1739 } 1740 } 1741 0x3: decode OP_LO { 1742 format DspIntOp { | 1894 } 1895 } 1896 0x3: decode OP_LO { 1897 format DspIntOp { |
1743 0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1744 UNSIGNED, CMP_EQ, &dspctl ); }}); 1745 0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1746 UNSIGNED, CMP_LT, &dspctl ); }}); 1747 0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1748 UNSIGNED, CMP_LE, &dspctl ); }}); 1749 0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 1750 SIMD_FMT_W, NOROUND ); }}); 1751 0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 1752 SIMD_FMT_W, ROUND ); }}); | 1898 0x0: cmpgdu_eq_qb({{ 1899 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1900 UNSIGNED, CMP_EQ, &dspctl); 1901 }}); 1902 0x1: cmpgdu_lt_qb({{ 1903 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1904 UNSIGNED, CMP_LT, &dspctl); 1905 }}); 1906 0x2: cmpgdu_le_qb({{ 1907 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1908 UNSIGNED, CMP_LE, &dspctl); 1909 }}); 1910 0x6: precr_sra_ph_w({{ 1911 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1912 SIMD_FMT_W, NOROUND); 1913 }}); 1914 0x7: precr_sra_r_ph_w({{ 1915 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1916 SIMD_FMT_W, ROUND); 1917 }}); |
1753 } 1754 } 1755 } 1756 | 1918 } 1919 } 1920 } 1921 |
1757 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL) | 1922 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1923 //(DSP ASE MANUAL) |
1758 0x2: decode OP_HI { 1759 0x0: decode OP_LO { 1760 format DspIntOp { | 1924 0x2: decode OP_HI { 1925 0x0: decode OP_LO { 1926 format DspIntOp { |
1761 0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}}); 1762 0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 | 1763 RS_RT<7:0> << 16 | 1764 RS_RT<7:0> << 8 | 1765 RS_RT<7:0>; }}); 1766 0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 | 1767 Rt.uw<7:0> << 16 | 1768 Rt.uw<7:0> << 8 | 1769 Rt.uw<7:0>; }}); 1770 0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1771 SIMD_FMT_PH, SIGNED, MODE_L ); }}); 1772 0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1773 SIMD_FMT_PH, SIGNED, MODE_R ); }}); 1774 0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1775 SIMD_FMT_PH, SIGNED, MODE_LA ); }}); 1776 0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1777 SIMD_FMT_PH, SIGNED, MODE_RA ); }}); | 1927 0x1: absq_s_qb({{ 1928 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_QB, &dspctl); 1929 }}); 1930 0x2: repl_qb({{ 1931 Rd.uw = RS_RT<7:0> << 24 | 1932 RS_RT<7:0> << 16 | 1933 RS_RT<7:0> << 8 | 1934 RS_RT<7:0>; 1935 }}); 1936 0x3: replv_qb({{ 1937 Rd.sw = Rt.uw<7:0> << 24 | 1938 Rt.uw<7:0> << 16 | 1939 Rt.uw<7:0> << 8 | 1940 Rt.uw<7:0>; 1941 }}); 1942 0x4: precequ_ph_qbl({{ 1943 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1944 SIMD_FMT_PH, SIGNED, MODE_L); 1945 }}); 1946 0x5: precequ_ph_qbr({{ 1947 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1948 SIMD_FMT_PH, SIGNED, MODE_R); 1949 }}); 1950 0x6: precequ_ph_qbla({{ 1951 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1952 SIMD_FMT_PH, SIGNED, MODE_LA); 1953 }}); 1954 0x7: precequ_ph_qbra({{ 1955 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1956 SIMD_FMT_PH, SIGNED, MODE_RA); 1957 }}); |
1778 } 1779 } 1780 0x1: decode OP_LO { 1781 format DspIntOp { | 1958 } 1959 } 1960 0x1: decode OP_LO { 1961 format DspIntOp { |
1782 0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }}); 1783 0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 1784 (sext<10>(RS_RT))<15:0>; }}); 1785 0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 | 1786 Rt.uw<15:0>; }}); 1787 0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 1788 SIMD_FMT_W, SIGNED, MODE_L ); }}); 1789 0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 1790 SIMD_FMT_W, SIGNED, MODE_R ); }}); | 1962 0x1: absq_s_ph({{ 1963 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_PH, &dspctl); 1964 }}); 1965 0x2: repl_ph({{ 1966 Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 1967 (sext<10>(RS_RT))<15:0>; 1968 }}); 1969 0x3: replv_ph({{ 1970 Rd.uw = Rt.uw<15:0> << 16 | 1971 Rt.uw<15:0>; 1972 }}); 1973 0x4: preceq_w_phl({{ 1974 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1975 SIMD_FMT_W, SIGNED, MODE_L); 1976 }}); 1977 0x5: preceq_w_phr({{ 1978 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1979 SIMD_FMT_W, SIGNED, MODE_R); 1980 }}); |
1791 } 1792 } 1793 0x2: decode OP_LO { 1794 format DspIntOp { | 1981 } 1982 } 1983 0x2: decode OP_LO { 1984 format DspIntOp { |
1795 0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }}); | 1985 0x1: absq_s_w({{ 1986 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_W, &dspctl); 1987 }}); |
1796 } 1797 } 1798 0x3: decode OP_LO { | 1988 } 1989 } 1990 0x3: decode OP_LO { |
1799 0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }}); | 1991 0x3: IntOp::bitrev({{ 1992 Rd.uw = bitrev( Rt.uw<15:0> ); 1993 }}); |
1800 format DspIntOp { | 1994 format DspIntOp { |
1801 0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1802 SIMD_FMT_PH, UNSIGNED, MODE_L ); }}); 1803 0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1804 SIMD_FMT_PH, UNSIGNED, MODE_R ); }}); 1805 0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1806 SIMD_FMT_PH, UNSIGNED, MODE_LA ); }}); 1807 0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1808 SIMD_FMT_PH, UNSIGNED, MODE_RA ); }}); | 1995 0x4: preceu_ph_qbl({{ 1996 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 1997 UNSIGNED, SIMD_FMT_PH, 1998 UNSIGNED, MODE_L); 1999 }}); 2000 0x5: preceu_ph_qbr({{ 2001 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2002 UNSIGNED, SIMD_FMT_PH, 2003 UNSIGNED, MODE_R ); 2004 }}); 2005 0x6: preceu_ph_qbla({{ 2006 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2007 UNSIGNED, SIMD_FMT_PH, 2008 UNSIGNED, MODE_LA ); 2009 }}); 2010 0x7: preceu_ph_qbra({{ 2011 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2012 UNSIGNED, SIMD_FMT_PH, 2013 UNSIGNED, MODE_RA); 2014 }}); |
1809 } 1810 } 1811 } 1812 | 2015 } 2016 } 2017 } 2018 |
1813 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL) | 2019 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 2020 //(DSP ASE MANUAL) |
1814 0x3: decode OP_HI { 1815 0x0: decode OP_LO { 1816 format DspIntOp { | 2021 0x3: decode OP_HI { 2022 0x0: decode OP_LO { 2023 format DspIntOp { |
1817 0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB, 1818 NOSATURATE, UNSIGNED, &dspctl ); }}); 1819 0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB, 1820 UNSIGNED ); }}); 1821 0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB, 1822 NOSATURATE, UNSIGNED, &dspctl ); }}); 1823 0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB, 1824 UNSIGNED ); }}); 1825 0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 1826 NOROUND, SIGNED, &dspctl ); }}); 1827 0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 1828 ROUND, SIGNED, &dspctl ); }}); 1829 0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 1830 NOROUND, SIGNED, &dspctl ); }}); 1831 0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 1832 ROUND, SIGNED, &dspctl ); }}); | 2024 0x0: shll_qb({{ 2025 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_QB, 2026 NOSATURATE, UNSIGNED, &dspctl); 2027 }}); 2028 0x1: shrl_qb({{ 2029 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_QB, 2030 UNSIGNED); 2031 }}); 2032 0x2: shllv_qb({{ 2033 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_QB, 2034 NOSATURATE, UNSIGNED, &dspctl); 2035 }}); 2036 0x3: shrlv_qb({{ 2037 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_QB, 2038 UNSIGNED); 2039 }}); 2040 0x4: shra_qb({{ 2041 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2042 NOROUND, SIGNED, &dspctl); 2043 }}); 2044 0x5: shra_r_qb({{ 2045 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2046 ROUND, SIGNED, &dspctl); 2047 }}); 2048 0x6: shrav_qb({{ 2049 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2050 NOROUND, SIGNED, &dspctl); 2051 }}); 2052 0x7: shrav_r_qb({{ 2053 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2054 ROUND, SIGNED, &dspctl); 2055 }}); |
1833 } 1834 } 1835 0x1: decode OP_LO { 1836 format DspIntOp { | 2056 } 2057 } 2058 0x1: decode OP_LO { 2059 format DspIntOp { |
1837 0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH, 1838 NOSATURATE, SIGNED, &dspctl ); }}); 1839 0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 1840 NOROUND, SIGNED, &dspctl ); }}); 1841 0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 1842 NOSATURATE, SIGNED, &dspctl ); }}); 1843 0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 1844 NOROUND, SIGNED, &dspctl ); }}); 1845 0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH, 1846 SATURATE, SIGNED, &dspctl ); }}); 1847 0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 1848 ROUND, SIGNED, &dspctl ); }}); 1849 0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 1850 SATURATE, SIGNED, &dspctl ); }}); 1851 0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 1852 ROUND, SIGNED, &dspctl ); }}); | 2060 0x0: shll_ph({{ 2061 Rd.uw = dspShll(Rt.uw, RS, SIMD_FMT_PH, 2062 NOSATURATE, SIGNED, &dspctl); 2063 }}); 2064 0x1: shra_ph({{ 2065 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2066 NOROUND, SIGNED, &dspctl); 2067 }}); 2068 0x2: shllv_ph({{ 2069 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2070 NOSATURATE, SIGNED, &dspctl); 2071 }}); 2072 0x3: shrav_ph({{ 2073 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2074 NOROUND, SIGNED, &dspctl); 2075 }}); 2076 0x4: shll_s_ph({{ 2077 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_PH, 2078 SATURATE, SIGNED, &dspctl); 2079 }}); 2080 0x5: shra_r_ph({{ 2081 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2082 ROUND, SIGNED, &dspctl); 2083 }}); 2084 0x6: shllv_s_ph({{ 2085 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2086 SATURATE, SIGNED, &dspctl); 2087 }}); 2088 0x7: shrav_r_ph({{ 2089 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2090 ROUND, SIGNED, &dspctl); 2091 }}); |
1853 } 1854 } 1855 0x2: decode OP_LO { 1856 format DspIntOp { | 2092 } 2093 } 2094 0x2: decode OP_LO { 2095 format DspIntOp { |
1857 0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W, 1858 SATURATE, SIGNED, &dspctl ); }}); 1859 0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W, 1860 ROUND, SIGNED, &dspctl ); }}); 1861 0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W, 1862 SATURATE, SIGNED, &dspctl ); }}); 1863 0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W, 1864 ROUND, SIGNED, &dspctl ); }}); | 2096 0x4: shll_s_w({{ 2097 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_W, 2098 SATURATE, SIGNED, &dspctl); 2099 }}); 2100 0x5: shra_r_w({{ 2101 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_W, 2102 ROUND, SIGNED, &dspctl); 2103 }}); 2104 0x6: shllv_s_w({{ 2105 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_W, 2106 SATURATE, SIGNED, &dspctl); 2107 }}); 2108 0x7: shrav_r_w({{ 2109 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_W, 2110 ROUND, SIGNED, &dspctl); 2111 }}); |
1865 } 1866 } 1867 0x3: decode OP_LO { 1868 format DspIntOp { | 2112 } 2113 } 2114 0x3: decode OP_LO { 2115 format DspIntOp { |
1869 0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH, 1870 UNSIGNED ); }}); 1871 0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH, 1872 UNSIGNED ); }}); | 2116 0x1: shrl_ph({{ 2117 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_PH, 2118 UNSIGNED); 2119 }}); 2120 0x3: shrlv_ph({{ 2121 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_PH, 2122 UNSIGNED); 2123 }}); |
1873 } 1874 } 1875 } 1876 } 1877 1878 0x3: decode FUNCTION_LO { 1879 | 2124 } 2125 } 2126 } 2127 } 2128 2129 0x3: decode FUNCTION_LO { 2130 |
1880 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual) | 2131 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2132 //(DSP ASE Rev2 Manual) |
1881 0x0: decode OP_HI { 1882 0x0: decode OP_LO { 1883 format DspIntOp { | 2133 0x0: decode OP_HI { 2134 0x0: decode OP_LO { 2135 format DspIntOp { |
1884 0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1885 NOROUND, UNSIGNED ); }}); 1886 0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1887 NOROUND, UNSIGNED ); }}); 1888 0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1889 ROUND, UNSIGNED ); }}); 1890 0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1891 ROUND, UNSIGNED ); }}); | 2136 0x0: adduh_qb({{ 2137 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2138 NOROUND, UNSIGNED); 2139 }}); 2140 0x1: subuh_qb({{ 2141 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2142 NOROUND, UNSIGNED); 2143 }}); 2144 0x2: adduh_r_qb({{ 2145 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2146 ROUND, UNSIGNED); 2147 }}); 2148 0x3: subuh_r_qb({{ 2149 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2150 ROUND, UNSIGNED); 2151 }}); |
1892 } 1893 } 1894 0x1: decode OP_LO { 1895 format DspIntOp { | 2152 } 2153 } 2154 0x1: decode OP_LO { 2155 format DspIntOp { |
1896 0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1897 NOROUND, SIGNED ); }}); 1898 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1899 NOROUND, SIGNED ); }}); 1900 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1901 ROUND, SIGNED ); }}); 1902 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1903 ROUND, SIGNED ); }}); 1904 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 1905 NOSATURATE, &dspctl ); }}, IntMultOp); 1906 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 1907 SATURATE, &dspctl ); }}, IntMultOp); 1908 | 2156 0x0: addqh_ph({{ 2157 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2158 NOROUND, SIGNED); 2159 }}); 2160 0x1: subqh_ph({{ 2161 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2162 NOROUND, SIGNED); 2163 }}); 2164 0x2: addqh_r_ph({{ 2165 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2166 ROUND, SIGNED); 2167 }}); 2168 0x3: subqh_r_ph({{ 2169 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2170 ROUND, SIGNED); 2171 }}); 2172 0x4: mul_ph({{ 2173 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2174 NOSATURATE, &dspctl); 2175 }}, IntMultOp); 2176 0x6: mul_s_ph({{ 2177 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2178 SATURATE, &dspctl); 2179 }}, IntMultOp); |
1909 } 1910 } 1911 0x2: decode OP_LO { 1912 format DspIntOp { | 2180 } 2181 } 2182 0x2: decode OP_LO { 2183 format DspIntOp { |
1913 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 1914 NOROUND, SIGNED ); }}); 1915 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 1916 NOROUND, SIGNED ); }}); 1917 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 1918 ROUND, SIGNED ); }}); 1919 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 1920 ROUND, SIGNED ); }}); 1921 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 1922 SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 1923 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 1924 SATURATE, ROUND, &dspctl ); }}, IntMultOp); | 2184 0x0: addqh_w({{ 2185 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2186 NOROUND, SIGNED); 2187 }}); 2188 0x1: subqh_w({{ 2189 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2190 NOROUND, SIGNED); 2191 }}); 2192 0x2: addqh_r_w({{ 2193 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2194 ROUND, SIGNED); 2195 }}); 2196 0x3: subqh_r_w({{ 2197 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2198 ROUND, SIGNED); 2199 }}); 2200 0x6: mulq_s_w({{ 2201 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2202 SATURATE, NOROUND, &dspctl); 2203 }}, IntMultOp); 2204 0x7: mulq_rs_w({{ 2205 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2206 SATURATE, ROUND, &dspctl); 2207 }}, IntMultOp); |
1925 } 1926 } 1927 } 1928 } 1929 1930 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1931 0x4: decode SA { 1932 format BasicOp { | 2208 } 2209 } 2210 } 2211 } 2212 2213 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2214 0x4: decode SA { 2215 format BasicOp { |
1933 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | 1934 Rt.uw<31:24> << 16 | 1935 Rt.uw<7:0> << 8 | 1936 Rt.uw<15:8>; | 2216 0x02: wsbh({{ 2217 Rd.uw = Rt.uw<23:16> << 24 | 2218 Rt.uw<31:24> << 16 | 2219 Rt.uw<7:0> << 8 | 2220 Rt.uw<15:8>; |
1937 }}); 1938 0x10: seb({{ Rd.sw = Rt.sb; }}); 1939 0x18: seh({{ Rd.sw = Rt.sh; }}); 1940 } 1941 } 1942 1943 0x6: decode FUNCTION_LO { 1944 | 2221 }}); 2222 0x10: seb({{ Rd.sw = Rt.sb; }}); 2223 0x18: seh({{ Rd.sw = Rt.sh; }}); 2224 } 2225 } 2226 2227 0x6: decode FUNCTION_LO { 2228 |
1945 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL) | 2229 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2230 //(DSP ASE MANUAL) |
1946 0x0: decode OP_HI { 1947 0x0: decode OP_LO { 1948 format DspHiLoOp { | 2231 0x0: decode OP_HI { 2232 0x0: decode OP_LO { 2233 format DspHiLoOp { |
1949 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1950 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 1951 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1952 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 1953 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw, 1954 ACDST, SIMD_FMT_PH ); }}, IntMultOp); 1955 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1956 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 1957 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1958 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1959 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1960 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1961 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw, 1962 ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp); 1963 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1964 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); | 2234 0x0: dpa_w_ph({{ 2235 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2236 SIMD_FMT_PH, SIGNED, MODE_L); 2237 }}, IntMultOp); 2238 0x1: dps_w_ph({{ 2239 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2240 SIMD_FMT_PH, SIGNED, MODE_L); 2241 }}, IntMultOp); 2242 0x2: mulsa_w_ph({{ 2243 dspac = dspMulsa(dspac, Rs.sw, Rt.sw, 2244 ACDST, SIMD_FMT_PH ); 2245 }}, IntMultOp); 2246 0x3: dpau_h_qbl({{ 2247 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2248 SIMD_FMT_QB, UNSIGNED, MODE_L); 2249 }}, IntMultOp); 2250 0x4: dpaq_s_w_ph({{ 2251 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2252 ACDST, SIMD_FMT_PH, 2253 SIMD_FMT_W, NOSATURATE, 2254 MODE_L, &dspctl); 2255 }}, IntMultOp); 2256 0x5: dpsq_s_w_ph({{ 2257 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2258 ACDST, SIMD_FMT_PH, 2259 SIMD_FMT_W, NOSATURATE, 2260 MODE_L, &dspctl); 2261 }}, IntMultOp); 2262 0x6: mulsaq_s_w_ph({{ 2263 dspac = dspMulsaq(dspac, Rs.sw, Rt.sw, 2264 ACDST, SIMD_FMT_PH, 2265 &dspctl); 2266 }}, IntMultOp); 2267 0x7: dpau_h_qbr({{ 2268 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2269 SIMD_FMT_QB, UNSIGNED, MODE_R); 2270 }}, IntMultOp); |
1965 } 1966 } 1967 0x1: decode OP_LO { 1968 format DspHiLoOp { | 2271 } 2272 } 2273 0x1: decode OP_LO { 2274 format DspHiLoOp { |
1969 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1970 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 1971 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1972 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 1973 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1974 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 1975 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 1976 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1977 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 1978 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1979 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1980 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); | 2275 0x0: dpax_w_ph({{ 2276 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2277 SIMD_FMT_PH, SIGNED, MODE_X); 2278 }}, IntMultOp); 2279 0x1: dpsx_w_ph({{ 2280 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2281 SIMD_FMT_PH, SIGNED, MODE_X); 2282 }}, IntMultOp); 2283 0x3: dpsu_h_qbl({{ 2284 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2285 SIMD_FMT_QB, UNSIGNED, MODE_L); 2286 }}, IntMultOp); 2287 0x4: dpaq_sa_l_w({{ 2288 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2289 ACDST, SIMD_FMT_W, 2290 SIMD_FMT_L, SATURATE, 2291 MODE_L, &dspctl); 2292 }}, IntMultOp); 2293 0x5: dpsq_sa_l_w({{ 2294 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2295 ACDST, SIMD_FMT_W, 2296 SIMD_FMT_L, SATURATE, 2297 MODE_L, &dspctl); 2298 }}, IntMultOp); 2299 0x7: dpsu_h_qbr({{ 2300 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2301 SIMD_FMT_QB, UNSIGNED, MODE_R); 2302 }}, IntMultOp); |
1981 } 1982 } 1983 0x2: decode OP_LO { 1984 format DspHiLoOp { | 2303 } 2304 } 2305 0x2: decode OP_LO { 2306 format DspHiLoOp { |
1985 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1986 MODE_L, SATURATE, &dspctl ); }}, IntMultOp); 1987 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1988 MODE_R, SATURATE, &dspctl ); }}, IntMultOp); 1989 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1990 MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp); 1991 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1992 MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp); | 2307 0x0: maq_sa_w_phl({{ 2308 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2309 ACDST, SIMD_FMT_PH, 2310 MODE_L, SATURATE, &dspctl); 2311 }}, IntMultOp); 2312 0x2: maq_sa_w_phr({{ 2313 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2314 ACDST, SIMD_FMT_PH, 2315 MODE_R, SATURATE, &dspctl); 2316 }}, IntMultOp); 2317 0x4: maq_s_w_phl({{ 2318 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2319 ACDST, SIMD_FMT_PH, 2320 MODE_L, NOSATURATE, &dspctl); 2321 }}, IntMultOp); 2322 0x6: maq_s_w_phr({{ 2323 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2324 ACDST, SIMD_FMT_PH, 2325 MODE_R, NOSATURATE, &dspctl); 2326 }}, IntMultOp); |
1993 } 1994 } 1995 0x3: decode OP_LO { 1996 format DspHiLoOp { | 2327 } 2328 } 2329 0x3: decode OP_LO { 2330 format DspHiLoOp { |
1997 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1998 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1999 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 2000 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 2001 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 2002 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); 2003 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 2004 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); | 2331 0x0: dpaqx_s_w_ph({{ 2332 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2333 ACDST, SIMD_FMT_PH, 2334 SIMD_FMT_W, NOSATURATE, 2335 MODE_X, &dspctl); 2336 }}, IntMultOp); 2337 0x1: dpsqx_s_w_ph({{ 2338 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2339 ACDST, SIMD_FMT_PH, 2340 SIMD_FMT_W, NOSATURATE, 2341 MODE_X, &dspctl); 2342 }}, IntMultOp); 2343 0x2: dpaqx_sa_w_ph({{ 2344 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2345 ACDST, SIMD_FMT_PH, 2346 SIMD_FMT_W, SATURATE, 2347 MODE_X, &dspctl); 2348 }}, IntMultOp); 2349 0x3: dpsqx_sa_w_ph({{ 2350 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2351 ACDST, SIMD_FMT_PH, 2352 SIMD_FMT_W, SATURATE, 2353 MODE_X, &dspctl); 2354 }}, IntMultOp); |
2005 } 2006 } 2007 } 2008 2009 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2010 0x1: decode OP_HI { 2011 0x0: decode OP_LO { 2012 format IntOp { | 2355 } 2356 } 2357 } 2358 2359 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2360 0x1: decode OP_HI { 2361 0x0: decode OP_LO { 2362 format IntOp { |
2013 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }}); 2014 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw, RD - 1, 0) << (32 - RD)); }}); | 2363 0x0: append({{ 2364 Rt.uw = (Rt.uw << RD) | bits(Rs.uw, RD - 1, 0); 2365 }}); 2366 0x1: prepend({{ 2367 Rt.uw = (Rt.uw >> RD) | 2368 (bits(Rs.uw, RD - 1, 0) << (32 - RD)); 2369 }}); |
2015 } 2016 } 2017 0x2: decode OP_LO { 2018 format IntOp { | 2370 } 2371 } 2372 0x2: decode OP_LO { 2373 format IntOp { |
2019 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }}); | 2374 0x0: balign({{ 2375 Rt.uw = (Rt.uw << (8 * BP)) | 2376 (Rs.uw >> (8 * (4 - BP))); 2377 }}); |
2020 } 2021 } 2022 } 2023 2024 } 2025 0x7: decode FUNCTION_LO { 2026 | 2378 } 2379 } 2380 } 2381 2382 } 2383 0x7: decode FUNCTION_LO { 2384 |
2027 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL) | 2385 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2386 //(DSP ASE MANUAL) |
2028 0x0: decode OP_HI { 2029 0x0: decode OP_LO { 2030 format DspHiLoOp { | 2387 0x0: decode OP_HI { 2388 0x0: decode OP_LO { 2389 format DspHiLoOp { |
2031 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 2032 NOROUND, NOSATURATE, &dspctl ); }}); 2033 0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 2034 NOROUND, NOSATURATE, &dspctl ); }}); 2035 0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }}); 2036 0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }}); 2037 0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 2038 ROUND, NOSATURATE, &dspctl ); }}); 2039 0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 2040 ROUND, NOSATURATE, &dspctl ); }}); 2041 0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 2042 ROUND, SATURATE, &dspctl ); }}); 2043 0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 2044 ROUND, SATURATE, &dspctl ); }}); | 2390 0x0: extr_w({{ 2391 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2392 NOROUND, NOSATURATE, &dspctl); 2393 }}); 2394 0x1: extrv_w({{ 2395 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2396 NOROUND, NOSATURATE, &dspctl); 2397 }}); 2398 0x2: extp({{ 2399 Rt.uw = dspExtp(dspac, RS, &dspctl); 2400 }}); 2401 0x3: extpv({{ 2402 Rt.uw = dspExtp(dspac, Rs.uw, &dspctl); 2403 }}); 2404 0x4: extr_r_w({{ 2405 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2406 ROUND, NOSATURATE, &dspctl); 2407 }}); 2408 0x5: extrv_r_w({{ 2409 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2410 ROUND, NOSATURATE, &dspctl); 2411 }}); 2412 0x6: extr_rs_w({{ 2413 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2414 ROUND, SATURATE, &dspctl); 2415 }}); 2416 0x7: extrv_rs_w({{ 2417 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2418 ROUND, SATURATE, &dspctl); 2419 }}); |
2045 } 2046 } 2047 0x1: decode OP_LO { 2048 format DspHiLoOp { | 2420 } 2421 } 2422 0x1: decode OP_LO { 2423 format DspHiLoOp { |
2049 0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }}); 2050 0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }}); 2051 0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS, 2052 NOROUND, SATURATE, &dspctl ); }}); 2053 0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw, 2054 NOROUND, SATURATE, &dspctl ); }}); | 2424 0x2: extpdp({{ 2425 Rt.uw = dspExtpd(dspac, RS, &dspctl); 2426 }}); 2427 0x3: extpdpv({{ 2428 Rt.uw = dspExtpd(dspac, Rs.uw, &dspctl); 2429 }}); 2430 0x6: extr_s_h({{ 2431 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2432 NOROUND, SATURATE, &dspctl); 2433 }}); 2434 0x7: extrv_s_h({{ 2435 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, Rs.uw, 2436 NOROUND, SATURATE, &dspctl); 2437 }}); |
2055 } 2056 } 2057 0x2: decode OP_LO { 2058 format DspIntOp { | 2438 } 2439 } 2440 0x2: decode OP_LO { 2441 format DspIntOp { |
2059 0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }}); 2060 0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }}); | 2442 0x2: rddsp({{ 2443 Rd.uw = readDSPControl(&dspctl, RDDSPMASK); 2444 }}); 2445 0x3: wrdsp({{ 2446 writeDSPControl(&dspctl, Rs.uw, WRDSPMASK); 2447 }}); |
2061 } 2062 } 2063 0x3: decode OP_LO { 2064 format DspHiLoOp { | 2448 } 2449 } 2450 0x3: decode OP_LO { 2451 format DspHiLoOp { |
2065 0x2: shilo({{ if( sext<6>(HILOSA) < 0 ) 2066 dspac = (uint64_t)dspac << -sext<6>(HILOSA); 2067 else 2068 dspac = (uint64_t)dspac >> sext<6>(HILOSA); }}); 2069 0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 ) 2070 dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>); 2071 else 2072 dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }}); 2073 0x7: mthlip({{ dspac = dspac << 32; 2074 dspac |= Rs.uw; 2075 dspctl = insertBits( dspctl, 5, 0, 2076 dspctl<5:0>+32 ); }}); | 2452 0x2: shilo({{ 2453 if (sext<6>(HILOSA) < 0) { 2454 dspac = (uint64_t)dspac << 2455 -sext<6>(HILOSA); 2456 } else { 2457 dspac = (uint64_t)dspac >> 2458 sext<6>(HILOSA); 2459 } 2460 }}); 2461 0x3: shilov({{ 2462 if (sext<6>(Rs.sw<5:0>) < 0) { 2463 dspac = (uint64_t)dspac << 2464 -sext<6>(Rs.sw<5:0>); 2465 } else { 2466 dspac = (uint64_t)dspac >> 2467 sext<6>(Rs.sw<5:0>); 2468 } 2469 }}); 2470 0x7: mthlip({{ 2471 dspac = dspac << 32; 2472 dspac |= Rs.uw; 2473 dspctl = insertBits(dspctl, 5, 0, 2474 dspctl<5:0> + 32); 2475 }}); |
2077 } 2078 } 2079 } 2080 0x3: decode OP_HI { 2081 0x2: decode OP_LO { 2082 0x3: FailUnimpl::rdhwr(); 2083 } 2084 } 2085 } 2086 } 2087 } 2088 2089 0x4: decode OPCODE_LO { 2090 format LoadMemory { 2091 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT); 2092 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2093 0x3: lw({{ Rt.sw = Mem.sw; }}); 2094 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT); | 2476 } 2477 } 2478 } 2479 0x3: decode OP_HI { 2480 0x2: decode OP_LO { 2481 0x3: FailUnimpl::rdhwr(); 2482 } 2483 } 2484 } 2485 } 2486 } 2487 2488 0x4: decode OPCODE_LO { 2489 format LoadMemory { 2490 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT); 2491 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2492 0x3: lw({{ Rt.sw = Mem.sw; }}); 2493 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT); |
2095 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); | 2494 0x5: lhu({{ Rt.uw = Mem.uh; }}, 2495 mem_flags = NO_HALF_WORD_ALIGN_FAULT); |
2096 } 2097 2098 format LoadUnalignedMemory { | 2496 } 2497 2498 format LoadUnalignedMemory { |
2099 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); 2100 Rt.uw = mem_word << mem_shift | 2101 (Rt.uw & mask(mem_shift)); 2102 }}); 2103 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; 2104 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | 2105 (mem_word >> mem_shift); 2106 }}); 2107 } | 2499 0x2: lwl({{ 2500 uint32_t mem_shift = 24 - (8 * byte_offset); 2501 Rt.uw = mem_word << mem_shift | (Rt.uw & mask(mem_shift)); 2502 }}); 2503 0x6: lwr({{ 2504 uint32_t mem_shift = 8 * byte_offset; 2505 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | 2506 (mem_word >> mem_shift); 2507 }}); 2508 } |
2108 } 2109 2110 0x5: decode OPCODE_LO { 2111 format StoreMemory { 2112 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT); | 2509 } 2510 2511 0x5: decode OPCODE_LO { 2512 format StoreMemory { 2513 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT); |
2113 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); | 2514 0x1: sh({{ Mem.uh = Rt<15:0>; }}, 2515 mem_flags = NO_HALF_WORD_ALIGN_FAULT); |
2114 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 2115 } 2116 2117 format StoreUnalignedMemory { | 2516 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 2517 } 2518 2519 format StoreUnalignedMemory { |
2118 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); 2119 uint32_t mem_shift = 32 - reg_shift; 2120 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2121 (Rt.uw >> reg_shift); 2122 }}); 2123 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; 2124 mem_word = Rt.uw << reg_shift | 2125 (mem_word & (mask(reg_shift))); 2126 }}); | 2520 0x2: swl({{ 2521 uint32_t reg_shift = 24 - (8 * byte_offset); 2522 uint32_t mem_shift = 32 - reg_shift; 2523 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2524 (Rt.uw >> reg_shift); 2525 }}); 2526 0x6: swr({{ 2527 uint32_t reg_shift = 8 * byte_offset; 2528 mem_word = Rt.uw << reg_shift | 2529 (mem_word & (mask(reg_shift))); 2530 }}); |
2127 } 2128 format CP0Control { 2129 0x7: cache({{ 2130 //Addr CacheEA = Rs.uw + OFFSET; | 2531 } 2532 format CP0Control { 2533 0x7: cache({{ 2534 //Addr CacheEA = Rs.uw + OFFSET; |
2131 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2132 }}); | 2535 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2536 }}); |
2133 } 2134 } 2135 2136 0x6: decode OPCODE_LO { 2137 format LoadMemory { 2138 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC); 2139 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 2140 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 2141 } 2142 0x2: CP2Unimpl::lwc2(); 2143 0x6: CP2Unimpl::ldc2(); 2144 0x3: Prefetch::pref(); 2145 } 2146 2147 2148 0x7: decode OPCODE_LO { | 2537 } 2538 } 2539 2540 0x6: decode OPCODE_LO { 2541 format LoadMemory { 2542 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC); 2543 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 2544 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 2545 } 2546 0x2: CP2Unimpl::lwc2(); 2547 0x6: CP2Unimpl::ldc2(); 2548 0x3: Prefetch::pref(); 2549 } 2550 2551 2552 0x7: decode OPCODE_LO { |
2149 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, | 2553 0x0: StoreCond::sc({{ Mem.uw = Rt.uw; }}, |
2150 {{ uint64_t tmp = write_result; 2151 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; | 2554 {{ uint64_t tmp = write_result; 2555 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; |
2152 }}, mem_flags=LLSC, inst_flags = IsStoreConditional); 2153 | 2556 }}, mem_flags=LLSC, 2557 inst_flags = IsStoreConditional); |
2154 format StoreMemory { | 2558 format StoreMemory { |
2155 0x1: swc1({{ Mem.uw = Ft.uw;}}); 2156 0x5: sdc1({{ Mem.ud = Ft.ud;}}); | 2559 0x1: swc1({{ Mem.uw = Ft.uw; }}); 2560 0x5: sdc1({{ Mem.ud = Ft.ud; }}); |
2157 } | 2561 } |
2158 | |
2159 0x2: CP2Unimpl::swc2(); 2160 0x6: CP2Unimpl::sdc2(); | 2562 0x2: CP2Unimpl::swc2(); 2563 0x6: CP2Unimpl::sdc2(); |
2161 | |
2162 } 2163} 2164 2165 | 2564 } 2565} 2566 2567 |