decoder.isa (6379:75d4aaf7dd54) decoder.isa (6383:31c067ae3331)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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401 0x8: decode MT_U {
402 0x0: mftc0({{
403 data = xc->readRegOtherThread((RT << 3 | SEL) +
404 Ctrl_Base_DepTag);
405 }});
406 0x1: decode SEL {
407 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
408 0x1: decode RT {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 392 unchanged lines hidden (view full) ---

401 0x8: decode MT_U {
402 0x0: mftc0({{
403 data = xc->readRegOtherThread((RT << 3 | SEL) +
404 Ctrl_Base_DepTag);
405 }});
406 0x1: decode SEL {
407 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
408 0x1: decode RT {
409 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }});
410 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }});
411 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }});
412 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }});
413 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }});
414 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
415 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
416 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
417 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
418 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
419 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
420 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
421 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
409 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }});
410 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }});
411 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }});
412 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }});
413 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }});
414 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }});
415 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }});
416 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }});
417 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }});
418 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }});
419 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }});
420 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }});
421 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }});
422 default: CP0Unimpl::unknown();
423 }
424 0x2: decode MT_H {
425 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
426 FP_Base_DepTag);
427 }});
428 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
429 FP_Base_DepTag);
430 }});
431 }
422 default: CP0Unimpl::unknown();
423 }
424 0x2: decode MT_H {
425 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
426 FP_Base_DepTag);
427 }});
428 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
429 FP_Base_DepTag);
430 }});
431 }
432 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
432 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
433 FP_Base_DepTag);
434 switch (RT)
435 {
436 case 0:
433 FP_Base_DepTag);
434 switch (RT)
435 {
436 case 0:
437 data = xc->readRegOtherThread(MipsISA::FIR +
437 data = xc->readRegOtherThread(FLOATREG_FIR +
438 Ctrl_Base_DepTag);
439 break;
440 case 25:
441 data = (fcsr_val & 0xFE000000 >> 24)
442 | (fcsr_val & 0x00800000 >> 23);
443 break;
444 case 26:
445 data = fcsr_val & 0x0003F07C;

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464 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
465 0xC: decode MT_U {
466 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
467 Rt);
468 }});
469 0x1: decode SEL {
470 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
471 0x1: decode RT {
438 Ctrl_Base_DepTag);
439 break;
440 case 25:
441 data = (fcsr_val & 0xFE000000 >> 24)
442 | (fcsr_val & 0x00800000 >> 23);
443 break;
444 case 26:
445 data = fcsr_val & 0x0003F07C;

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464 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
465 0xC: decode MT_U {
466 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
467 Rt);
468 }});
469 0x1: decode SEL {
470 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
471 0x1: decode RT {
472 0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt);
472 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt);
473 }});
473 }});
474 0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0,
474 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0,
475 Rt);
476 }});
475 Rt);
476 }});
477 0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0,
477 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0,
478 Rt);
479 }});
478 Rt);
479 }});
480 0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1,
480 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1,
481 Rt);
482 }});
481 Rt);
482 }});
483 0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1,
483 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1,
484 Rt);
485 }});
484 Rt);
485 }});
486 0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1,
486 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1,
487 Rt);
488 }});
487 Rt);
488 }});
489 0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2,
489 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2,
490 Rt);
491 }});
490 Rt);
491 }});
492 0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2,
492 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2,
493 Rt);
494 }});
493 Rt);
494 }});
495 0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2,
495 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2,
496 Rt);
497 }});
496 Rt);
497 }});
498 0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3,
498 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3,
499 Rt);
500 }});
499 Rt);
500 }});
501 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
501 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3,
502 Rt);
503 }});
502 Rt);
503 }});
504 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
504 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt);
505 }});
505 }});
506 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
506 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }});
507 default: CP0Unimpl::unknown();
508
509 }
510 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
511 FP_Base_DepTag);
512 data = insertBits(data, top_bit, bottom_bit, Rt);
513 xc->setRegOtherThread(RD + FP_Base_DepTag, data);
514 }});

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541 case 31:
542 data = Rt.uw;
543 break;
544
545 default:
546 panic("FP Control Value (%d) Not Available. Ignoring Access to"
547 "Floating Control Status Register", FS);
548 }
507 default: CP0Unimpl::unknown();
508
509 }
510 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
511 FP_Base_DepTag);
512 data = insertBits(data, top_bit, bottom_bit, Rt);
513 xc->setRegOtherThread(RD + FP_Base_DepTag, data);
514 }});

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541 case 31:
542 data = Rt.uw;
543 break;
544
545 default:
546 panic("FP Control Value (%d) Not Available. Ignoring Access to"
547 "Floating Control Status Register", FS);
548 }
549 xc->setRegOtherThread(FCSR, data);
549 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
550 }});
551 default: CP0Unimpl::unknown();
552 }
553 }
554 }
555
556
557 0xB: decode RD {

--- 1608 unchanged lines hidden --- 		550 }});
551 default: CP0Unimpl::unknown();
552 }
553 }
554 }
555
556
557 0xB: decode RD {

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