decoder.isa (6076:e141cc7896ce) decoder.isa (6376:eaf61ef6a8f2)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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115 }
116 }
117
118 0x1: decode FUNCTION_LO {
119 //Table A-3 Note: "Specific encodings of the hint field are
120 //used to distinguish JR from JR.HB and JALR from JALR.HB"
121 format Jump {
122 0x0: decode HINT {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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115 }
116 }
117
118 0x1: decode FUNCTION_LO {
119 //Table A-3 Note: "Specific encodings of the hint field are
120 //used to distinguish JR from JR.HB and JALR from JALR.HB"
121 format Jump {
122 0x0: decode HINT {
123 0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards);
124 default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn);
123 0x1: jr_hb({{
124 Config1Reg config1 = Config1;
125 if (config1.ca == 0) {
126 NNPC = Rs;
127 } else {
128 panic("MIPS16e not supported\n");
129 }
130 }}, IsReturn, ClearHazards);
131 default: jr({{
132 Config1Reg config1 = Config1;
133 if (config1.ca == 0) {
134 NNPC = Rs;
135 } else {
136 panic("MIPS16e not supported\n");
137 }
138 }}, IsReturn);
125 }
126
127 0x1: decode HINT {
128 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
129 , ClearHazards);
130 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
131 }
132 }

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346 }
347 }
348
349 0x2: decode OPCODE_LO {
350 //Table A-11 MIPS32 COP0 Encoding of rs Field
351 0x0: decode RS_MSB {
352 0x0: decode RS {
353 format CP0Control {
139 }
140
141 0x1: decode HINT {
142 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
143 , ClearHazards);
144 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
145 }
146 }

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360 }
361 }
362
363 0x2: decode OPCODE_LO {
364 //Table A-11 MIPS32 COP0 Encoding of rs Field
365 0x0: decode RS_MSB {
366 0x0: decode RS {
367 format CP0Control {
354 0x0: mfc0({{ Rt = CP0_RD_SEL;
355 /* Hack for PageMask */
356 if(RD == 5) // PageMask
357 if(Config3_SP == 0 || PageGrain_ESP == 0)
358 Rt &= 0xFFFFE7FF;
359 }});
360 0x4: mtc0({{ CP0_RD_SEL = Rt;
361
362 if(RD == 11) // Compare{
363 if(Cause_TI == 1){
364 Cause_TI = 0;
365 MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause);
366 int Offset = 10; // corresponding to Cause_IP0
367 Offset += ((IntCtl_IPTI) - 2);
368 replaceBits(cause,Offset,Offset,0);
369 xc->setMiscRegNoEffect(MipsISA::Cause,cause);
370 }
371
372 }});
368 0x0: mfc0({{
369 Config3Reg config3 = Config3;
370 PageGrainReg pageGrain = PageGrain;
371 Rt = CP0_RD_SEL;
372 /* Hack for PageMask */
373 if (RD == 5) {
374 // PageMask
375 if(config3.sp == 0 || pageGrain.esp == 0)
376 Rt &= 0xFFFFE7FF;
377 }
378 }});
379 0x4: mtc0({{
380 CP0_RD_SEL = Rt;
381 CauseReg cause = Cause;
382 IntCtlReg intCtl = IntCtl;
383 if (RD == 11) {
384 // Compare
385 if (cause.ti == 1) {
386 cause.ti = 0;
387 int offset = 10; // corresponding to cause.ip0
388 offset += intCtl.ipti - 2;
389 replaceBits(cause, offset, offset, 0);
390 }
391 }
392 Cause = cause;
393 }});
373 }
374 format CP0Unimpl {
375 0x1: dmfc0();
376 0x5: dmtc0();
377 default: unknown();
378 }
379 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
380 0x8: decode MT_U {
394 }
395 format CP0Unimpl {
396 0x1: dmfc0();
397 0x5: dmtc0();
398 default: unknown();
399 }
400 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
401 0x8: decode MT_U {
381 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
382 Ctrl_Base_DepTag);
383 }});
402 0x0: mftc0({{
403 data = xc->readRegOtherThread((RT << 3 | SEL) +
404 Ctrl_Base_DepTag);
405 }});
384 0x1: decode SEL {
385 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
386 0x1: decode RT {
387 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }});
388 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }});
389 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }});
390 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }});
391 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }});

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532 }
533
534
535 0xB: decode RD {
536 format MT_Control {
537 0x0: decode POS {
538 0x0: decode SEL {
539 0x1: decode SC {
406 0x1: decode SEL {
407 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
408 0x1: decode RT {
409 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }});
410 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }});
411 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }});
412 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }});
413 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }});

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554 }
555
556
557 0xB: decode RD {
558 format MT_Control {
559 0x0: decode POS {
560 0x0: decode SEL {
561 0x1: decode SC {
540 0x0: dvpe({{ Rt = MVPControl;
541 if (VPEConf0<VPEC0_MVP:> == 1) {
542 MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
543 }
544 }});
545 0x1: evpe({{ Rt = MVPControl;
546 if (VPEConf0<VPEC0_MVP:> == 1) {
547 MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
548 }
549 }});
562 0x0: dvpe({{
563 MVPControlReg mvpControl = MVPControl;
564 VPEConf0Reg vpeConf0 = VPEConf0;
565 Rt = MVPControl;
566 if (vpeConf0.mvp == 1)
567 mvpControl.evp = 0;
568 MVPControl = mvpControl;
569 }});
570 0x1: evpe({{
571 MVPControlReg mvpControl = MVPControl;
572 VPEConf0Reg vpeConf0 = VPEConf0;
573 Rt = MVPControl;
574 if (vpeConf0.mvp == 1)
575 mvpControl.evp = 1;
576 MVPControl = mvpControl;
577 }});
550 default:CP0Unimpl::unknown();
551 }
552 default:CP0Unimpl::unknown();
553 }
554 default:CP0Unimpl::unknown();
555 }
556
557 0x1: decode POS {
558 0xF: decode SEL {
559 0x1: decode SC {
578 default:CP0Unimpl::unknown();
579 }
580 default:CP0Unimpl::unknown();
581 }
582 default:CP0Unimpl::unknown();
583 }
584
585 0x1: decode POS {
586 0xF: decode SEL {
587 0x1: decode SC {
560 0x0: dmt({{ Rt = VPEControl;
561 VPEControl = insertBits(VPEControl, VPEC_TE, 0);
562 }});
563 0x1: emt({{ Rt = VPEControl;
564 VPEControl = insertBits(VPEControl, VPEC_TE, 1);
565 }});
588 0x0: dmt({{
589 VPEControlReg vpeControl = VPEControl;
590 Rt = vpeControl;
591 vpeControl.te = 0;
592 VPEControl = vpeControl;
593 }});
594 0x1: emt({{
595 VPEControlReg vpeControl = VPEControl;
596 Rt = vpeControl;
597 vpeControl.te = 1;
598 VPEControl = vpeControl;
599 }});
566 default:CP0Unimpl::unknown();
567 }
568 default:CP0Unimpl::unknown();
569 }
570 default:CP0Unimpl::unknown();
571 }
572 }
573 0xC: decode POS {
574 0x0: decode SC {
575 0x0: CP0Control::di({{
600 default:CP0Unimpl::unknown();
601 }
602 default:CP0Unimpl::unknown();
603 }
604 default:CP0Unimpl::unknown();
605 }
606 }
607 0xC: decode POS {
608 0x0: decode SC {
609 0x0: CP0Control::di({{
576 if(Config_AR >= 1) // Rev 2.0 or beyond?
577 {
578 Rt = Status;
579 Status_IE = 0;
580 }
581 else // Enable this else branch once we actually set values for Config on init
582 {
610 StatusReg status = Status;
611 ConfigReg config = Config;
612 // Rev 2.0 or beyond?
613 if (config.ar >= 1) {
614 Rt = status;
615 status.ie = 0;
616 } else {
617 // Enable this else branch once we
618 // actually set values for Config on init
583 fault = new ReservedInstructionFault();
619 fault = new ReservedInstructionFault();
584 }
585 }});
620 }
621 Status = status;
622 }});
586 0x1: CP0Control::ei({{
623 0x1: CP0Control::ei({{
587 if(Config_AR >= 1)
588 {
589 Rt = Status;
590 Status_IE = 1;
591 }
592 else
593 {
624 StatusReg status = Status;
625 ConfigReg config = Config;
626 if (config.ar >= 1) {
627 Rt = status;
628 status.ie = 1;
629 } else {
594 fault = new ReservedInstructionFault();
630 fault = new ReservedInstructionFault();
595 }
596 }});
631 }
632 }});
597 default:CP0Unimpl::unknown();
598 }
599 }
600 default: CP0Unimpl::unknown();
601 }
602 format CP0Control {
603 0xA: rdpgpr({{
633 default:CP0Unimpl::unknown();
634 }
635 }
636 default: CP0Unimpl::unknown();
637 }
638 format CP0Control {
639 0xA: rdpgpr({{
604 if(Config_AR >= 1)
605 { // Rev 2 of the architecture
606 panic("Shadow Sets Not Fully Implemented.\n");
607 //Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS);
608 }
609 else
610 {
640 ConfigReg config = Config;
641 if (config.ar >= 1) {
642 // Rev 2 of the architecture
643 panic("Shadow Sets Not Fully Implemented.\n");
644 } else {
611 fault = new ReservedInstructionFault();
612 }
645 fault = new ReservedInstructionFault();
646 }
613 }});
647 }});
614 0xE: wrpgpr({{
648 0xE: wrpgpr({{
615 if(Config_AR >= 1)
616 { // Rev 2 of the architecture
617 panic("Shadow Sets Not Fully Implemented.\n");
618 //xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt);
619 // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl);
649 ConfigReg config = Config;
650 if (config.ar >= 1) {
651 // Rev 2 of the architecture
652 panic("Shadow Sets Not Fully Implemented.\n");
653 } else {
654 fault = new ReservedInstructionFault();
620 }
655 }
621 else
622 {
623 fault = new ReservedInstructionFault();
624 }
625
626 }});
656 }});
627 }
628
629 }
630
631 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
632 0x1: decode FUNCTION {
633 format CP0Control {
634 0x18: eret({{
657 }
658
659 }
660
661 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
662 0x1: decode FUNCTION {
663 format CP0Control {
664 0x18: eret({{
635 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
636 // Ugly hack to get the value of Status_EXL
637 if(Status_EXL == 1){
638 DPRINTF(MipsPRA,"ERET EXL Hack\n");
639 }
640 if(Status_ERL == 1){
641 Status_ERL = 0;
642 NPC = ErrorEPC;
643 NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
644 }
645 else {
646 NPC = EPC;
647 NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
648 Status_EXL = 0;
649 if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){
650 SRSCtl_CSS = SRSCtl_PSS;
651 //xc->setShadowSet(SRSCtl_PSS);
665 StatusReg status = Status;
666 ConfigReg config = Config;
667 SRSCtlReg srsCtl = SRSCtl;
668 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
669 if (status.erl == 1) {
670 status.erl = 0;
671 NPC = ErrorEPC;
672 // Need to adjust NNPC, otherwise things break
673 NNPC = ErrorEPC + sizeof(MachInst);
674 } else {
675 NPC = EPC;
676 // Need to adjust NNPC, otherwise things break
677 NNPC = EPC + sizeof(MachInst);
678 status.exl = 0;
679 if (config.ar >=1 &&
680 srsCtl.hss > 0 &&
681 status.bev == 0) {
682 srsCtl.css = srsCtl.pss;
683 //xc->setShadowSet(srsCtl.pss);
684 }
652 }
685 }
653 }
654 LLFlag = 0;
655 }},IsReturn,IsSerializing,IsERET);
686 LLFlag = 0;
687 Status = status;
688 SRSCtl = srsCtl;
689 }},IsReturn,IsSerializing,IsERET);
656
657 0x1F: deret({{
690
691 0x1F: deret({{
658 // if(EJTagImplemented()) {
659 if(Debug_DM == 1){
660 Debug_DM = 1;
661 Debug_IEXI = 0;
662 NPC = DEPC;
663 }
664 else
665 {
666 // Undefined;
692 DebugReg debug = Debug;
693 if (debug.dm == 1) {
694 debug.dm = 1;
695 debug.iexi = 0;
696 NPC = DEPC;
697 } else {
698 // Undefined;
667 }
699 }
668 //} // EJTag Implemented
669 //else {
670 // Reserved Instruction Exception
671 //}
672 }},IsReturn,IsSerializing,IsERET);
700 Debug = debug;
701 }}, IsReturn, IsSerializing, IsERET);
673 }
674 format CP0TLB {
675 0x01: tlbr({{
676 MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF);
677 if(PTEntry == NULL)
678 {
679 fatal("Invalid PTE Entry received on a TLBR instruction\n");
680 }
681 /* Setup PageMask */
682 PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11
683 /* Setup EntryHi */
684 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
685 /* Setup Entry Lo0 */
686 EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G);
687 /* Setup Entry Lo1 */
688 EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G);
689 }}); // Need to hook up to TLB
690
691 0x02: tlbwi({{
702 }
703 format CP0TLB {
704 0x01: tlbr({{
705 MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF);
706 if(PTEntry == NULL)
707 {
708 fatal("Invalid PTE Entry received on a TLBR instruction\n");
709 }
710 /* Setup PageMask */
711 PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11
712 /* Setup EntryHi */
713 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
714 /* Setup Entry Lo0 */
715 EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G);
716 /* Setup Entry Lo1 */
717 EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G);
718 }}); // Need to hook up to TLB
719
720 0x02: tlbwi({{
692 //Create PTE
693 MipsISA::PTE NewEntry;
694 //Write PTE
695 NewEntry.Mask = (Addr)(PageMask >> 11);
696 NewEntry.VPN = (Addr)(EntryHi >> 11);
697 /* PageGrain _ ESP Config3 _ SP */
698 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
699 NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
700 NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
701 }
702 NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
721 //Create PTE
722 MipsISA::PTE NewEntry;
723 //Write PTE
724 NewEntry.Mask = (Addr)(PageMask >> 11);
725 NewEntry.VPN = (Addr)(EntryHi >> 11);
726 /* PageGrain _ ESP Config3 _ SP */
727 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
728 // If 1KB pages are *NOT* enabled, lowest bits of the
729 // mask are 0b11 for TLB writes
730 NewEntry.Mask |= 0x3;
731 // Reset bits 0 and 1 if 1KB pages are not enabled
732 NewEntry.VPN &= 0xFFFFFFFC;
733 }
734 NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
703
735
704 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
705 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
706 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
707 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
708 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
709 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
710 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
711 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
712 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
713 /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
714 /* Addr Shift Amount for 1KB or larger pages */
715 // warn("PTE->Mask: %x\n",pte->Mask);
716 if((NewEntry.Mask & 0xFFFF) == 3){
717 NewEntry.AddrShiftAmount = 12;
718 } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
719 NewEntry.AddrShiftAmount = 10;
720 } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
721 NewEntry.AddrShiftAmount = 14;
722 } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
723 NewEntry.AddrShiftAmount = 16;
724 } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
725 NewEntry.AddrShiftAmount = 18;
726 } else if((NewEntry.Mask & 0xFF00) == 0x0300){
727 NewEntry.AddrShiftAmount = 20;
728 } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
729 NewEntry.AddrShiftAmount = 22;
730 } else if((NewEntry.Mask & 0xF000) == 0x3000){
731 NewEntry.AddrShiftAmount = 24;
732 } else if((NewEntry.Mask & 0xC000) == 0xC000){
733 NewEntry.AddrShiftAmount = 26;
734 } else if((NewEntry.Mask & 0x30000) == 0x30000){
735 NewEntry.AddrShiftAmount = 28;
736 } else {
737 fatal("Invalid Mask Pattern Detected!\n");
738 }
739 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
736 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
737 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
738 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
739 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
740 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
741 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
742 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
743 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
744 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
745 /* Now, compute the AddrShiftAmount and OffsetMask - TLB
746 optimizations */
747 /* Addr Shift Amount for 1KB or larger pages */
748 if ((NewEntry.Mask & 0xFFFF) == 3) {
749 NewEntry.AddrShiftAmount = 12;
750 } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) {
751 NewEntry.AddrShiftAmount = 10;
752 } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) {
753 NewEntry.AddrShiftAmount = 14;
754 } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) {
755 NewEntry.AddrShiftAmount = 16;
756 } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) {
757 NewEntry.AddrShiftAmount = 18;
758 } else if ((NewEntry.Mask & 0xFF00) == 0x0300) {
759 NewEntry.AddrShiftAmount = 20;
760 } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) {
761 NewEntry.AddrShiftAmount = 22;
762 } else if ((NewEntry.Mask & 0xF000) == 0x3000) {
763 NewEntry.AddrShiftAmount = 24;
764 } else if ((NewEntry.Mask & 0xC000) == 0xC000) {
765 NewEntry.AddrShiftAmount = 26;
766 } else if ((NewEntry.Mask & 0x30000) == 0x30000) {
767 NewEntry.AddrShiftAmount = 28;
768 } else {
769 fatal("Invalid Mask Pattern Detected!\n");
770 }
771 NewEntry.OffsetMask = ((1<
740
772
741 MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
742 MiscReg c3=xc->readMiscReg(MipsISA::Config3);
743 MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
744 int SP=0;
745 if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
746 SP=1;
747 }
748 Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP);
773 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
774 Config3Reg config3 = Config3
775 PageGrainReg pageGrain = PageGrain;
776 int SP = 0;
777 if (bits(config3, config3.sp) == 1 &&
778 bits(pageGrain, pageGrain.esp) == 1) {
779 SP = 1;
780 }
781 IndexReg index = Index;
782 Ptr->insertAt(NewEntry, Index & 0x7FFFFFFF, SP);
749 }});
750 0x06: tlbwr({{
783 }});
784 0x06: tlbwr({{
751 //Create PTE
752 MipsISA::PTE NewEntry;
753 //Write PTE
754 NewEntry.Mask = (Addr)(PageMask >> 11);
755 NewEntry.VPN = (Addr)(EntryHi >> 11);
756 /* PageGrain _ ESP Config3 _ SP */
757 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
758 NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
759 NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
760 }
761 NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
785 //Create PTE
786 MipsISA::PTE NewEntry;
787 //Write PTE
788 NewEntry.Mask = (Addr)(PageMask >> 11);
789 NewEntry.VPN = (Addr)(EntryHi >> 11);
790 /* PageGrain _ ESP Config3 _ SP */
791 if (((PageGrain >> 28) & 1) == 0 ||
792 (( Config3 >> 4) & 1) ==0) {
793 // If 1KB pages are *NOT* enabled, lowest bits of
794 // the mask are 0b11 for TLB writes
795 NewEntry.Mask |= 0x3;
796 // Reset bits 0 and 1 if 1KB pages are not enabled
797 NewEntry.VPN &= 0xFFFFFFFC;
798 }
799 NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
762
800
763 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
764 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
765 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
766 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
767 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
768 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
769 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
770 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
771 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
772 /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
773 /* Addr Shift Amount for 1KB or larger pages */
774 // warn("PTE->Mask: %x\n",pte->Mask);
775 if((NewEntry.Mask & 0xFFFF) == 3){
776 NewEntry.AddrShiftAmount = 12;
777 } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
778 NewEntry.AddrShiftAmount = 10;
779 } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
780 NewEntry.AddrShiftAmount = 14;
781 } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
782 NewEntry.AddrShiftAmount = 16;
783 } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
784 NewEntry.AddrShiftAmount = 18;
785 } else if((NewEntry.Mask & 0xFF00) == 0x0300){
786 NewEntry.AddrShiftAmount = 20;
787 } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
788 NewEntry.AddrShiftAmount = 22;
789 } else if((NewEntry.Mask & 0xF000) == 0x3000){
790 NewEntry.AddrShiftAmount = 24;
791 } else if((NewEntry.Mask & 0xC000) == 0xC000){
792 NewEntry.AddrShiftAmount = 26;
793 } else if((NewEntry.Mask & 0x30000) == 0x30000){
794 NewEntry.AddrShiftAmount = 28;
795 } else {
796 fatal("Invalid Mask Pattern Detected!\n");
797 }
798 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
801 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
802 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
803 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
804 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
805 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
806 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
807 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
808 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
809 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
810 /* Now, compute the AddrShiftAmount and OffsetMask -
811 TLB optimizations */
812 /* Addr Shift Amount for 1KB or larger pages */
813 if ((NewEntry.Mask & 0xFFFF) == 3){
814 NewEntry.AddrShiftAmount = 12;
815 } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) {
816 NewEntry.AddrShiftAmount = 10;
817 } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) {
818 NewEntry.AddrShiftAmount = 14;
819 } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) {
820 NewEntry.AddrShiftAmount = 16;
821 } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) {
822 NewEntry.AddrShiftAmount = 18;
823 } else if ((NewEntry.Mask & 0xFF00) == 0x0300) {
824 NewEntry.AddrShiftAmount = 20;
825 } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) {
826 NewEntry.AddrShiftAmount = 22;
827 } else if ((NewEntry.Mask & 0xF000) == 0x3000) {
828 NewEntry.AddrShiftAmount = 24;
829 } else if ((NewEntry.Mask & 0xC000) == 0xC000) {
830 NewEntry.AddrShiftAmount = 26;
831 } else if ((NewEntry.Mask & 0x30000) == 0x30000) {
832 NewEntry.AddrShiftAmount = 28;
833 } else {
834 fatal("Invalid Mask Pattern Detected!\n");
835 }
836 NewEntry.OffsetMask = ((1 << NewEntry.AddrShiftAmount) - 1);
799
837
800 MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
801 MiscReg c3=xc->readMiscReg(MipsISA::Config3);
802 MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
803 int SP=0;
804 if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
805 SP=1;
806 }
807 Ptr->insertAt(NewEntry,Random,SP);
838 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
839 Config3Reg config3 = Config3
840 PageGrainReg pageGrain = PageGrain;
841 int SP = 0;
842 if (bits(config3, config3.sp) == 1 &&
843 bits(pageGrain, pageGrain.esp) == 1) {
844 SP = 1;
845 }
846 IndexReg index = Index;
847 Ptr->insertAt(NewEntry, Random, SP);
808 }});
809
810 0x08: tlbp({{
848 }});
849
850 0x08: tlbp({{
811 int TLB_Index;
812 Addr VPN;
813 if(PageGrain_ESP == 1 && Config3_SP ==1){
814 VPN = EntryHi >> 11;
815 } else {
816 VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits
817 }
818 TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID);
819 if(TLB_Index != -1){ // Check TLB for entry matching EntryHi
820 Index=TLB_Index;
821 // warn("\ntlbp: Match Found!\n");
822 } else {// else, set Index = 1<<31
823 Index = (1<<31);
824 }
825 }});
851 Config3Reg config3 = Config3;
852 PageGrainReg pageGrain = PageGrain;
853 EntryHiReg entryHi = EntryHi;
854 int TLB_Index;
855 Addr VPN;
856 if (pageGrain.esp == 1 && config3.sp ==1) {
857 VPN = EntryHi >> 11;
858 } else {
859 // Mask off lower 2 bits
860 VPN = ((EntryHi >> 11) & 0xFFFFFFFC);
861 }
862 TLB_Index = xc->tcBase()->getITBPtr()->
863 probeEntry(VPN, entryHi.asid);
864 // Check TLB for entry matching EntryHi
865 if (TLB_Index != -1) {
866 Index = TLB_Index;
867 } else {
868 // else, set Index = 1 << 31
869 Index = (1 << 31);
870 }
871 }});
826 }
827 format CP0Unimpl {
828 0x20: wait();
829 }
830 default: CP0Unimpl::unknown();
831
832 }
833 }

--- 1286 unchanged lines hidden --- 		872 }
873 format CP0Unimpl {
874 0x20: wait();
875 }
876 default: CP0Unimpl::unknown();
877
878 }
879 }

--- 1286 unchanged lines hidden ---