decoder.isa (6037:0b0341bfb359) decoder.isa (6076:e141cc7896ce)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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2084 //Addr CacheEA = Rs.uw + OFFSET;
2085 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
2086 }});
2087 }
2088 }
2089
2090 0x6: decode OPCODE_LO {
2091 format LoadMemory {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 2075 unchanged lines hidden (view full) ---

2084 //Addr CacheEA = Rs.uw + OFFSET;
2085 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
2086 }});
2087 }
2088 }
2089
2090 0x6: decode OPCODE_LO {
2091 format LoadMemory {
2092 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
2092 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC);
2093 0x1: lwc1({{ Ft.uw = Mem.uw; }});
2094 0x5: ldc1({{ Ft.ud = Mem.ud; }});
2095 }
2096 0x2: CP2Unimpl::lwc2();
2097 0x6: CP2Unimpl::ldc2();
2098 0x3: Prefetch::pref();
2099 }
2100
2101
2102 0x7: decode OPCODE_LO {
2103 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
2104 {{ uint64_t tmp = write_result;
2105 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
2093 0x1: lwc1({{ Ft.uw = Mem.uw; }});
2094 0x5: ldc1({{ Ft.ud = Mem.ud; }});
2095 }
2096 0x2: CP2Unimpl::lwc2();
2097 0x6: CP2Unimpl::ldc2();
2098 0x3: Prefetch::pref();
2099 }
2100
2101
2102 0x7: decode OPCODE_LO {
2103 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
2104 {{ uint64_t tmp = write_result;
2105 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
2106 }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
2106 }}, mem_flags=LLSC, inst_flags = IsStoreConditional);
2107
2108 format StoreMemory {
2109 0x1: swc1({{ Mem.uw = Ft.uw;}});
2110 0x5: sdc1({{ Mem.ud = Ft.ud;}});
2111 }
2112
2113 0x2: CP2Unimpl::swc2();
2114 0x6: CP2Unimpl::sdc2();
2115
2116 }
2117}
2118
2119
2107
2108 format StoreMemory {
2109 0x1: swc1({{ Mem.uw = Ft.uw;}});
2110 0x5: sdc1({{ Mem.ud = Ft.ud;}});
2111 }
2112
2113 0x2: CP2Unimpl::swc2();
2114 0x6: CP2Unimpl::sdc2();
2115
2116 }
2117}
2118
2119