decoder.isa (4828:768d4cf6b0dc) decoder.isa (5222:bb733a878f85)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
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15// this software without specific prior written permission.
16//
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18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30// Brett Miller
3// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
31
4
5// This software is part of the M5 simulator.
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19// advertising or publicity pertaining to the use or distribution of
20// this software without specific, written prior authorization.
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23// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
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33// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
34
35//Authors: Korey L. Sewell
36// Brett Miller
37// Jaidev Patwardhan
38
32////////////////////////////////////////////////////////////////////
33//
34// The actual MIPS32 ISA decoder
35// -----------------------------
36// The following instructions are specified in the MIPS32 ISA
37// Specification. Decoding closely follows the style specified
38// in the MIPS32 ISA specification document starting with Table
39// A-2 (document available @ http://www.mips.com)

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52
53 format BasicOp {
54 //Table A-3 Note: "Specific encodings of the rd, rs, and
55 //rt fields are used to distinguish SLL, SSNOP, and EHB
56 //functions
57 0x0: decode RS {
58 0x0: decode RT_RD {
59 0x0: decode SA default Nop::nop() {
39////////////////////////////////////////////////////////////////////
40//
41// The actual MIPS32 ISA decoder
42// -----------------------------
43// The following instructions are specified in the MIPS32 ISA
44// Specification. Decoding closely follows the style specified
45// in the MIPS32 ISA specification document starting with Table
46// A-2 (document available @ http://www.mips.com)

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59
60 format BasicOp {
61 //Table A-3 Note: "Specific encodings of the rd, rs, and
62 //rt fields are used to distinguish SLL, SSNOP, and EHB
63 //functions
64 0x0: decode RS {
65 0x0: decode RT_RD {
66 0x0: decode SA default Nop::nop() {
60 0x1: WarnUnimpl::ssnop();
61 0x3: WarnUnimpl::ehb();
67 0x1: ssnop({{;}});
68 0x3: ehb({{;}});
62 }
63 default: sll({{ Rd = Rt.uw << SA; }});
64 }
65 }
66
67 0x2: decode RS_SRL {
68 0x0:decode SRL {
69 0: srl({{ Rd = Rt.uw >> SA; }});

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114 }
115 }
116
117 0x1: decode FUNCTION_LO {
118 //Table A-3 Note: "Specific encodings of the hint field are
119 //used to distinguish JR from JR.HB and JALR from JALR.HB"
120 format Jump {
121 0x0: decode HINT {
69 }
70 default: sll({{ Rd = Rt.uw << SA; }});
71 }
72 }
73
74 0x2: decode RS_SRL {
75 0x0:decode SRL {
76 0: srl({{ Rd = Rt.uw >> SA; }});

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121 }
122 }
123
124 0x1: decode FUNCTION_LO {
125 //Table A-3 Note: "Specific encodings of the hint field are
126 //used to distinguish JR from JR.HB and JALR from JALR.HB"
127 format Jump {
128 0x0: decode HINT {
122 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
123 default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
129 0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards);
130 default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn);
124 }
125
126 0x1: decode HINT {
127 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
128 , ClearHazards);
129 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
130 }
131 }
132
133 format BasicOp {
134 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
135 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
131 }
132
133 0x1: decode HINT {
134 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
135 , ClearHazards);
136 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
137 }
138 }
139
140 format BasicOp {
141 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
142 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
143#if FULL_SYSTEM
144 0x4: syscall({{
145 fault = new SystemCallFault();
146 }});
147#else
136 0x4: syscall({{ xc->syscall(R2); }},
148 0x4: syscall({{ xc->syscall(R2); }},
137 IsSerializeAfter, IsNonSpeculative,
138 IsSyscall);
149 IsSerializing, IsNonSpeculative);
150#endif
139 0x7: sync({{ ; }}, IsMemBarrier);
151 0x7: sync({{ ; }}, IsMemBarrier);
152 0x5: break({{fault = new BreakpointFault();}});
140 }
141
153 }
154
142 format FailUnimpl {
143 0x5: break();
144 }
145 }
146
147 0x2: decode FUNCTION_LO {
155 }
156
157 0x2: decode FUNCTION_LO {
148 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
158 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess);
149 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
159 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
150 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
160 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess);
151 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
152 }
153
154 0x3: decode FUNCTION_LO {
155 format HiLoRdSelValOp {
161 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
162 }
163
164 0x3: decode FUNCTION_LO {
165 format HiLoRdSelValOp {
156 0x0: mult({{ val = Rs.sd * Rt.sd; }});
157 0x1: multu({{ val = Rs.ud * Rt.ud; }});
166 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp);
167 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp);
158 }
159
160 format HiLoOp {
161 0x2: div({{ if (Rt.sd != 0) {
162 HI0 = Rs.sd % Rt.sd;
163 LO0 = Rs.sd / Rt.sd;
164 }
168 }
169
170 format HiLoOp {
171 0x2: div({{ if (Rt.sd != 0) {
172 HI0 = Rs.sd % Rt.sd;
173 LO0 = Rs.sd / Rt.sd;
174 }
165 }});
175 }}, IntDivOp);
176
166 0x3: divu({{ if (Rt.ud != 0) {
167 HI0 = Rs.ud % Rt.ud;
168 LO0 = Rs.ud / Rt.ud;
169 }
177 0x3: divu({{ if (Rt.ud != 0) {
178 HI0 = Rs.ud % Rt.ud;
179 LO0 = Rs.ud / Rt.ud;
180 }
170 }});
181 }}, IntDivOp);
171 }
172 }
173
174 0x4: decode HINT {
175 0x0: decode FUNCTION_LO {
176 format IntOp {
182 }
183 }
184
185 0x4: decode HINT {
186 0x0: decode FUNCTION_LO {
187 format IntOp {
177 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
188 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */
189 int64_t Src1 = Rs.sw;
190 int64_t Src2 = Rt.sw;
191 int64_t temp_result;
192#if FULL_SYSTEM
193 if(((Src1 >> 31) & 1) == 1)
194 Src1 |= 0x100000000LL;
195#endif
196 temp_result = Src1 + Src2;
197#if FULL_SYSTEM
198 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
199#endif
200 Rd.sw = temp_result;
201#if FULL_SYSTEM
202 } else{
203 fault = new ArithmeticFault();
204 }
205#endif
206
207 }});
178 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
208 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
179 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
209 0x2: sub({{
210 /* More complicated since an SUB can cause an arithmetic overflow exception */
211 int64_t Src1 = Rs.sw;
212 int64_t Src2 = Rt.sw;
213 int64_t temp_result = Src1 - Src2;
214#if FULL_SYSTEM
215 if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){
216#endif
217 Rd.sw = temp_result;
218#if FULL_SYSTEM
219 } else{
220 fault = new ArithmeticFault();
221 }
222#endif
223 }});
180 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
181 0x4: and({{ Rd = Rs & Rt;}});
182 0x5: or({{ Rd = Rs | Rt;}});
183 0x6: xor({{ Rd = Rs ^ Rt;}});
184 0x7: nor({{ Rd = ~(Rs | Rt);}});
185 }
186 }
187 }

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195 }
196 }
197
198 0x6: decode FUNCTION_LO {
199 format Trap {
200 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
201 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
202 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
224 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
225 0x4: and({{ Rd = Rs & Rt;}});
226 0x5: or({{ Rd = Rs | Rt;}});
227 0x6: xor({{ Rd = Rs ^ Rt;}});
228 0x7: nor({{ Rd = ~(Rs | Rt);}});
229 }
230 }
231 }

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239 }
240 }
241
242 0x6: decode FUNCTION_LO {
243 format Trap {
244 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
245 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
246 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
203 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
247 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }});
204 0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
205 0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
206 }
207 }
208 }
209
210 0x1: decode REGIMM_HI {
211 0x0: decode REGIMM_LO {
212 format Branch {
213 0x0: bltz({{ cond = (Rs.sw < 0); }});
214 0x1: bgez({{ cond = (Rs.sw >= 0); }});
215 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
216 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
217 }
218 }
219
220 0x1: decode REGIMM_LO {
248 0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
249 0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
250 }
251 }
252 }
253
254 0x1: decode REGIMM_HI {
255 0x0: decode REGIMM_LO {
256 format Branch {
257 0x0: bltz({{ cond = (Rs.sw < 0); }});
258 0x1: bgez({{ cond = (Rs.sw >= 0); }});
259 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
260 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
261 }
262 }
263
264 0x1: decode REGIMM_LO {
221 format Trap {
222 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
223 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
224 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
225 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
226 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
227 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
265 format TrapImm {
266 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }});
267 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }});
268 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }});
269 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }});
270 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}});
271 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}});
228 }
229 }
230
231 0x2: decode REGIMM_LO {
232 format Branch {
233 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
234 0x1: decode RS {
235 0x0: bal ({{ cond = 1; }}, IsCall, Link);

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263 0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
264 0x6: blez({{ cond = (Rs.sw <= 0); }});
265 0x7: bgtz({{ cond = (Rs.sw > 0); }});
266 }
267 }
268
269 0x1: decode OPCODE_LO {
270 format IntImmOp {
272 }
273 }
274
275 0x2: decode REGIMM_LO {
276 format Branch {
277 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
278 0x1: decode RS {
279 0x0: bal ({{ cond = 1; }}, IsCall, Link);

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307 0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
308 0x6: blez({{ cond = (Rs.sw <= 0); }});
309 0x7: bgtz({{ cond = (Rs.sw > 0); }});
310 }
311 }
312
313 0x1: decode OPCODE_LO {
314 format IntImmOp {
271 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
315 0x0: addi({{
316 int64_t Src1 = Rs.sw;
317 int64_t Src2 = imm;
318 int64_t temp_result;
319#if FULL_SYSTEM
320 if(((Src1 >> 31) & 1) == 1)
321 Src1 |= 0x100000000LL;
322#endif
323 temp_result = Src1 + Src2;
324#if FULL_SYSTEM
325 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
326#endif
327 Rt.sw = temp_result;
328#if FULL_SYSTEM
329 } else{
330 fault = new ArithmeticFault();
331 }
332#endif
333 }});
272 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
273 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
274
275 //Edited to include MIPS AVP Pass/Fail instructions and
276 //default to the sltiu instruction
277 0x3: decode RS_RT_INTIMM {
278 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }});
279 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }});

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289 }
290 }
291 }
292
293 0x2: decode OPCODE_LO {
294 //Table A-11 MIPS32 COP0 Encoding of rs Field
295 0x0: decode RS_MSB {
296 0x0: decode RS {
334 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
335 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
336
337 //Edited to include MIPS AVP Pass/Fail instructions and
338 //default to the sltiu instruction
339 0x3: decode RS_RT_INTIMM {
340 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }});
341 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }});

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351 }
352 }
353 }
354
355 0x2: decode OPCODE_LO {
356 //Table A-11 MIPS32 COP0 Encoding of rs Field
357 0x0: decode RS_MSB {
358 0x0: decode RS {
297 format CP0Control {
298 0x0: mfc0({{ Rt = CP0_RD_SEL; }});
299 0x4: mtc0({{ CP0_RD_SEL = Rt; }});
300 }
359 format CP0Control {
360 0x0: mfc0({{ Rt = CP0_RD_SEL;
361 /* Hack for PageMask */
362 if(RD == 5) // PageMask
363 if(Config3_SP == 0 || PageGrain_ESP == 0)
364 Rt &= 0xFFFFE7FF;
365 }});
366 0x4: mtc0({{ CP0_RD_SEL = Rt;
301
367
368 if(RD == 11) // Compare{
369 if(Cause_TI == 1){
370 Cause_TI = 0;
371 MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause);
372 int Offset = 10; // corresponding to Cause_IP0
373 Offset += ((IntCtl_IPTI) - 2);
374 replaceBits(cause,Offset,Offset,0);
375 xc->setMiscRegNoEffect(MipsISA::Cause,cause);
376 }
302
377
378 }});
379 }
380 format CP0Unimpl {
381 0x1: dmfc0();
382 0x5: dmtc0();
383 default: unknown();
384 }
303 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
304 0x8: decode MT_U {
305 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
306 Ctrl_Base_DepTag);
307 }});
308 0x1: decode SEL {
309 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
310 0x1: decode RT {

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316 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
317 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
318 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
319 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
320 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
321 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
322 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
323 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
385 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
386 0x8: decode MT_U {
387 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
388 Ctrl_Base_DepTag);
389 }});
390 0x1: decode SEL {
391 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
392 0x1: decode RT {

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398 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
399 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
400 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
401 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
402 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
403 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
404 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
405 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
406 default: CP0Unimpl::unknown();
324 }
325 0x2: decode MT_H {
326 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
327 FP_Base_DepTag);
328 }});
329 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
330 FP_Base_DepTag);
331 }});
407 }
408 0x2: decode MT_H {
409 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
410 FP_Base_DepTag);
411 }});
412 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
413 FP_Base_DepTag);
414 }});
332 }
415 }
333 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
334 FP_Base_DepTag);
335 switch (RT)
336 {
337 case 0:
338 data = xc->readRegOtherThread(MipsISA::FIR +
339 Ctrl_Base_DepTag);
340 break;

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352 break;
353 case 31:
354 data = fcsr_val;
355 break;
356 default:
357 fatal("FP Control Value (%d) Not Valid");
358 }
359 }});
416 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
417 FP_Base_DepTag);
418 switch (RT)
419 {
420 case 0:
421 data = xc->readRegOtherThread(MipsISA::FIR +
422 Ctrl_Base_DepTag);
423 break;

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435 break;
436 case 31:
437 data = fcsr_val;
438 break;
439 default:
440 fatal("FP Control Value (%d) Not Valid");
441 }
442 }});
443 default: CP0Unimpl::unknown();
360 }
444 }
361 }
445 }
362 }
363
364 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
365 0xC: decode MT_U {
366 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
367 Rt);
368 }});
369 0x1: decode SEL {

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399 Rt);
400 }});
401 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
402 Rt);
403 }});
404 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
405 }});
406 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
446 }
447
448 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
449 0xC: decode MT_U {
450 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
451 Rt);
452 }});
453 0x1: decode SEL {

--- 29 unchanged lines hidden (view full) ---

483 Rt);
484 }});
485 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
486 Rt);
487 }});
488 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
489 }});
490 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
491 default: CP0Unimpl::unknown();
492
407 }
408 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
409 FP_Base_DepTag);
410 data = insertBits(data, top_bit, bottom_bit, Rt);
411 xc->setRegOtherThread(RD + FP_Base_DepTag, data);
412 }});
413 0x3: cttc1({{ uint32_t data;
414 switch (RD)

--- 26 unchanged lines hidden (view full) ---

441 break;
442
443 default:
444 panic("FP Control Value (%d) Not Available. Ignoring Access to"
445 "Floating Control Status Register", FS);
446 }
447 xc->setRegOtherThread(FCSR, data);
448 }});
493 }
494 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
495 FP_Base_DepTag);
496 data = insertBits(data, top_bit, bottom_bit, Rt);
497 xc->setRegOtherThread(RD + FP_Base_DepTag, data);
498 }});
499 0x3: cttc1({{ uint32_t data;
500 switch (RD)

--- 26 unchanged lines hidden (view full) ---

527 break;
528
529 default:
530 panic("FP Control Value (%d) Not Available. Ignoring Access to"
531 "Floating Control Status Register", FS);
532 }
533 xc->setRegOtherThread(FCSR, data);
534 }});
535 default: CP0Unimpl::unknown();
449 }
450 }
451 }
452
453
454 0xB: decode RD {
455 format MT_Control {
456 0x0: decode POS {

--- 4 unchanged lines hidden (view full) ---

461 MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
462 }
463 }});
464 0x1: evpe({{ Rt = MVPControl;
465 if (VPEConf0<VPEC0_MVP:> == 1) {
466 MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
467 }
468 }});
536 }
537 }
538 }
539
540
541 0xB: decode RD {
542 format MT_Control {
543 0x0: decode POS {

--- 4 unchanged lines hidden (view full) ---

548 MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
549 }
550 }});
551 0x1: evpe({{ Rt = MVPControl;
552 if (VPEConf0<VPEC0_MVP:> == 1) {
553 MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
554 }
555 }});
556 default:CP0Unimpl::unknown();
469 }
557 }
558 default:CP0Unimpl::unknown();
470 }
559 }
471 }
560 default:CP0Unimpl::unknown();
561 }
472
473 0x1: decode POS {
474 0xF: decode SEL {
475 0x1: decode SC {
476 0x0: dmt({{ Rt = VPEControl;
477 VPEControl = insertBits(VPEControl, VPEC_TE, 0);
478 }});
479 0x1: emt({{ Rt = VPEControl;
480 VPEControl = insertBits(VPEControl, VPEC_TE, 1);
481 }});
562
563 0x1: decode POS {
564 0xF: decode SEL {
565 0x1: decode SC {
566 0x0: dmt({{ Rt = VPEControl;
567 VPEControl = insertBits(VPEControl, VPEC_TE, 0);
568 }});
569 0x1: emt({{ Rt = VPEControl;
570 VPEControl = insertBits(VPEControl, VPEC_TE, 1);
571 }});
482
572 default:CP0Unimpl::unknown();
483 }
573 }
574 default:CP0Unimpl::unknown();
484 }
575 }
576 default:CP0Unimpl::unknown();
485 }
486 }
487 0xC: decode POS {
488 0x0: decode SC {
489 0x0: CP0Control::di({{
490 if(Config_AR >= 1) // Rev 2.0 or beyond?
491 {
492 Rt = Status;

--- 10 unchanged lines hidden (view full) ---

503 Rt = Status;
504 Status_IE = 1;
505 }
506 else
507 {
508 fault = new ReservedInstructionFault();
509 }
510 }});
577 }
578 }
579 0xC: decode POS {
580 0x0: decode SC {
581 0x0: CP0Control::di({{
582 if(Config_AR >= 1) // Rev 2.0 or beyond?
583 {
584 Rt = Status;

--- 10 unchanged lines hidden (view full) ---

595 Rt = Status;
596 Status_IE = 1;
597 }
598 else
599 {
600 fault = new ReservedInstructionFault();
601 }
602 }});
603 default:CP0Unimpl::unknown();
511 }
512 }
604 }
605 }
606 default: CP0Unimpl::unknown();
513 }
607 }
514
515 format CP0Control {
516 0xA: rdpgpr({{
517 if(Config_AR >= 1)
518 { // Rev 2 of the architecture
608 format CP0Control {
609 0xA: rdpgpr({{
610 if(Config_AR >= 1)
611 { // Rev 2 of the architecture
519 Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
612 Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS);
520 }
521 else
522 {
523 fault = new ReservedInstructionFault();
524 }
525 }});
526 0xE: wrpgpr({{
527 if(Config_AR >= 1)
528 { // Rev 2 of the architecture
613 }
614 else
615 {
616 fault = new ReservedInstructionFault();
617 }
618 }});
619 0xE: wrpgpr({{
620 if(Config_AR >= 1)
621 { // Rev 2 of the architecture
529 xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
622 xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt);
623 // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl);
530 }
531 else
532 {
533 fault = new ReservedInstructionFault();
534 }
535
536 }});
624 }
625 else
626 {
627 fault = new ReservedInstructionFault();
628 }
629
630 }});
537
538 }
539
631 }
632
540 }
633 }
541
542 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
543 0x1: decode FUNCTION {
544 format CP0Control {
545 0x18: eret({{
634
635 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
636 0x1: decode FUNCTION {
637 format CP0Control {
638 0x18: eret({{
639 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
640 // Ugly hack to get the value of Status_EXL
641 if(Status_EXL == 1){
642 DPRINTF(MipsPRA,"ERET EXL Hack\n");
643 }
546 if(Status_ERL == 1){
547 Status_ERL = 0;
548 NPC = ErrorEPC;
644 if(Status_ERL == 1){
645 Status_ERL = 0;
646 NPC = ErrorEPC;
647 NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
549 }
648 }
550 else{
649 else {
551 NPC = EPC;
650 NPC = EPC;
651 NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
552 Status_EXL = 0;
652 Status_EXL = 0;
553 if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
653 if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){
554 SRSCtl_CSS = SRSCtl_PSS;
654 SRSCtl_CSS = SRSCtl_PSS;
655 xc->setShadowSet(SRSCtl_PSS);
555 }
556 }
656 }
657 }
557 // LLFlag = 0;
558 // ClearHazards(); ?
559 }});
658 LLFlag = 0;
659 }},IsReturn,IsSerializing,IsERET);
560
561 0x1F: deret({{
660
661 0x1F: deret({{
562 //if(Debug_DM == 1){
563 //Debug_DM = 1;
564 //Debug_IEXI = 0;
565 //NPC = DEPC;
566 //}
567 panic("deret not implemented");
568 }});
662 // if(EJTagImplemented()) {
663 if(Debug_DM == 1){
664 Debug_DM = 1;
665 Debug_IEXI = 0;
666 NPC = DEPC;
667 }
668 else
669 {
670 // Undefined;
671 }
672 //} // EJTag Implemented
673 //else {
674 // Reserved Instruction Exception
675 //}
676 }},IsReturn,IsSerializing,IsERET);
569 }
677 }
678 format CP0TLB {
679 0x01: tlbr({{
680 MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF);
681 if(PTEntry == NULL)
682 {
683 fatal("Invalid PTE Entry received on a TLBR instruction\n");
684 }
685 /* Setup PageMask */
686 PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11
687 /* Setup EntryHi */
688 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
689 /* Setup Entry Lo0 */
690 EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G);
691 /* Setup Entry Lo1 */
692 EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G);
693 }}); // Need to hook up to TLB
570
694
571 format FailUnimpl {
572 0x01: tlbr(); // Need to hook up to TLB
573 0x02: tlbwi(); // Need to hook up to TLB
574 0x06: tlbwr();// Need to hook up to TLB
575 0x08: tlbp();// Need to hook up to TLB
695 0x02: tlbwi({{
696 //Create PTE
697 MipsISA::PTE NewEntry;
698 //Write PTE
699 NewEntry.Mask = (Addr)(PageMask >> 11);
700 NewEntry.VPN = (Addr)(EntryHi >> 11);
701 /* PageGrain _ ESP Config3 _ SP */
702 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
703 NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
704 NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
705 }
706 NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
576
707
577 0x20: wait();
578 }
708 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
709 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
710 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
711 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
712 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
713 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
714 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
715 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
716 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
717 /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
718 /* Addr Shift Amount for 1KB or larger pages */
719 // warn("PTE->Mask: %x\n",pte->Mask);
720 if((NewEntry.Mask & 0xFFFF) == 3){
721 NewEntry.AddrShiftAmount = 12;
722 } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
723 NewEntry.AddrShiftAmount = 10;
724 } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
725 NewEntry.AddrShiftAmount = 14;
726 } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
727 NewEntry.AddrShiftAmount = 16;
728 } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
729 NewEntry.AddrShiftAmount = 18;
730 } else if((NewEntry.Mask & 0xFF00) == 0x0300){
731 NewEntry.AddrShiftAmount = 20;
732 } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
733 NewEntry.AddrShiftAmount = 22;
734 } else if((NewEntry.Mask & 0xF000) == 0x3000){
735 NewEntry.AddrShiftAmount = 24;
736 } else if((NewEntry.Mask & 0xC000) == 0xC000){
737 NewEntry.AddrShiftAmount = 26;
738 } else if((NewEntry.Mask & 0x30000) == 0x30000){
739 NewEntry.AddrShiftAmount = 28;
740 } else {
741 fatal("Invalid Mask Pattern Detected!\n");
742 }
743 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
579
744
745 MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
746 MiscReg c3=xc->readMiscReg(MipsISA::Config3);
747 MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
748 int SP=0;
749 if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
750 SP=1;
751 }
752 Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP);
753 }});
754 0x06: tlbwr({{
755 //Create PTE
756 MipsISA::PTE NewEntry;
757 //Write PTE
758 NewEntry.Mask = (Addr)(PageMask >> 11);
759 NewEntry.VPN = (Addr)(EntryHi >> 11);
760 /* PageGrain _ ESP Config3 _ SP */
761 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
762 NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
763 NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
764 }
765 NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
766
767 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
768 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
769 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
770 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
771 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
772 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
773 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
774 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
775 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
776 /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
777 /* Addr Shift Amount for 1KB or larger pages */
778 // warn("PTE->Mask: %x\n",pte->Mask);
779 if((NewEntry.Mask & 0xFFFF) == 3){
780 NewEntry.AddrShiftAmount = 12;
781 } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
782 NewEntry.AddrShiftAmount = 10;
783 } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
784 NewEntry.AddrShiftAmount = 14;
785 } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
786 NewEntry.AddrShiftAmount = 16;
787 } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
788 NewEntry.AddrShiftAmount = 18;
789 } else if((NewEntry.Mask & 0xFF00) == 0x0300){
790 NewEntry.AddrShiftAmount = 20;
791 } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
792 NewEntry.AddrShiftAmount = 22;
793 } else if((NewEntry.Mask & 0xF000) == 0x3000){
794 NewEntry.AddrShiftAmount = 24;
795 } else if((NewEntry.Mask & 0xC000) == 0xC000){
796 NewEntry.AddrShiftAmount = 26;
797 } else if((NewEntry.Mask & 0x30000) == 0x30000){
798 NewEntry.AddrShiftAmount = 28;
799 } else {
800 fatal("Invalid Mask Pattern Detected!\n");
801 }
802 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
803
804 MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
805 MiscReg c3=xc->readMiscReg(MipsISA::Config3);
806 MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
807 int SP=0;
808 if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
809 SP=1;
810 }
811 Ptr->insertAt(NewEntry,Random,SP);
812 }});
813
814 0x08: tlbp({{
815 int TLB_Index;
816 Addr VPN;
817 if(PageGrain_ESP == 1 && Config3_SP ==1){
818 VPN = EntryHi >> 11;
819 } else {
820 VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits
821 }
822 TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID);
823 if(TLB_Index != -1){ // Check TLB for entry matching EntryHi
824 Index=TLB_Index;
825 // warn("\ntlbp: Match Found!\n");
826 } else {// else, set Index = 1<<31
827 Index = (1<<31);
828 }
829 }});
830 }
831 format CP0Unimpl {
832 0x20: wait();
833 }
834 default: CP0Unimpl::unknown();
835
580 }
581 }
582
583 //Table A-13 MIPS32 COP1 Encoding of rs Field
584 0x1: decode RS_MSB {
585
586 0x0: decode RS_HI {
587 0x0: decode RS_LO {

--- 14 unchanged lines hidden (view full) ---

602 break;
603 case 28:
604 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
605 break;
606 case 31:
607 Rt = FCSR;
608 break;
609 default:
836 }
837 }
838
839 //Table A-13 MIPS32 COP1 Encoding of rs Field
840 0x1: decode RS_MSB {
841
842 0x0: decode RS_HI {
843 0x0: decode RS_LO {

--- 14 unchanged lines hidden (view full) ---

858 break;
859 case 28:
860 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
861 break;
862 case 31:
863 Rt = FCSR;
864 break;
865 default:
610 panic("FP Control Value (%d) Not Valid");
866 warn("FP Control Value (%d) Not Valid");
611 }
867 }
868 // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt);
612 }});
613
614 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
615
616 0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
617
618 0x6: ctc1({{
619 switch (FS)

--- 33 unchanged lines hidden (view full) ---

653
654 0x7: mthc1({{
655 uint64_t fs_hi = Rt.uw;
656 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
657 Fs.ud = (fs_hi << 32) | fs_lo;
658 }});
659
660 }
869 }});
870
871 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
872
873 0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
874
875 0x6: ctc1({{
876 switch (FS)

--- 33 unchanged lines hidden (view full) ---

910
911 0x7: mthc1({{
912 uint64_t fs_hi = Rt.uw;
913 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
914 Fs.ud = (fs_hi << 32) | fs_lo;
915 }});
916
917 }
661 }
662
663 0x1: decode ND {
664 format Branch {
665 0x0: decode TF {
666 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
667 }});
668 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
669 }});
670 }
671 0x1: decode TF {
672 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
673 }}, Likely);
674 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
675 }}, Likely);
676 }
918 format CP1Unimpl {
919 0x1: dmfc1();
920 0x5: dmtc1();
677 }
921 }
678 }
922 }
923
924 0x1:
925 decode RS_LO {
926 0x0:
927 decode ND {
928 format Branch {
929 0x0: decode TF {
930 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
931 }});
932 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
933 }});
934 }
935 0x1: decode TF {
936 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
937 }}, Likely);
938 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
939 }}, Likely);
940 }
941 }
942 }
943 format CP1Unimpl {
944 0x1: bc1any2();
945 0x2: bc1any4();
946 default: unknown();
947 }
948 }
679 }
680
681 0x1: decode RS_HI {
682 0x2: decode RS_LO {
683 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
684 //(( single-precision floating point))
685 0x0: decode FUNCTION_HI {
686 0x0: decode FUNCTION_LO {

--- 43 unchanged lines hidden (view full) ---

730 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
731 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
732 }
733
734 format FloatOp {
735 0x5: recip_s({{ Fd = 1 / Fs; }});
736 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
737 }
949 }
950
951 0x1: decode RS_HI {
952 0x2: decode RS_LO {
953 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
954 //(( single-precision floating point))
955 0x0: decode FUNCTION_HI {
956 0x0: decode FUNCTION_LO {

--- 43 unchanged lines hidden (view full) ---

1000 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
1001 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
1002 }
1003
1004 format FloatOp {
1005 0x5: recip_s({{ Fd = 1 / Fs; }});
1006 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
1007 }
1008 format CP1Unimpl {
1009 default: unknown();
1010 }
738 }
1011 }
1012 0x3: CP1Unimpl::unknown();
739
740 0x4: decode FUNCTION_LO {
741 format FloatConvertOp {
742 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
743 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
744 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
745 }
746
747 0x6: FloatOp::cvt_ps_s({{
748 Fd.ud = (uint64_t) Fs.uw << 32 |
749 (uint64_t) Ft.uw;
750 }});
1013
1014 0x4: decode FUNCTION_LO {
1015 format FloatConvertOp {
1016 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
1017 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
1018 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
1019 }
1020
1021 0x6: FloatOp::cvt_ps_s({{
1022 Fd.ud = (uint64_t) Fs.uw << 32 |
1023 (uint64_t) Ft.uw;
1024 }});
1025 format CP1Unimpl {
1026 default: unknown();
1027 }
751 }
1028 }
1029 0x5: CP1Unimpl::unknown();
752
753 0x6: decode FUNCTION_LO {
754 format FloatCompareOp {
755 0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
756 UnorderedFalse);
757 0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
758 UnorderedTrue);
759 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},

--- 86 unchanged lines hidden (view full) ---

846 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
847 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
848 }
849
850 format FloatOp {
851 0x5: recip_d({{ Fd.df = 1 / Fs.df }});
852 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
853 }
1030
1031 0x6: decode FUNCTION_LO {
1032 format FloatCompareOp {
1033 0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
1034 UnorderedFalse);
1035 0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
1036 UnorderedTrue);
1037 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},

--- 86 unchanged lines hidden (view full) ---

1124 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
1125 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
1126 }
1127
1128 format FloatOp {
1129 0x5: recip_d({{ Fd.df = 1 / Fs.df }});
1130 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
1131 }
854 }
1132 format CP1Unimpl {
1133 default: unknown();
1134 }
855
1135
1136 }
856 0x4: decode FUNCTION_LO {
857 format FloatConvertOp {
858 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
859 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
860 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
861 }
1137 0x4: decode FUNCTION_LO {
1138 format FloatConvertOp {
1139 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
1140 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
1141 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
1142 }
1143 default: CP1Unimpl::unknown();
862 }
863
864 0x6: decode FUNCTION_LO {
865 format FloatCompareOp {
866 0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
867 UnorderedFalse);
868 0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
869 UnorderedTrue);

--- 27 unchanged lines hidden (view full) ---

897 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
898 UnorderedTrue, QnanException);
899 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
900 UnorderedFalse, QnanException);
901 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
902 UnorderedTrue, QnanException);
903 }
904 }
1144 }
1145
1146 0x6: decode FUNCTION_LO {
1147 format FloatCompareOp {
1148 0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
1149 UnorderedFalse);
1150 0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
1151 UnorderedTrue);

--- 27 unchanged lines hidden (view full) ---

1179 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
1180 UnorderedTrue, QnanException);
1181 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
1182 UnorderedFalse, QnanException);
1183 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
1184 UnorderedTrue, QnanException);
1185 }
1186 }
1187 default: CP1Unimpl::unknown();
905 }
1188 }
1189 0x2: CP1Unimpl::unknown();
1190 0x3: CP1Unimpl::unknown();
1191 0x7: CP1Unimpl::unknown();
906
907 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
908 0x4: decode FUNCTION {
909 format FloatConvertOp {
910 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
911 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
1192
1193 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
1194 0x4: decode FUNCTION {
1195 format FloatConvertOp {
1196 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
1197 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
912 0x26: FailUnimpl::cvt_ps_w();
1198 0x26: CP1Unimpl::cvt_ps_w();
913 }
1199 }
1200 default: CP1Unimpl::unknown();
914 }
915
916 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
917 //Note: "1. Format type L is legal only if 64-bit floating point operations
918 //are enabled."
919 0x5: decode FUNCTION_HI {
920 format FloatConvertOp {
921 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
922 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
1201 }
1202
1203 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
1204 //Note: "1. Format type L is legal only if 64-bit floating point operations
1205 //are enabled."
1206 0x5: decode FUNCTION_HI {
1207 format FloatConvertOp {
1208 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
1209 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
923 0x26: FailUnimpl::cvt_ps_l();
1210 0x26: CP1Unimpl::cvt_ps_l();
924 }
1211 }
1212 default: CP1Unimpl::unknown();
925 }
926
927 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
928 //Note: "1. Format type PS is legal only if 64-bit floating point operations
929 //are enabled. "
930 0x6: decode FUNCTION_HI {
931 0x0: decode FUNCTION_LO {
932 format Float64Op {

--- 16 unchanged lines hidden (view full) ---

949 0x6: mov_ps({{
950 Fd1.sf = Fs1.sf;
951 Fd2.sf = Fs2.sf;
952 }});
953 0x7: neg_ps({{
954 Fd1.sf = -(Fs1.sf);
955 Fd2.sf = -(Fs2.sf);
956 }});
1213 }
1214
1215 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
1216 //Note: "1. Format type PS is legal only if 64-bit floating point operations
1217 //are enabled. "
1218 0x6: decode FUNCTION_HI {
1219 0x0: decode FUNCTION_LO {
1220 format Float64Op {

--- 16 unchanged lines hidden (view full) ---

1237 0x6: mov_ps({{
1238 Fd1.sf = Fs1.sf;
1239 Fd2.sf = Fs2.sf;
1240 }});
1241 0x7: neg_ps({{
1242 Fd1.sf = -(Fs1.sf);
1243 Fd2.sf = -(Fs2.sf);
1244 }});
1245 default: CP1Unimpl::unknown();
957 }
958 }
1246 }
1247 }
959
1248 0x1: CP1Unimpl::unknown();
960 0x2: decode FUNCTION_LO {
961 0x1: decode MOVCF {
962 format Float64Op {
963 0x0: movf_ps({{
964 Fd1 = (getCondCode(FCSR, CC) == 0) ?
965 Fs1 : Fd1;
966 Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
967 Fs2 : Fd2;

--- 16 unchanged lines hidden (view full) ---

984 }});
985 0x3: movn_ps({{
986 Fd1 = (getCondCode(FCSR, CC) == 1) ?
987 Fs1 : Fd1;
988 Fd2 = (getCondCode(FCSR, CC) == 1) ?
989 Fs2 : Fd2;
990 }});
991 }
1249 0x2: decode FUNCTION_LO {
1250 0x1: decode MOVCF {
1251 format Float64Op {
1252 0x0: movf_ps({{
1253 Fd1 = (getCondCode(FCSR, CC) == 0) ?
1254 Fs1 : Fd1;
1255 Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
1256 Fs2 : Fd2;

--- 16 unchanged lines hidden (view full) ---

1273 }});
1274 0x3: movn_ps({{
1275 Fd1 = (getCondCode(FCSR, CC) == 1) ?
1276 Fs1 : Fd1;
1277 Fd2 = (getCondCode(FCSR, CC) == 1) ?
1278 Fs2 : Fd2;
1279 }});
1280 }
1281 default: CP1Unimpl::unknown();
992
993 }
1282
1283 }
994
1284 0x3: CP1Unimpl::unknown();
995 0x4: decode FUNCTION_LO {
996 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
1285 0x4: decode FUNCTION_LO {
1286 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
1287 default: CP1Unimpl::unknown();
997 }
998
999 0x5: decode FUNCTION_LO {
1000 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
1001
1002 format Float64Op {
1003 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1004 Ft1.uw;
1005 }});
1006 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1007 Ft2.uw;
1008 }});
1009 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1010 Ft1.uw;
1011 }});
1012 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1013 Ft2.uw;
1014 }});
1015 }
1288 }
1289
1290 0x5: decode FUNCTION_LO {
1291 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
1292
1293 format Float64Op {
1294 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1295 Ft1.uw;
1296 }});
1297 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1298 Ft2.uw;
1299 }});
1300 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1301 Ft1.uw;
1302 }});
1303 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1304 Ft2.uw;
1305 }});
1306 }
1307 default: CP1Unimpl::unknown();
1016 }
1017
1018 0x6: decode FUNCTION_LO {
1019 format FloatPSCompareOp {
1020 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1021 UnorderedFalse);
1022 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1023 UnorderedTrue);

--- 42 unchanged lines hidden (view full) ---

1066 UnorderedFalse, QnanException);
1067 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1068 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1069 UnorderedTrue, QnanException);
1070 }
1071 }
1072 }
1073 }
1308 }
1309
1310 0x6: decode FUNCTION_LO {
1311 format FloatPSCompareOp {
1312 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1313 UnorderedFalse);
1314 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1315 UnorderedTrue);

--- 42 unchanged lines hidden (view full) ---

1358 UnorderedFalse, QnanException);
1359 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1360 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1361 UnorderedTrue, QnanException);
1362 }
1363 }
1364 }
1365 }
1366 default: CP1Unimpl::unknown();
1074 }
1075 }
1076
1077 //Table A-19 MIPS32 COP2 Encoding of rs Field
1078 0x2: decode RS_MSB {
1367 }
1368 }
1369
1370 //Table A-19 MIPS32 COP2 Encoding of rs Field
1371 0x2: decode RS_MSB {
1079 format FailUnimpl {
1372 format CP2Unimpl {
1080 0x0: decode RS_HI {
1081 0x0: decode RS_LO {
1082 0x0: mfc2();
1083 0x2: cfc2();
1084 0x3: mfhc2();
1085 0x4: mtc2();
1086 0x6: ctc2();
1087 0x7: mftc2();
1373 0x0: decode RS_HI {
1374 0x0: decode RS_LO {
1375 0x0: mfc2();
1376 0x2: cfc2();
1377 0x3: mfhc2();
1378 0x4: mtc2();
1379 0x6: ctc2();
1380 0x7: mftc2();
1381 default: unknown();
1088 }
1089
1090 0x1: decode ND {
1091 0x0: decode TF {
1092 0x0: bc2f();
1093 0x1: bc2t();
1382 }
1383
1384 0x1: decode ND {
1385 0x0: decode TF {
1386 0x0: bc2f();
1387 0x1: bc2t();
1388 default: unknown();
1094 }
1095
1096 0x1: decode TF {
1097 0x0: bc2fl();
1098 0x1: bc2tl();
1389 }
1390
1391 0x1: decode TF {
1392 0x0: bc2fl();
1393 0x1: bc2tl();
1394 default: unknown();
1099 }
1395 }
1100 }
1101 }
1396 default: unknown();
1397
1398 }
1399 default: unknown();
1400
1401 }
1402 default: unknown();
1102 }
1103 }
1104
1105 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1106 //Note: "COP1X instructions are legal only if 64-bit floating point
1107 //operations are enabled."
1108 0x3: decode FUNCTION_HI {
1109 0x0: decode FUNCTION_LO {

--- 82 unchanged lines hidden (view full) ---

1192 }
1193
1194 0x3: decode OPCODE_LO {
1195 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1196 0x4: decode FUNCTION_HI {
1197 0x0: decode FUNCTION_LO {
1198 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
1199 Rd.sw = temp1<31:0>;
1403 }
1404 }
1405
1406 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1407 //Note: "COP1X instructions are legal only if 64-bit floating point
1408 //operations are enabled."
1409 0x3: decode FUNCTION_HI {
1410 0x0: decode FUNCTION_LO {

--- 82 unchanged lines hidden (view full) ---

1493 }
1494
1495 0x3: decode OPCODE_LO {
1496 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1497 0x4: decode FUNCTION_HI {
1498 0x0: decode FUNCTION_LO {
1499 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
1500 Rd.sw = temp1<31:0>;
1200 }});
1501 }}, IntMultOp);
1201
1202 format HiLoRdSelValOp {
1502
1503 format HiLoRdSelValOp {
1203 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
1204 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
1205 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
1206 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
1504 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp);
1505 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp);
1506 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp);
1507 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp);
1207 }
1208 }
1209
1210 0x4: decode FUNCTION_LO {
1211 format BasicOp {
1212 0x0: clz({{ int cnt = 32;
1213 for (int idx = 31; idx >= 0; idx--) {
1214 if( Rs<idx:idx> == 1) {

--- 66 unchanged lines hidden (view full) ---

1281 NOSATURATE, UNSIGNED, &dspctl ); }});
1282 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1283 NOSATURATE, UNSIGNED, &dspctl ); }});
1284 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1285 SATURATE, UNSIGNED, &dspctl ); }});
1286 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1287 SATURATE, UNSIGNED, &dspctl ); }});
1288 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1508 }
1509 }
1510
1511 0x4: decode FUNCTION_LO {
1512 format BasicOp {
1513 0x0: clz({{ int cnt = 32;
1514 for (int idx = 31; idx >= 0; idx--) {
1515 if( Rs<idx:idx> == 1) {

--- 66 unchanged lines hidden (view full) ---

1582 NOSATURATE, UNSIGNED, &dspctl ); }});
1583 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1584 NOSATURATE, UNSIGNED, &dspctl ); }});
1585 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1586 SATURATE, UNSIGNED, &dspctl ); }});
1587 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1588 SATURATE, UNSIGNED, &dspctl ); }});
1589 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1289 MODE_L, &dspctl ); }});
1590 MODE_L, &dspctl ); }}, IntMultOp);
1290 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1591 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1291 MODE_R, &dspctl ); }});
1592 MODE_R, &dspctl ); }}, IntMultOp);
1292 }
1293 }
1294 0x1: decode OP_LO {
1295 format DspIntOp {
1296 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1297 NOSATURATE, UNSIGNED, &dspctl ); }});
1298 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1299 NOSATURATE, UNSIGNED, &dspctl ); }});

--- 30 unchanged lines hidden (view full) ---

1330 SATURATE, SIGNED, &dspctl ); }});
1331 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W,
1332 SATURATE, SIGNED, &dspctl ); }});
1333 }
1334 }
1335 0x3: decode OP_LO {
1336 format DspIntOp {
1337 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1593 }
1594 }
1595 0x1: decode OP_LO {
1596 format DspIntOp {
1597 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1598 NOSATURATE, UNSIGNED, &dspctl ); }});
1599 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1600 NOSATURATE, UNSIGNED, &dspctl ); }});

--- 30 unchanged lines hidden (view full) ---

1631 SATURATE, SIGNED, &dspctl ); }});
1632 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W,
1633 SATURATE, SIGNED, &dspctl ); }});
1634 }
1635 }
1636 0x3: decode OP_LO {
1637 format DspIntOp {
1638 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1338 MODE_L, &dspctl ); }});
1639 MODE_L, &dspctl ); }}, IntMultOp);
1339 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1640 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1340 MODE_R, &dspctl ); }});
1641 MODE_R, &dspctl ); }}, IntMultOp);
1341 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1642 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1342 SATURATE, NOROUND, &dspctl ); }});
1643 SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
1343 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1644 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1344 SATURATE, ROUND, &dspctl ); }});
1645 SATURATE, ROUND, &dspctl ); }}, IntMultOp);
1345 }
1346 }
1347 }
1348
1349 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL)
1350 0x1: decode OP_HI {
1351 0x0: decode OP_LO {
1352 format DspIntOp {

--- 201 unchanged lines hidden (view full) ---

1554 NOROUND, SIGNED ); }});
1555 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1556 NOROUND, SIGNED ); }});
1557 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1558 ROUND, SIGNED ); }});
1559 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1560 ROUND, SIGNED ); }});
1561 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1646 }
1647 }
1648 }
1649
1650 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL)
1651 0x1: decode OP_HI {
1652 0x0: decode OP_LO {
1653 format DspIntOp {

--- 201 unchanged lines hidden (view full) ---

1855 NOROUND, SIGNED ); }});
1856 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1857 NOROUND, SIGNED ); }});
1858 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1859 ROUND, SIGNED ); }});
1860 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1861 ROUND, SIGNED ); }});
1862 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1562 NOSATURATE, &dspctl ); }});
1863 NOSATURATE, &dspctl ); }}, IntMultOp);
1563 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1864 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1564 SATURATE, &dspctl ); }});
1865 SATURATE, &dspctl ); }}, IntMultOp);
1866
1565 }
1566 }
1567 0x2: decode OP_LO {
1568 format DspIntOp {
1569 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1570 NOROUND, SIGNED ); }});
1571 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1572 NOROUND, SIGNED ); }});
1573 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1574 ROUND, SIGNED ); }});
1575 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1576 ROUND, SIGNED ); }});
1577 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1867 }
1868 }
1869 0x2: decode OP_LO {
1870 format DspIntOp {
1871 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1872 NOROUND, SIGNED ); }});
1873 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1874 NOROUND, SIGNED ); }});
1875 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1876 ROUND, SIGNED ); }});
1877 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1878 ROUND, SIGNED ); }});
1879 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1578 SATURATE, NOROUND, &dspctl ); }});
1880 SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
1579 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1881 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1580 SATURATE, ROUND, &dspctl ); }});
1882 SATURATE, ROUND, &dspctl ); }}, IntMultOp);
1581 }
1582 }
1583 }
1584 }
1585
1586 //Table A-10 MIPS32 BSHFL Encoding of sa Field
1587 0x4: decode SA {
1588 format BasicOp {

--- 9 unchanged lines hidden (view full) ---

1598
1599 0x6: decode FUNCTION_LO {
1600
1601 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL)
1602 0x0: decode OP_HI {
1603 0x0: decode OP_LO {
1604 format DspHiLoOp {
1605 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1883 }
1884 }
1885 }
1886 }
1887
1888 //Table A-10 MIPS32 BSHFL Encoding of sa Field
1889 0x4: decode SA {
1890 format BasicOp {

--- 9 unchanged lines hidden (view full) ---

1900
1901 0x6: decode FUNCTION_LO {
1902
1903 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL)
1904 0x0: decode OP_HI {
1905 0x0: decode OP_LO {
1906 format DspHiLoOp {
1907 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1606 SIMD_FMT_PH, SIGNED, MODE_L ); }});
1908 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
1607 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1909 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1608 SIMD_FMT_PH, SIGNED, MODE_L ); }});
1910 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
1609 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw,
1911 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw,
1610 ACDST, SIMD_FMT_PH ); }});
1912 ACDST, SIMD_FMT_PH ); }}, IntMultOp);
1611 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1913 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1612 SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1914 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
1613 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1915 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1614 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1916 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1615 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1917 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1616 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1918 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1617 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw,
1919 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw,
1618 ACDST, SIMD_FMT_PH, &dspctl ); }});
1920 ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp);
1619 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1921 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1620 SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1922 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
1621 }
1622 }
1623 0x1: decode OP_LO {
1624 format DspHiLoOp {
1625 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1923 }
1924 }
1925 0x1: decode OP_LO {
1926 format DspHiLoOp {
1927 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1626 SIMD_FMT_PH, SIGNED, MODE_X ); }});
1928 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
1627 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1929 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1628 SIMD_FMT_PH, SIGNED, MODE_X ); }});
1930 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
1629 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1931 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1630 SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1932 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
1631 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1933 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1632 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1934 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1633 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1935 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1634 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1936 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1635 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1937 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1636 SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1938 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
1637 }
1638 }
1639 0x2: decode OP_LO {
1640 format DspHiLoOp {
1641 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1939 }
1940 }
1941 0x2: decode OP_LO {
1942 format DspHiLoOp {
1943 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1642 MODE_L, SATURATE, &dspctl ); }});
1944 MODE_L, SATURATE, &dspctl ); }}, IntMultOp);
1643 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1945 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1644 MODE_R, SATURATE, &dspctl ); }});
1946 MODE_R, SATURATE, &dspctl ); }}, IntMultOp);
1645 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1947 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1646 MODE_L, NOSATURATE, &dspctl ); }});
1948 MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp);
1647 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1949 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1648 MODE_R, NOSATURATE, &dspctl ); }});
1950 MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp);
1649 }
1650 }
1651 0x3: decode OP_LO {
1652 format DspHiLoOp {
1653 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1951 }
1952 }
1953 0x3: decode OP_LO {
1954 format DspHiLoOp {
1955 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1654 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1956 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1655 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1957 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1656 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1958 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1657 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1959 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1658 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1960 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1659 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1961 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1660 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1962 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1661 }
1662 }
1663 }
1664
1665 //Table 3.3 MIPS32 APPEND Encoding of the op Field
1666 0x1: decode OP_HI {
1667 0x0: decode OP_LO {
1668 format IntOp {
1669 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
1670 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
1671 }
1672 }
1673 0x2: decode OP_LO {
1674 format IntOp {
1675 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }});
1676 }
1677 }
1678 }
1679
1963 }
1964 }
1965 }
1966
1967 //Table 3.3 MIPS32 APPEND Encoding of the op Field
1968 0x1: decode OP_HI {
1969 0x0: decode OP_LO {
1970 format IntOp {
1971 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
1972 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
1973 }
1974 }
1975 0x2: decode OP_LO {
1976 format IntOp {
1977 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }});
1978 }
1979 }
1980 }
1981
1680 0x7: FailUnimpl::rdhwr();
1681 }
1982 }
1682
1683 0x7: decode FUNCTION_LO {
1684
1685 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL)
1686 0x0: decode OP_HI {
1687 0x0: decode OP_LO {
1688 format DspHiLoOp {
1689 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1690 NOROUND, NOSATURATE, &dspctl ); }});

--- 39 unchanged lines hidden (view full) ---

1730 dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }});
1731 0x7: mthlip({{ dspac = dspac << 32;
1732 dspac |= Rs.uw;
1733 dspctl = insertBits( dspctl, 5, 0,
1734 dspctl<5:0>+32 ); }});
1735 }
1736 }
1737 }
1983 0x7: decode FUNCTION_LO {
1984
1985 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL)
1986 0x0: decode OP_HI {
1987 0x0: decode OP_LO {
1988 format DspHiLoOp {
1989 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1990 NOROUND, NOSATURATE, &dspctl ); }});

--- 39 unchanged lines hidden (view full) ---

2030 dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }});
2031 0x7: mthlip({{ dspac = dspac << 32;
2032 dspac |= Rs.uw;
2033 dspctl = insertBits( dspctl, 5, 0,
2034 dspctl<5:0>+32 ); }});
2035 }
2036 }
2037 }
2038 0x3: decode OP_HI {
2039 0x2: decode OP_LO {
2040 0x3: FailUnimpl::rdhwr();
2041 }
2042 }
1738 }
1739 }
1740 }
1741
1742 0x4: decode OPCODE_LO {
1743 format LoadMemory {
2043 }
2044 }
2045 }
2046
2047 0x4: decode OPCODE_LO {
2048 format LoadMemory {
1744 0x0: lb({{ Rt.sw = Mem.sb; }});
1745 0x1: lh({{ Rt.sw = Mem.sh; }});
2049 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);
2050 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
1746 0x3: lw({{ Rt.sw = Mem.sw; }});
2051 0x3: lw({{ Rt.sw = Mem.sw; }});
1747 0x4: lbu({{ Rt.uw = Mem.ub; }});
1748 0x5: lhu({{ Rt.uw = Mem.uh; }});
2052 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT);
2053 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
1749 }
1750
1751 format LoadUnalignedMemory {
1752 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1753 Rt.uw = mem_word << mem_shift |
2054 }
2055
2056 format LoadUnalignedMemory {
2057 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
2058 Rt.uw = mem_word << mem_shift |
1754 Rt.uw & mask(mem_shift);
2059 Rt.uw & mask(mem_shift);
1755 }});
1756 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1757 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
2060 }});
2061 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
2062 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1758 mem_word >> mem_shift;
2063 mem_word >> mem_shift;
1759 }});
1760 }
1761 }
1762
1763 0x5: decode OPCODE_LO {
1764 format StoreMemory {
2064 }});
2065 }
2066 }
2067
2068 0x5: decode OPCODE_LO {
2069 format StoreMemory {
1765 0x0: sb({{ Mem.ub = Rt<7:0>; }});
1766 0x1: sh({{ Mem.uh = Rt<15:0>; }});
2070 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT);
2071 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
1767 0x3: sw({{ Mem.uw = Rt<31:0>; }});
1768 }
1769
1770 format StoreUnalignedMemory {
1771 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
1772 uint32_t mem_shift = 32 - reg_shift;
1773 mem_word = mem_word & (mask(reg_shift) << mem_shift) |
1774 Rt.uw >> reg_shift;
1775 }});
1776 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
1777 mem_word = Rt.uw << reg_shift |
1778 mem_word & (mask(reg_shift));
1779 }});
1780 }
2072 0x3: sw({{ Mem.uw = Rt<31:0>; }});
2073 }
2074
2075 format StoreUnalignedMemory {
2076 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
2077 uint32_t mem_shift = 32 - reg_shift;
2078 mem_word = mem_word & (mask(reg_shift) << mem_shift) |
2079 Rt.uw >> reg_shift;
2080 }});
2081 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
2082 mem_word = Rt.uw << reg_shift |
2083 mem_word & (mask(reg_shift));
2084 }});
2085 }
1781
1782 0x7: FailUnimpl::cache();
2086 format CP0Control {
2087 0x7: cache({{
2088 Addr CacheEA = Rs.uw + OFFSET;
2089 fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
2090 }});
2091 }
1783 }
1784
1785 0x6: decode OPCODE_LO {
1786 format LoadMemory {
1787 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
1788 0x1: lwc1({{ Ft.uw = Mem.uw; }});
1789 0x5: ldc1({{ Ft.ud = Mem.ud; }});
1790 }
2092 }
2093
2094 0x6: decode OPCODE_LO {
2095 format LoadMemory {
2096 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
2097 0x1: lwc1({{ Ft.uw = Mem.uw; }});
2098 0x5: ldc1({{ Ft.ud = Mem.ud; }});
2099 }
1791
2100 0x2: CP2Unimpl::lwc2();
2101 0x6: CP2Unimpl::ldc2();
1792 0x3: Prefetch::pref();
1793 }
1794
1795
1796 0x7: decode OPCODE_LO {
1797 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1798 {{ uint64_t tmp = write_result;
1799 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1800 }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
1801
1802 format StoreMemory {
2102 0x3: Prefetch::pref();
2103 }
2104
2105
2106 0x7: decode OPCODE_LO {
2107 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
2108 {{ uint64_t tmp = write_result;
2109 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
2110 }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
2111
2112 format StoreMemory {
1803 0x1: swc1({{ Mem.uw = Ft.uw; }});
1804 0x5: sdc1({{ Mem.ud = Ft.ud; }});
2113 0x1: swc1({{ Mem.uw = Ft.uw;}});
2114 0x5: sdc1({{ Mem.ud = Ft.ud;}});
1805 }
2115 }
2116
2117 0x2: CP2Unimpl::swc2();
2118 0x6: CP2Unimpl::sdc2();
2119
1806 }
1807}
1808
1809
2120 }
2121}
2122
2123