decoder.isa (4172:141705d83494) decoder.isa (4661:44458219add1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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30
31////////////////////////////////////////////////////////////////////
32//
33// The actual MIPS32 ISA decoder
34// -----------------------------
35// The following instructions are specified in the MIPS32 ISA
36// Specification. Decoding closely follows the style specified
37// in the MIPS32 ISA specification document starting with Table
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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30
31////////////////////////////////////////////////////////////////////
32//
33// The actual MIPS32 ISA decoder
34// -----------------------------
35// The following instructions are specified in the MIPS32 ISA
36// Specification. Decoding closely follows the style specified
37// in the MIPS32 ISA specification document starting with Table
38// A-2 (document available @ www.mips.com)
38// A-2 (document available @ http://www.mips.com)
39//
40decode OPCODE_HI default Unknown::unknown() {
41 //Table A-2
42 0x0: decode OPCODE_LO {
43 0x0: decode FUNCTION_HI {
44 0x0: decode FUNCTION_LO {
45 0x1: decode MOVCI {
46 format BasicOp {
47 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
48 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
49 }
50 }
51
52 format BasicOp {
53 //Table A-3 Note: "Specific encodings of the rd, rs, and
54 //rt fields are used to distinguish SLL, SSNOP, and EHB
55 //functions
56 0x0: decode RS {
57 0x0: decode RT_RD {
39//
40decode OPCODE_HI default Unknown::unknown() {
41 //Table A-2
42 0x0: decode OPCODE_LO {
43 0x0: decode FUNCTION_HI {
44 0x0: decode FUNCTION_LO {
45 0x1: decode MOVCI {
46 format BasicOp {
47 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
48 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
49 }
50 }
51
52 format BasicOp {
53 //Table A-3 Note: "Specific encodings of the rd, rs, and
54 //rt fields are used to distinguish SLL, SSNOP, and EHB
55 //functions
56 0x0: decode RS {
57 0x0: decode RT_RD {
58 0x0: decode SA default Nop::nop(){
58 0x0: decode SA default Nop::nop() {
59 0x1: WarnUnimpl::ssnop();
60 0x3: WarnUnimpl::ehb();
61 }
62 default: sll({{ Rd = Rt.uw << SA; }});
63 }
64 }
65
66 0x2: decode RS_SRL {

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118 //used to distinguish JR from JR.HB and JALR from JALR.HB"
119 format Jump {
120 0x0: decode HINT {
121 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
122 default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
123 }
124
125 0x1: decode HINT {
59 0x1: WarnUnimpl::ssnop();
60 0x3: WarnUnimpl::ehb();
61 }
62 default: sll({{ Rd = Rt.uw << SA; }});
63 }
64 }
65
66 0x2: decode RS_SRL {

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118 //used to distinguish JR from JR.HB and JALR from JALR.HB"
119 format Jump {
120 0x0: decode HINT {
121 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
122 default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
123 }
124
125 0x1: decode HINT {
126 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall, Link
126 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
127 , ClearHazards);
127 , ClearHazards);
128 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall,
129 Link);
128 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
130 }
131 }
132
133 format BasicOp {
134 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
135 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
136 0x4: syscall({{ xc->syscall(R2); }},
137 IsSerializeAfter, IsNonSpeculative);
138 0x7: sync({{ ; }}, IsMemBarrier);
139 }
140
141 format FailUnimpl {
142 0x5: break();
143 }
144 }
145
146 0x2: decode FUNCTION_LO {
129 }
130 }
131
132 format BasicOp {
133 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
134 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
135 0x4: syscall({{ xc->syscall(R2); }},
136 IsSerializeAfter, IsNonSpeculative);
137 0x7: sync({{ ; }}, IsMemBarrier);
138 }
139
140 format FailUnimpl {
141 0x5: break();
142 }
143 }
144
145 0x2: decode FUNCTION_LO {
147 format HiLoMiscOp {
148 0x0: mfhi({{ Rd = HI; }});
149 0x1: mthi({{ HI = Rs; }});
150 0x2: mflo({{ Rd = LO; }});
151 0x3: mtlo({{ LO = Rs; }});
152 }
146 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
147 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
148 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
149 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
153 }
154
155 0x3: decode FUNCTION_LO {
150 }
151
152 0x3: decode FUNCTION_LO {
153 format HiLoRdSelValOp {
154 0x0: mult({{ val = Rs.sd * Rt.sd; }});
155 0x1: multu({{ val = Rs.ud * Rt.ud; }});
156 }
157
156 format HiLoOp {
158 format HiLoOp {
157 0x0: mult({{ int64_t val = Rs.sd * Rt.sd; }});
158 0x1: multu({{ uint64_t val = Rs.ud * Rt.ud; }});
159 0x2: div({{ //Initialized to placate g++
160 int64_t val = 0;
161 if (Rt.sd != 0) {
162 int64_t hi = Rs.sd % Rt.sd;
163 int64_t lo = Rs.sd / Rt.sd;
164 val = (hi << 32) | lo;
165 }
166 }});
167 0x3: divu({{ //Initialized to placate g++
168 uint64_t val = 0;
169 if (Rt.ud != 0) {
170 uint64_t hi = Rs.ud % Rt.ud;
171 uint64_t lo = Rs.ud / Rt.ud;
172 val = (hi << 32) | lo;
173 }
174 }});
159 0x2: div({{ if (Rt.sd != 0) {
160 HI0 = Rs.sd % Rt.sd;
161 LO0 = Rs.sd / Rt.sd;
162 }
163 }});
164 0x3: divu({{ if (Rt.ud != 0) {
165 HI0 = Rs.ud % Rt.ud;
166 LO0 = Rs.ud / Rt.ud;
167 }
168 }});
175 }
176 }
177
178 0x4: decode HINT {
179 0x0: decode FUNCTION_LO {
180 format IntOp {
181 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
182 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});

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240 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
241 }
242 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
243 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
244 }
245 }
246
247 0x3: decode REGIMM_LO {
169 }
170 }
171
172 0x4: decode HINT {
173 0x0: decode FUNCTION_LO {
174 format IntOp {
175 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
176 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});

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234 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
235 }
236 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
237 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
238 }
239 }
240
241 0x3: decode REGIMM_LO {
242 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL)
243 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }});
248 format WarnUnimpl {
249 0x7: synci();
250 }
251 }
252 }
253
254 format Jump {
255 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});

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268 }
269 }
270
271 0x1: decode OPCODE_LO {
272 format IntImmOp {
273 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
274 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
275 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
244 format WarnUnimpl {
245 0x7: synci();
246 }
247 }
248 }
249
250 format Jump {
251 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});

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264 }
265 }
266
267 0x1: decode OPCODE_LO {
268 format IntImmOp {
269 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
270 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
271 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
276 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
272
273 //Edited to include MIPS AVP Pass/Fail instructions and
274 //default to the sltiu instruction
275 0x3: decode RS_RT_INTIMM {
276 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }});
277 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }});
278 default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
279 }
280
277 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
278 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
279 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
280
281 0x7: decode RS {
282 0x0: lui({{ Rt = imm << 16}});
283 }
284 }
285 }
286
287 0x2: decode OPCODE_LO {
288 //Table A-11 MIPS32 COP0 Encoding of rs Field
289 0x0: decode RS_MSB {
290 0x0: decode RS {
291 format CP0Control {
281 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
282 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
283 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
284
285 0x7: decode RS {
286 0x0: lui({{ Rt = imm << 16}});
287 }
288 }
289 }
290
291 0x2: decode OPCODE_LO {
292 //Table A-11 MIPS32 COP0 Encoding of rs Field
293 0x0: decode RS_MSB {
294 0x0: decode RS {
295 format CP0Control {
292 0x0: mfc0({{ Rt = xc->readMiscRegNoEffect(RD << 5 | SEL); }});
293 0x4: mtc0({{ xc->setMiscRegNoEffect(RD << 5 | SEL, Rt); }});
296 0x0: mfc0({{ Rt = CP0_RD_SEL; }});
297 0x4: mtc0({{ CP0_RD_SEL = Rt; }});
294 }
295
298 }
299
296 format MipsMT {
297 0x8: mftr();
298 0xC: mttr();
299 0xB: decode RD {
300 0x0: decode SC {
301 0x0: dvpe();
302 0x1: evpe();
300
301 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
302 0x8: decode MT_U {
303 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
304 Ctrl_Base_DepTag);
305 }});
306 0x1: decode SEL {
307 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
308 0x1: decode RT {
309 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }});
310 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }});
311 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }});
312 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }});
313 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }});
314 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
315 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
316 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
317 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
318 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
319 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
320 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
321 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
322 }
323 0x2: decode MT_H {
324 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
325 FP_Base_DepTag);
326 }});
327 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
328 FP_Base_DepTag);
329 }});
330 }
331 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
332 FP_Base_DepTag);
333 switch (RT)
334 {
335 case 0:
336 data = xc->readRegOtherThread(MipsISA::FIR +
337 Ctrl_Base_DepTag);
338 break;
339 case 25:
340 data = 0 | fcsr_val & 0xFE000000 >> 24
341 | fcsr_val & 0x00800000 >> 23;
342 break;
343 case 26:
344 data = 0 | fcsr_val & 0x0003F07C;
345 break;
346 case 28:
347 data = 0 | fcsr_val & 0x00000F80
348 | fcsr_val & 0x01000000 >> 21
349 | fcsr_val & 0x00000003;
350 break;
351 case 31:
352 data = fcsr_val;
353 break;
354 default:
355 fatal("FP Control Value (%d) Not Valid");
356 }
357 }});
303 }
358 }
304 0x1: decode SC {
305 0x0: dmt();
306 0x1: emt();
307 0xC: decode SC {
308 0x0: di();
309 0x1: ei();
359 }
360 }
361
362 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
363 0xC: decode MT_U {
364 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
365 Rt);
366 }});
367 0x1: decode SEL {
368 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
369 0x1: decode RT {
370 0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt);
371 }});
372 0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0,
373 Rt);
374 }});
375 0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0,
376 Rt);
377 }});
378 0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1,
379 Rt);
380 }});
381 0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1,
382 Rt);
383 }});
384 0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1,
385 Rt);
386 }});
387 0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2,
388 Rt);
389 }});
390 0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2,
391 Rt);
392 }});
393 0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2,
394 Rt);
395 }});
396 0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3,
397 Rt);
398 }});
399 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
400 Rt);
401 }});
402 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
403 }});
404 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
310 }
405 }
406 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
407 FP_Base_DepTag);
408 data = insertBits(data, top_bit, bottom_bit, Rt);
409 xc->setRegOtherThread(RD + FP_Base_DepTag, data);
410 }});
411 0x3: cttc1({{ uint32_t data;
412 switch (RD)
413 {
414 case 25:
415 data = 0 | (Rt.uw<7:1> << 25) // move 31...25
416 | (FCSR & 0x01000000) // bit 24
417 | (FCSR & 0x004FFFFF);// bit 22...0
418 break;
419
420 case 26:
421 data = 0 | (FCSR & 0xFFFC0000) // move 31...18
422 | Rt.uw<17:12> << 12 // bit 17...12
423 | (FCSR & 0x00000F80) << 7// bit 11...7
424 | Rt.uw<6:2> << 2 // bit 6...2
425 | (FCSR & 0x00000002); // bit 1...0
426 break;
427
428 case 28:
429 data = 0 | (FCSR & 0xFE000000) // move 31...25
430 | Rt.uw<2:2> << 24 // bit 24
431 | (FCSR & 0x00FFF000) << 23// bit 23...12
432 | Rt.uw<11:7> << 7 // bit 24
433 | (FCSR & 0x000007E)
434 | Rt.uw<1:0>;// bit 22...0
435 break;
436
437 case 31:
438 data = Rt.uw;
439 break;
440
441 default:
442 panic("FP Control Value (%d) Not Available. Ignoring Access to"
443 "Floating Control Status Register", FS);
444 }
445 xc->setRegOtherThread(FCSR, data);
446 }});
311 }
312 }
313 }
314
447 }
448 }
449 }
450
315 format FailUnimpl {
316 0xA: rdpgpr();
317 0xE: wrpgpr();
451
452 0xB: decode RD {
453 format MT_Control {
454 0x0: decode POS {
455 0x0: decode SEL {
456 0x1: decode SC {
457 0x0: dvpe({{ Rt = MVPControl;
458 if (VPEConf0<VPEC0_MVP:> == 1) {
459 MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
460 }
461 }});
462 0x1: evpe({{ Rt = MVPControl;
463 if (VPEConf0<VPEC0_MVP:> == 1) {
464 MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
465 }
466 }});
467 }
468 }
469 }
470
471 0x1: decode POS {
472 0xF: decode SEL {
473 0x1: decode SC {
474 0x0: dmt({{ Rt = VPEControl;
475 VPEControl = insertBits(VPEControl, VPEC_TE, 0);
476 }});
477 0x1: emt({{ Rt = VPEControl;
478 VPEControl = insertBits(VPEControl, VPEC_TE, 1);
479 }});
480
481 }
482 }
483 }
484 }
485 0xC: decode POS {
486 0x0: decode SC {
487 0x0: CP0Control::di({{
488 if(Config_AR >= 1) // Rev 2.0 or beyond?
489 {
490 Rt = Status;
491 Status_IE = 0;
492 }
493 else // Enable this else branch once we actually set values for Config on init
494 {
495 fault = new ReservedInstructionFault();
496 }
497 }});
498 0x1: CP0Control::ei({{
499 if(Config_AR >= 1)
500 {
501 Rt = Status;
502 Status_IE = 1;
503 }
504 else
505 {
506 fault = new ReservedInstructionFault();
507 }
508 }});
509 }
510 }
318 }
511 }
512
513 format CP0Control {
514 0xA: rdpgpr({{
515 if(Config_AR >= 1)
516 { // Rev 2 of the architecture
517 Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
518 }
519 else
520 {
521 fault = new ReservedInstructionFault();
522 }
523 }});
524 0xE: wrpgpr({{
525 if(Config_AR >= 1)
526 { // Rev 2 of the architecture
527 xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
528 }
529 else
530 {
531 fault = new ReservedInstructionFault();
532 }
533
534 }});
535
536 }
537
319 }
320
321 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
322 0x1: decode FUNCTION {
538 }
539
540 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
541 0x1: decode FUNCTION {
323 format FailUnimpl {
324 0x01: tlbr();
325 0x02: tlbwi();
326 0x06: tlbwr();
327 0x08: tlbp();
542 format CP0Control {
543 0x18: eret({{
544 if(Status_ERL == 1){
545 Status_ERL = 0;
546 NPC = ErrorEPC;
547 }
548 else{
549 NPC = EPC;
550 Status_EXL = 0;
551 if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
552 SRSCtl_CSS = SRSCtl_PSS;
553 }
554 }
555 // LLFlag = 0;
556 // ClearHazards(); ?
557 }});
328
558
329 0x18: eret();
330 0x1F: deret();
559 0x1F: deret({{
560 // if(EJTagImplemented()) {
561 if(Debug_DM == 1){
562 Debug_DM = 1;
563 Debug_IEXI = 0;
564 NPC = DEPC;
565 }
566 else
567 {
568 // Undefined;
569 }
570 //} // EJTag Implemented
571 //else {
572 // Reserved Instruction Exception
573 //}
574 }});
575 }
576
577 format FailUnimpl {
578 0x01: tlbr(); // Need to hook up to TLB
579 0x02: tlbwi(); // Need to hook up to TLB
580 0x06: tlbwr();// Need to hook up to TLB
581 0x08: tlbp();// Need to hook up to TLB
582
331 0x20: wait();
332 }
583 0x20: wait();
584 }
585
333 }
334 }
335
336 //Table A-13 MIPS32 COP1 Encoding of rs Field
337 0x1: decode RS_MSB {
338
339 0x0: decode RS_HI {
340 0x0: decode RS_LO {

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944 }
945 }
946
947 0x3: decode OPCODE_LO {
948 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
949 0x4: decode FUNCTION_HI {
950 0x0: decode FUNCTION_LO {
951 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
586 }
587 }
588
589 //Table A-13 MIPS32 COP1 Encoding of rs Field
590 0x1: decode RS_MSB {
591
592 0x0: decode RS_HI {
593 0x0: decode RS_LO {

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1197 }
1198 }
1199
1200 0x3: decode OPCODE_LO {
1201 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1202 0x4: decode FUNCTION_HI {
1203 0x0: decode FUNCTION_LO {
1204 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
952 Rd.sw = temp1<31:0>
1205 Rd.sw = temp1<31:0>;
953 }});
954
1206 }});
1207
955 format HiLoOp {
956 0x0: madd({{ int64_t val = ((int64_t) HI << 32 | LO) +
957 (Rs.sd * Rt.sd);
958 }});
959 0x1: maddu({{ uint64_t val = ((uint64_t) HI << 32 | LO) +
960 (Rs.ud * Rt.ud);
961 }});
962 0x4: msub({{ int64_t val = ((int64_t) HI << 32 | LO) -
963 (Rs.sd * Rt.sd);
964 }});
965 0x5: msubu({{ uint64_t val = ((uint64_t) HI << 32 | LO) -
966 (Rs.ud * Rt.ud);
967 }});
1208 format HiLoRdSelValOp {
1209 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
1210 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
1211 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
1212 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
968 }
969 }
970
971 0x4: decode FUNCTION_LO {
972 format BasicOp {
973 0x0: clz({{ int cnt = 32;
1213 }
1214 }
1215
1216 0x4: decode FUNCTION_LO {
1217 format BasicOp {
1218 0x0: clz({{ int cnt = 32;
974 for (int idx = 31; idx >= 0; idx--) {
975 if( Rs<idx:idx> == 1) {
976 cnt = 31 - idx;
977 break;
978 }
979 }
980 Rd.uw = cnt;
981 }});
1219 for (int idx = 31; idx >= 0; idx--) {
1220 if( Rs == 1) {
1221 cnt = 31 - idx;
1222 break;
1223 }
1224 }
1225 Rd.uw = cnt;
1226 }});
982 0x1: clo({{ int cnt = 32;
1227 0x1: clo({{ int cnt = 32;
983 for (int idx = 31; idx >= 0; idx--) {
984 if( Rs<idx:idx> == 0) {
985 cnt = 31 - idx;
986 break;
987 }
988 }
989 Rd.uw = cnt;
990 }});
1228 for (int idx = 31; idx >= 0; idx--) {
1229 if( Rs == 0) {
1230 cnt = 31 - idx;
1231 break;
1232 }
1233 }
1234 Rd.uw = cnt;
1235 }});
991 }
992 }
993
994 0x7: decode FUNCTION_LO {
995 0x7: FailUnimpl::sdbbp();
996 }
997 }
998

--- 6 unchanged lines hidden (view full) ---

1005 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
1006 bits(Rs.uw, MSB-LSB, 0) << LSB |
1007 bits(Rt.uw, LSB-1, 0);
1008 }});
1009 }
1010 }
1011
1012 0x1: decode FUNCTION_LO {
1236 }
1237 }
1238
1239 0x7: decode FUNCTION_LO {
1240 0x7: FailUnimpl::sdbbp();
1241 }
1242 }
1243

--- 6 unchanged lines hidden (view full) ---

1250 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
1251 bits(Rs.uw, MSB-LSB, 0) << LSB |
1252 bits(Rt.uw, LSB-1, 0);
1253 }});
1254 }
1255 }
1256
1257 0x1: decode FUNCTION_LO {
1013 format MipsMT {
1014 0x0: fork();
1015 0x1: yield();
1258 format MT_Control {
1259 0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }},
1260 UserMode);
1261 0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }},
1262 UserMode);
1016 }
1263 }
1264
1265 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL)
1266 0x2: decode OP_HI {
1267 0x0: decode OP_LO {
1268 format LoadIndexedMemory {
1269 0x0: lwx({{ Rd.sw = Mem.sw; }});
1270 0x4: lhx({{ Rd.sw = Mem.sh; }});
1271 0x6: lbux({{ Rd.uw = Mem.ub; }});
1272 }
1273 }
1274 }
1275 0x4: DspIntOp::insv({{ int pos = dspctl<5:0>;
1276 int size = dspctl<12:7>-1;
1277 Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }});
1017 }
1018
1278 }
1279
1280 0x2: decode FUNCTION_LO {
1281
1282 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL)
1283 0x0: decode OP_HI {
1284 0x0: decode OP_LO {
1285 format DspIntOp {
1286 0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1287 NOSATURATE, UNSIGNED, &dspctl ); }});
1288 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1289 NOSATURATE, UNSIGNED, &dspctl ); }});
1290 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1291 SATURATE, UNSIGNED, &dspctl ); }});
1292 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1293 SATURATE, UNSIGNED, &dspctl ); }});
1294 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1295 MODE_L, &dspctl ); }});
1296 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1297 MODE_R, &dspctl ); }});
1298 }
1299 }
1300 0x1: decode OP_LO {
1301 format DspIntOp {
1302 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1303 NOSATURATE, UNSIGNED, &dspctl ); }});
1304 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1305 NOSATURATE, UNSIGNED, &dspctl ); }});
1306 0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1307 NOSATURATE, SIGNED, &dspctl ); }});
1308 0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1309 NOSATURATE, SIGNED, &dspctl ); }});
1310 0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1311 SATURATE, UNSIGNED, &dspctl ); }});
1312 0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1313 SATURATE, UNSIGNED, &dspctl ); }});
1314 0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1315 SATURATE, SIGNED, &dspctl ); }});
1316 0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1317 SATURATE, SIGNED, &dspctl ); }});
1318 }
1319 }
1320 0x2: decode OP_LO {
1321 format DspIntOp {
1322 0x0: addsc({{ int64_t dresult;
1323 dresult = Rs.ud + Rt.ud;
1324 Rd.sw = dresult<31:0>;
1325 dspctl = insertBits( dspctl, 13, 13,
1326 dresult<32:32> ); }});
1327 0x1: addwc({{ int64_t dresult;
1328 dresult = Rs.sd + Rt.sd + dspctl<13:13>;
1329 Rd.sw = dresult<31:0>;
1330 if( dresult<32:32> != dresult<31:31> )
1331 dspctl = insertBits( dspctl, 20, 20, 1 ); }});
1332 0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }});
1333 0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> +
1334 Rs.uw<15:8> + Rs.uw<7:0>; }});
1335 0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W,
1336 SATURATE, SIGNED, &dspctl ); }});
1337 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W,
1338 SATURATE, SIGNED, &dspctl ); }});
1339 }
1340 }
1341 0x3: decode OP_LO {
1342 format DspIntOp {
1343 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1344 MODE_L, &dspctl ); }});
1345 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1346 MODE_R, &dspctl ); }});
1347 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1348 SATURATE, NOROUND, &dspctl ); }});
1349 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1350 SATURATE, ROUND, &dspctl ); }});
1351 }
1352 }
1353 }
1354
1355 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL)
1356 0x1: decode OP_HI {
1357 0x0: decode OP_LO {
1358 format DspIntOp {
1359 0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1360 UNSIGNED, CMP_EQ, &dspctl ); }});
1361 0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1362 UNSIGNED, CMP_LT, &dspctl ); }});
1363 0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1364 UNSIGNED, CMP_LE, &dspctl ); }});
1365 0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw,
1366 SIMD_FMT_QB, &dspctl ); }});
1367 0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1368 UNSIGNED, CMP_EQ ); }});
1369 0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1370 UNSIGNED, CMP_LT ); }});
1371 0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1372 UNSIGNED, CMP_LE ); }});
1373 }
1374 }
1375 0x1: decode OP_LO {
1376 format DspIntOp {
1377 0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1378 SIGNED, CMP_EQ, &dspctl ); }});
1379 0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1380 SIGNED, CMP_LT, &dspctl ); }});
1381 0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1382 SIGNED, CMP_LE, &dspctl ); }});
1383 0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw,
1384 SIMD_FMT_PH, &dspctl ); }});
1385 0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 |
1386 Rs.uw<15:8> << 16 |
1387 Rt.uw<31:24> << 8 |
1388 Rt.uw<15:8>; }});
1389 0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 |
1390 Rs.uw<7:0> << 16 |
1391 Rt.uw<23:16> << 8 |
1392 Rt.uw<7:0>; }});
1393 0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw,
1394 SIMD_FMT_PH ); }});
1395 0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }});
1396 }
1397 }
1398 0x2: decode OP_LO {
1399 format DspIntOp {
1400 0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }});
1401 0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }});
1402 }
1403 }
1404 0x3: decode OP_LO {
1405 format DspIntOp {
1406 0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1407 UNSIGNED, CMP_EQ, &dspctl ); }});
1408 0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1409 UNSIGNED, CMP_LT, &dspctl ); }});
1410 0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1411 UNSIGNED, CMP_LE, &dspctl ); }});
1412 0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD,
1413 SIMD_FMT_W, NOROUND ); }});
1414 0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD,
1415 SIMD_FMT_W, ROUND ); }});
1416 }
1417 }
1418 }
1419
1420 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL)
1421 0x2: decode OP_HI {
1422 0x0: decode OP_LO {
1423 format DspIntOp {
1424 0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}});
1425 0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 |
1426 RS_RT<7:0> << 16 |
1427 RS_RT<7:0> << 8 |
1428 RS_RT<7:0>; }});
1429 0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 |
1430 Rt.uw<7:0> << 16 |
1431 Rt.uw<7:0> << 8 |
1432 Rt.uw<7:0>; }});
1433 0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1434 SIMD_FMT_PH, SIGNED, MODE_L ); }});
1435 0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1436 SIMD_FMT_PH, SIGNED, MODE_R ); }});
1437 0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1438 SIMD_FMT_PH, SIGNED, MODE_LA ); }});
1439 0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1440 SIMD_FMT_PH, SIGNED, MODE_RA ); }});
1441 }
1442 }
1443 0x1: decode OP_LO {
1444 format DspIntOp {
1445 0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }});
1446 0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 |
1447 (sext<10>(RS_RT))<15:0>; }});
1448 0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 |
1449 Rt.uw<15:0>; }});
1450 0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED,
1451 SIMD_FMT_W, SIGNED, MODE_L ); }});
1452 0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED,
1453 SIMD_FMT_W, SIGNED, MODE_R ); }});
1454 }
1455 }
1456 0x2: decode OP_LO {
1457 format DspIntOp {
1458 0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }});
1459 }
1460 }
1461 0x3: decode OP_LO {
1462 0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }});
1463 format DspIntOp {
1464 0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1465 SIMD_FMT_PH, UNSIGNED, MODE_L ); }});
1466 0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1467 SIMD_FMT_PH, UNSIGNED, MODE_R ); }});
1468 0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1469 SIMD_FMT_PH, UNSIGNED, MODE_LA ); }});
1470 0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1471 SIMD_FMT_PH, UNSIGNED, MODE_RA ); }});
1472 }
1473 }
1474 }
1475
1476 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL)
1477 0x3: decode OP_HI {
1478 0x0: decode OP_LO {
1479 format DspIntOp {
1480 0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB,
1481 NOSATURATE, UNSIGNED, &dspctl ); }});
1482 0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB,
1483 UNSIGNED ); }});
1484 0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB,
1485 NOSATURATE, UNSIGNED, &dspctl ); }});
1486 0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB,
1487 UNSIGNED ); }});
1488 0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB,
1489 NOROUND, SIGNED, &dspctl ); }});
1490 0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB,
1491 ROUND, SIGNED, &dspctl ); }});
1492 0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB,
1493 NOROUND, SIGNED, &dspctl ); }});
1494 0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB,
1495 ROUND, SIGNED, &dspctl ); }});
1496 }
1497 }
1498 0x1: decode OP_LO {
1499 format DspIntOp {
1500 0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH,
1501 NOSATURATE, SIGNED, &dspctl ); }});
1502 0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH,
1503 NOROUND, SIGNED, &dspctl ); }});
1504 0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH,
1505 NOSATURATE, SIGNED, &dspctl ); }});
1506 0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH,
1507 NOROUND, SIGNED, &dspctl ); }});
1508 0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH,
1509 SATURATE, SIGNED, &dspctl ); }});
1510 0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH,
1511 ROUND, SIGNED, &dspctl ); }});
1512 0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH,
1513 SATURATE, SIGNED, &dspctl ); }});
1514 0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH,
1515 ROUND, SIGNED, &dspctl ); }});
1516 }
1517 }
1518 0x2: decode OP_LO {
1519 format DspIntOp {
1520 0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W,
1521 SATURATE, SIGNED, &dspctl ); }});
1522 0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W,
1523 ROUND, SIGNED, &dspctl ); }});
1524 0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W,
1525 SATURATE, SIGNED, &dspctl ); }});
1526 0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W,
1527 ROUND, SIGNED, &dspctl ); }});
1528 }
1529 }
1530 0x3: decode OP_LO {
1531 format DspIntOp {
1532 0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH,
1533 UNSIGNED ); }});
1534 0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH,
1535 UNSIGNED ); }});
1536 }
1537 }
1538 }
1539 }
1540
1541 0x3: decode FUNCTION_LO {
1542
1543 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual)
1544 0x0: decode OP_HI {
1545 0x0: decode OP_LO {
1546 format DspIntOp {
1547 0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1548 NOROUND, UNSIGNED ); }});
1549 0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1550 NOROUND, UNSIGNED ); }});
1551 0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1552 ROUND, UNSIGNED ); }});
1553 0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1554 ROUND, UNSIGNED ); }});
1555 }
1556 }
1557 0x1: decode OP_LO {
1558 format DspIntOp {
1559 0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1560 NOROUND, SIGNED ); }});
1561 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1562 NOROUND, SIGNED ); }});
1563 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1564 ROUND, SIGNED ); }});
1565 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1566 ROUND, SIGNED ); }});
1567 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1568 NOSATURATE, &dspctl ); }});
1569 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1570 SATURATE, &dspctl ); }});
1571 }
1572 }
1573 0x2: decode OP_LO {
1574 format DspIntOp {
1575 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1576 NOROUND, SIGNED ); }});
1577 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1578 NOROUND, SIGNED ); }});
1579 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1580 ROUND, SIGNED ); }});
1581 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1582 ROUND, SIGNED ); }});
1583 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1584 SATURATE, NOROUND, &dspctl ); }});
1585 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1586 SATURATE, ROUND, &dspctl ); }});
1587 }
1588 }
1589 }
1590 }
1591
1019 //Table A-10 MIPS32 BSHFL Encoding of sa Field
1020 0x4: decode SA {
1021 format BasicOp {
1022 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 |
1592 //Table A-10 MIPS32 BSHFL Encoding of sa Field
1593 0x4: decode SA {
1594 format BasicOp {
1595 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 |
1023 Rt.uw<31:24> << 16 |
1024 Rt.uw<7:0> << 8 |
1025 Rt.uw<15:8>;
1596 Rt.uw<31:24> << 16 |
1597 Rt.uw<7:0> << 8 |
1598 Rt.uw<15:8>;
1026 }});
1027 0x10: seb({{ Rd.sw = Rt.sb; }});
1028 0x18: seh({{ Rd.sw = Rt.sh; }});
1029 }
1030 }
1031
1032 0x6: decode FUNCTION_LO {
1599 }});
1600 0x10: seb({{ Rd.sw = Rt.sb; }});
1601 0x18: seh({{ Rd.sw = Rt.sh; }});
1602 }
1603 }
1604
1605 0x6: decode FUNCTION_LO {
1606
1607 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL)
1608 0x0: decode OP_HI {
1609 0x0: decode OP_LO {
1610 format DspHiLoOp {
1611 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1612 SIMD_FMT_PH, SIGNED, MODE_L ); }});
1613 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1614 SIMD_FMT_PH, SIGNED, MODE_L ); }});
1615 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw,
1616 ACDST, SIMD_FMT_PH ); }});
1617 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1618 SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1619 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1620 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1621 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1622 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1623 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw,
1624 ACDST, SIMD_FMT_PH, &dspctl ); }});
1625 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1626 SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1627 }
1628 }
1629 0x1: decode OP_LO {
1630 format DspHiLoOp {
1631 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1632 SIMD_FMT_PH, SIGNED, MODE_X ); }});
1633 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1634 SIMD_FMT_PH, SIGNED, MODE_X ); }});
1635 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1636 SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1637 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1638 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1639 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1640 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1641 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1642 SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1643 }
1644 }
1645 0x2: decode OP_LO {
1646 format DspHiLoOp {
1647 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1648 MODE_L, SATURATE, &dspctl ); }});
1649 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1650 MODE_R, SATURATE, &dspctl ); }});
1651 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1652 MODE_L, NOSATURATE, &dspctl ); }});
1653 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1654 MODE_R, NOSATURATE, &dspctl ); }});
1655 }
1656 }
1657 0x3: decode OP_LO {
1658 format DspHiLoOp {
1659 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1660 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1661 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1662 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1663 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1664 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1665 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1666 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1667 }
1668 }
1669 }
1670
1671 //Table 3.3 MIPS32 APPEND Encoding of the op Field
1672 0x1: decode OP_HI {
1673 0x0: decode OP_LO {
1674 format IntOp {
1675 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
1676 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
1677 }
1678 }
1679 0x2: decode OP_LO {
1680 format IntOp {
1681 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }});
1682 }
1683 }
1684 }
1685
1033 0x7: FailUnimpl::rdhwr();
1034 }
1686 0x7: FailUnimpl::rdhwr();
1687 }
1688
1689 0x7: decode FUNCTION_LO {
1690
1691 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL)
1692 0x0: decode OP_HI {
1693 0x0: decode OP_LO {
1694 format DspHiLoOp {
1695 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1696 NOROUND, NOSATURATE, &dspctl ); }});
1697 0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1698 NOROUND, NOSATURATE, &dspctl ); }});
1699 0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }});
1700 0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }});
1701 0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1702 ROUND, NOSATURATE, &dspctl ); }});
1703 0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1704 ROUND, NOSATURATE, &dspctl ); }});
1705 0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1706 ROUND, SATURATE, &dspctl ); }});
1707 0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1708 ROUND, SATURATE, &dspctl ); }});
1709 }
1710 }
1711 0x1: decode OP_LO {
1712 format DspHiLoOp {
1713 0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }});
1714 0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }});
1715 0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS,
1716 NOROUND, SATURATE, &dspctl ); }});
1717 0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw,
1718 NOROUND, SATURATE, &dspctl ); }});
1719 }
1720 }
1721 0x2: decode OP_LO {
1722 format DspIntOp {
1723 0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }});
1724 0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }});
1725 }
1726 }
1727 0x3: decode OP_LO {
1728 format DspHiLoOp {
1729 0x2: shilo({{ if( sext<6>(HILOSA) < 0 )
1730 dspac = (uint64_t)dspac << -sext<6>(HILOSA);
1731 else
1732 dspac = (uint64_t)dspac >> sext<6>(HILOSA); }});
1733 0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 )
1734 dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>);
1735 else
1736 dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }});
1737 0x7: mthlip({{ dspac = dspac << 32;
1738 dspac |= Rs.uw;
1739 dspctl = insertBits( dspctl, 5, 0,
1740 dspctl<5:0>+32 ); }});
1741 }
1742 }
1743 }
1744 }
1035 }
1036 }
1037
1038 0x4: decode OPCODE_LO {
1039 format LoadMemory {
1040 0x0: lb({{ Rt.sw = Mem.sb; }});
1041 0x1: lh({{ Rt.sw = Mem.sh; }});
1042 0x3: lw({{ Rt.sw = Mem.sw; }});
1043 0x4: lbu({{ Rt.uw = Mem.ub; }});
1044 0x5: lhu({{ Rt.uw = Mem.uh; }});
1045 }
1046
1047 format LoadUnalignedMemory {
1048 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1049 Rt.uw = mem_word << mem_shift |
1745 }
1746 }
1747
1748 0x4: decode OPCODE_LO {
1749 format LoadMemory {
1750 0x0: lb({{ Rt.sw = Mem.sb; }});
1751 0x1: lh({{ Rt.sw = Mem.sh; }});
1752 0x3: lw({{ Rt.sw = Mem.sw; }});
1753 0x4: lbu({{ Rt.uw = Mem.ub; }});
1754 0x5: lhu({{ Rt.uw = Mem.uh; }});
1755 }
1756
1757 format LoadUnalignedMemory {
1758 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1759 Rt.uw = mem_word << mem_shift |
1050 Rt.uw & mask(mem_shift);
1760 Rt.uw & mask(mem_shift);
1051 }});
1052 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1053 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1761 }});
1762 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1763 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1054 mem_word >> mem_shift;
1764 mem_word >> mem_shift;
1055 }});
1765 }});
1056 }
1766 }
1057 }
1058
1059 0x5: decode OPCODE_LO {
1060 format StoreMemory {
1061 0x0: sb({{ Mem.ub = Rt<7:0>; }});
1062 0x1: sh({{ Mem.uh = Rt<15:0>; }});
1063 0x3: sw({{ Mem.uw = Rt<31:0>; }});
1064 }

--- 23 unchanged lines hidden (view full) ---

1088 0x3: Prefetch::pref();
1089 }
1090
1091
1092 0x7: decode OPCODE_LO {
1093 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1094 {{ uint64_t tmp = write_result;
1095 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1767 }
1768
1769 0x5: decode OPCODE_LO {
1770 format StoreMemory {
1771 0x0: sb({{ Mem.ub = Rt<7:0>; }});
1772 0x1: sh({{ Mem.uh = Rt<15:0>; }});
1773 0x3: sw({{ Mem.uw = Rt<31:0>; }});
1774 }

--- 23 unchanged lines hidden (view full) ---

1798 0x3: Prefetch::pref();
1799 }
1800
1801
1802 0x7: decode OPCODE_LO {
1803 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1804 {{ uint64_t tmp = write_result;
1805 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1096 if (tmp == 1) {
1097 xc->setStCondFailures(0);
1098 }
1099 }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
1100
1101 format StoreMemory {
1102 0x1: swc1({{ Mem.uw = Ft.uw; }});
1103 0x5: sdc1({{ Mem.ud = Ft.ud; }});
1104 }
1105 }
1106}
1107
1108
1806 }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
1807
1808 format StoreMemory {
1809 0x1: swc1({{ Mem.uw = Ft.uw; }});
1810 0x5: sdc1({{ Mem.ud = Ft.ud; }});
1811 }
1812 }
1813}
1814
1815