decoder.isa (12406:86bde4a026b5) decoder.isa (13389:ea6cf3af3c72)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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60 //rt fields are used to distinguish SLL, SSNOP, and EHB
61 //functions
62 0x0: decode RS {
63 0x0: decode RT_RD {
64 0x0: decode SA default Nop::nop() {
65 0x1: ssnop({{;}});
66 0x3: ehb({{;}});
67 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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60 //rt fields are used to distinguish SLL, SSNOP, and EHB
61 //functions
62 0x0: decode RS {
63 0x0: decode RT_RD {
64 0x0: decode SA default Nop::nop() {
65 0x1: ssnop({{;}});
66 0x3: ehb({{;}});
67 }
68 default: sll({{ Rd = Rt_uw << SA; }});
68 default: sll({{ Rd = Rt << SA; }});
69 }
70 }
71
72 0x2: decode RS_SRL {
73 0x0:decode SRL {
69 }
70 }
71
72 0x2: decode RS_SRL {
73 0x0:decode SRL {
74 0: srl({{ Rd = Rt_uw >> SA; }});
74 0: srl({{ Rd = Rt >> SA; }});
75
76 //Hardcoded assuming 32-bit ISA,
77 //probably need parameter here
78 1: rotr({{
75
76 //Hardcoded assuming 32-bit ISA,
77 //probably need parameter here
78 1: rotr({{
79 Rd = (Rt_uw << (32 - SA)) | (Rt_uw >> SA);
79 Rd = (Rt << (32 - SA)) | (Rt >> SA);
80 }});
81 }
82 }
83
84 0x3: decode RS {
85 0x0: sra({{
86 uint32_t temp = Rt >> SA;
87 if ( (Rt & 0x80000000) > 0 ) {
88 uint32_t mask = 0x80000000;
89 for(int i=0; i < SA; i++) {
90 temp |= mask;
91 mask = mask >> 1;
92 }
93 }
94 Rd = temp;
95 }});
96 }
97
80 }});
81 }
82 }
83
84 0x3: decode RS {
85 0x0: sra({{
86 uint32_t temp = Rt >> SA;
87 if ( (Rt & 0x80000000) > 0 ) {
88 uint32_t mask = 0x80000000;
89 for(int i=0; i < SA; i++) {
90 temp |= mask;
91 mask = mask >> 1;
92 }
93 }
94 Rd = temp;
95 }});
96 }
97
98 0x4: sllv({{ Rd = Rt_uw << Rs<4:0>; }});
98 0x4: sllv({{ Rd = Rt << Rs<4:0>; }});
99
100 0x6: decode SRLV {
99
100 0x6: decode SRLV {
101 0: srlv({{ Rd = Rt_uw >> Rs<4:0>; }});
101 0: srlv({{ Rd = Rt >> Rs<4:0>; }});
102
103 //Hardcoded assuming 32-bit ISA,
104 //probably need parameter here
105 1: rotrv({{
102
103 //Hardcoded assuming 32-bit ISA,
104 //probably need parameter here
105 1: rotrv({{
106 Rd = (Rt_uw << (32 - Rs<4:0>)) |
107 (Rt_uw >> Rs<4:0>);
106 Rd = (Rt << (32 - Rs<4:0>)) | (Rt >> Rs<4:0>);
108 }});
109 }
110
111 0x7: srav({{
112 int shift_amt = Rs<4:0>;
113
114 uint32_t temp = Rt >> shift_amt;
115

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205 }}, IntDivOp);
206 }
207 }
208
209 0x4: decode HINT {
210 0x0: decode FUNCTION_LO {
211 format IntOp {
212 0x0: add({{
107 }});
108 }
109
110 0x7: srav({{
111 int shift_amt = Rs<4:0>;
112
113 uint32_t temp = Rt >> shift_amt;
114

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204 }}, IntDivOp);
205 }
206 }
207
208 0x4: decode HINT {
209 0x0: decode FUNCTION_LO {
210 format IntOp {
211 0x0: add({{
213 IntReg result;
212 uint32_t result;
214 Rd = result = Rs + Rt;
215 if (FullSystem &&
216 findOverflow(32, result, Rs, Rt)) {
217 fault = std::make_shared<IntegerOverflowFault>();
218 }
219 }});
213 Rd = result = Rs + Rt;
214 if (FullSystem &&
215 findOverflow(32, result, Rs, Rt)) {
216 fault = std::make_shared<IntegerOverflowFault>();
217 }
218 }});
220 0x1: addu({{ Rd_sw = Rs_sw + Rt_sw;}});
219 0x1: addu({{ Rd = Rs_sw + Rt_sw;}});
221 0x2: sub({{
220 0x2: sub({{
222 IntReg result;
221 uint32_t result;
223 Rd = result = Rs - Rt;
224 if (FullSystem &&
225 findOverflow(32, result, Rs, ~Rt)) {
226 fault = std::make_shared<IntegerOverflowFault>();
227 }
228 }});
222 Rd = result = Rs - Rt;
223 if (FullSystem &&
224 findOverflow(32, result, Rs, ~Rt)) {
225 fault = std::make_shared<IntegerOverflowFault>();
226 }
227 }});
229 0x3: subu({{ Rd_sw = Rs_sw - Rt_sw; }});
228 0x3: subu({{ Rd = Rs_sw - Rt_sw; }});
230 0x4: and({{ Rd = Rs & Rt; }});
231 0x5: or({{ Rd = Rs | Rt; }});
232 0x6: xor({{ Rd = Rs ^ Rt; }});
233 0x7: nor({{ Rd = ~(Rs | Rt); }});
234 }
235 }
236 }
237
238 0x5: decode HINT {
239 0x0: decode FUNCTION_LO {
240 format IntOp{
229 0x4: and({{ Rd = Rs & Rt; }});
230 0x5: or({{ Rd = Rs | Rt; }});
231 0x6: xor({{ Rd = Rs ^ Rt; }});
232 0x7: nor({{ Rd = ~(Rs | Rt); }});
233 }
234 }
235 }
236
237 0x5: decode HINT {
238 0x0: decode FUNCTION_LO {
239 format IntOp{
241 0x2: slt({{ Rd_sw = (Rs_sw < Rt_sw) ? 1 : 0 }});
242 0x3: sltu({{ Rd_uw = (Rs_uw < Rt_uw) ? 1 : 0 }});
240 0x2: slt({{ Rd = (Rs_sw < Rt_sw) ? 1 : 0 }});
241 0x3: sltu({{ Rd = (Rs < Rt) ? 1 : 0 }});
243 }
244 }
245 }
246
247 0x6: decode FUNCTION_LO {
248 format Trap {
242 }
243 }
244 }
245
246 0x6: decode FUNCTION_LO {
247 format Trap {
249 0x0: tge({{ cond = (Rs_sw >= Rt_sw); }});
250 0x1: tgeu({{ cond = (Rs_uw >= Rt_uw); }});
248 0x0: tge({{ cond = (Rs_sw >= Rt_sw); }});
249 0x1: tgeu({{ cond = (Rs >= Rt); }});
251 0x2: tlt({{ cond = (Rs_sw < Rt_sw); }});
250 0x2: tlt({{ cond = (Rs_sw < Rt_sw); }});
252 0x3: tltu({{ cond = (Rs_uw < Rt_uw); }});
251 0x3: tltu({{ cond = (Rs < Rt); }});
253 0x4: teq({{ cond = (Rs_sw == Rt_sw); }});
254 0x6: tne({{ cond = (Rs_sw != Rt_sw); }});
255 }
256 }
257 }
258
259 0x1: decode REGIMM_HI {
260 0x0: decode REGIMM_LO {

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265 0x3: bgezl({{ cond = (Rs_sw >= 0); }}, Likely);
266 }
267 }
268
269 0x1: decode REGIMM_LO {
270 format TrapImm {
271 0x0: tgei( {{ cond = (Rs_sw >= (int16_t)INTIMM); }});
272 0x1: tgeiu({{
252 0x4: teq({{ cond = (Rs_sw == Rt_sw); }});
253 0x6: tne({{ cond = (Rs_sw != Rt_sw); }});
254 }
255 }
256 }
257
258 0x1: decode REGIMM_HI {
259 0x0: decode REGIMM_LO {

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264 0x3: bgezl({{ cond = (Rs_sw >= 0); }}, Likely);
265 }
266 }
267
268 0x1: decode REGIMM_LO {
269 format TrapImm {
270 0x0: tgei( {{ cond = (Rs_sw >= (int16_t)INTIMM); }});
271 0x1: tgeiu({{
273 cond = (Rs_uw >= (uint32_t)(int32_t)(int16_t)INTIMM);
272 cond = (Rs >= (uint32_t)(int32_t)(int16_t)INTIMM);
274 }});
275 0x2: tlti( {{ cond = (Rs_sw < (int16_t)INTIMM); }});
276 0x3: tltiu({{
273 }});
274 0x2: tlti( {{ cond = (Rs_sw < (int16_t)INTIMM); }});
275 0x3: tltiu({{
277 cond = (Rs_uw < (uint32_t)(int32_t)(int16_t)INTIMM);
276 cond = (Rs < (uint32_t)(int32_t)(int16_t)INTIMM);
278 }});
279 0x4: teqi( {{ cond = (Rs_sw == (int16_t)INTIMM); }});
280 0x6: tnei( {{ cond = (Rs_sw != (int16_t)INTIMM); }});
281 }
282 }
283
284 0x2: decode REGIMM_LO {
285 format Branch {

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318 0x6: blez({{ cond = (Rs_sw <= 0); }});
319 0x7: bgtz({{ cond = (Rs_sw > 0); }});
320 }
321 }
322
323 0x1: decode OPCODE_LO {
324 format IntImmOp {
325 0x0: addi({{
277 }});
278 0x4: teqi( {{ cond = (Rs_sw == (int16_t)INTIMM); }});
279 0x6: tnei( {{ cond = (Rs_sw != (int16_t)INTIMM); }});
280 }
281 }
282
283 0x2: decode REGIMM_LO {
284 format Branch {

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317 0x6: blez({{ cond = (Rs_sw <= 0); }});
318 0x7: bgtz({{ cond = (Rs_sw > 0); }});
319 }
320 }
321
322 0x1: decode OPCODE_LO {
323 format IntImmOp {
324 0x0: addi({{
326 IntReg result;
325 uint32_t result;
327 Rt = result = Rs + imm;
328 if (FullSystem &&
329 findOverflow(32, result, Rs, imm)) {
330 fault = std::make_shared<IntegerOverflowFault>();
331 }
332 }});
326 Rt = result = Rs + imm;
327 if (FullSystem &&
328 findOverflow(32, result, Rs, imm)) {
329 fault = std::make_shared<IntegerOverflowFault>();
330 }
331 }});
333 0x1: addiu({{ Rt_sw = Rs_sw + imm; }});
334 0x2: slti({{ Rt_sw = (Rs_sw < imm) ? 1 : 0 }});
335 0x3: sltiu({{ Rt_uw = (Rs_uw < (uint32_t)sextImm) ? 1 : 0;}});
336 0x4: andi({{ Rt_sw = Rs_sw & zextImm; }});
337 0x5: ori({{ Rt_sw = Rs_sw | zextImm; }});
338 0x6: xori({{ Rt_sw = Rs_sw ^ zextImm; }});
332 0x1: addiu({{ Rt = Rs_sw + imm; }});
333 0x2: slti({{ Rt = (Rs_sw < imm) ? 1 : 0 }});
334 0x3: sltiu({{ Rt = (Rs < (uint32_t)sextImm) ? 1 : 0;}});
335 0x4: andi({{ Rt = Rs_sw & zextImm; }});
336 0x5: ori({{ Rt = Rs_sw | zextImm; }});
337 0x6: xori({{ Rt = Rs_sw ^ zextImm; }});
339
340 0x7: decode RS {
341 0x0: lui({{ Rt = imm << 16; }});
342 }
343 }
344 }
345
346 0x2: decode OPCODE_LO {

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549 MT_H ? 32 : 0, Rt);
550 xc->setRegOtherThread(RegId(FloatRegClass, RD),
551 data);
552 }});
553 0x3: cttc1({{
554 uint32_t data;
555 switch (RD) {
556 case 25:
338
339 0x7: decode RS {
340 0x0: lui({{ Rt = imm << 16; }});
341 }
342 }
343 }
344
345 0x2: decode OPCODE_LO {

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548 MT_H ? 32 : 0, Rt);
549 xc->setRegOtherThread(RegId(FloatRegClass, RD),
550 data);
551 }});
552 0x3: cttc1({{
553 uint32_t data;
554 switch (RD) {
555 case 25:
557 data = (Rt_uw<7:1> << 25) | // move 31-25
556 data = (Rt<7:1> << 25) | // move 31-25
558 (FCSR & 0x01000000) | // bit 24
559 (FCSR & 0x004FFFFF); // bit 22-0
560 break;
561 case 26:
562 data = (FCSR & 0xFFFC0000) | // move 31-18
557 (FCSR & 0x01000000) | // bit 24
558 (FCSR & 0x004FFFFF); // bit 22-0
559 break;
560 case 26:
561 data = (FCSR & 0xFFFC0000) | // move 31-18
563 Rt_uw<17:12> << 12 | // bit 17-12
564 (FCSR & 0x00000F80) << 7 | // bit 11-7
565 Rt_uw<6:2> << 2 | // bit 6-2
562 Rt<17:12> << 12 | // bit 17-12
563 // bit 11-7
564 (FCSR & 0x00000F80) << 7 |
565 Rt<6:2> << 2 | // bit 6-2
566 (FCSR & 0x00000002); // bit 1...0
567 break;
568 case 28:
569 data = (FCSR & 0xFE000000) | // move 31-25
566 (FCSR & 0x00000002); // bit 1...0
567 break;
568 case 28:
569 data = (FCSR & 0xFE000000) | // move 31-25
570 Rt_uw<2:2> << 24 | // bit 24
571 (FCSR & 0x00FFF000) << 23 | // bit 23-12
572 Rt_uw<11:7> << 7 | // bit 24
570 Rt<2:2> << 24 | // bit 24
571 // bit 23-12
572 (FCSR & 0x00FFF000) << 23 |
573 Rt<11:7> << 7 | // bit 24
573 (FCSR & 0x000007E) |
574 (FCSR & 0x000007E) |
574 Rt_uw<1:0>; // bit 22-0
575 Rt<1:0>; // bit 22-0
575 break;
576 case 31:
576 break;
577 case 31:
577 data = Rt_uw;
578 data = Rt;
578 break;
579 default:
580 panic("FP Control Value (%d) "
581 "Not Available. Ignoring "
582 "Access to Floating Control "
583 "S""tatus Register", FS);
584 }
585 xc->setRegOtherThread(

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927 }
928 }
929
930 //Table A-13 MIPS32 COP1 Encoding of rs Field
931 0x1: decode RS_MSB {
932 0x0: decode RS_HI {
933 0x0: decode RS_LO {
934 format CP1Control {
579 break;
580 default:
581 panic("FP Control Value (%d) "
582 "Not Available. Ignoring "
583 "Access to Floating Control "
584 "S""tatus Register", FS);
585 }
586 xc->setRegOtherThread(

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928 }
929 }
930
931 //Table A-13 MIPS32 COP1 Encoding of rs Field
932 0x1: decode RS_MSB {
933 0x0: decode RS_HI {
934 0x0: decode RS_LO {
935 format CP1Control {
935 0x0: mfc1 ({{ Rt_uw = Fs_uw; }});
936 0x0: mfc1 ({{ Rt = Fs_uw; }});
936
937 0x2: cfc1({{
938 switch (FS) {
939 case 0:
940 Rt = FIR;
941 break;
942 case 25:
943 Rt = (FCSR & 0xFE000000) >> 24 |

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954 case 31:
955 Rt = FCSR;
956 break;
957 default:
958 warn("FP Control Value (%d) Not Valid");
959 }
960 }});
961
937
938 0x2: cfc1({{
939 switch (FS) {
940 case 0:
941 Rt = FIR;
942 break;
943 case 25:
944 Rt = (FCSR & 0xFE000000) >> 24 |

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955 case 31:
956 Rt = FCSR;
957 break;
958 default:
959 warn("FP Control Value (%d) Not Valid");
960 }
961 }});
962
962 0x3: mfhc1({{ Rt_uw = Fs_ud<63:32>; }});
963 0x3: mfhc1({{ Rt = Fs_ud<63:32>; }});
963
964
964 0x4: mtc1({{ Fs_uw = Rt_uw; }});
965 0x4: mtc1({{ Fs_uw = Rt; }});
965
966 0x6: ctc1({{
967 switch (FS) {
968 case 25:
966
967 0x6: ctc1({{
968 switch (FS) {
969 case 25:
969 FCSR = (Rt_uw<7:1> << 25) | // move 31-25
970 FCSR = (Rt<7:1> << 25) | // move 31-25
970 (FCSR & 0x01000000) | // bit 24
971 (FCSR & 0x004FFFFF); // bit 22-0
972 break;
973 case 26:
974 FCSR = (FCSR & 0xFFFC0000) | // move 31-18
971 (FCSR & 0x01000000) | // bit 24
972 (FCSR & 0x004FFFFF); // bit 22-0
973 break;
974 case 26:
975 FCSR = (FCSR & 0xFFFC0000) | // move 31-18
975 Rt_uw<17:12> << 12 | // bit 17-12
976 Rt<17:12> << 12 | // bit 17-12
976 (FCSR & 0x00000F80) << 7 | // bit 11-7
977 (FCSR & 0x00000F80) << 7 | // bit 11-7
977 Rt_uw<6:2> << 2 | // bit 6-2
978 Rt<6:2> << 2 | // bit 6-2
978 (FCSR & 0x00000002); // bit 1-0
979 break;
980 case 28:
981 FCSR = (FCSR & 0xFE000000) | // move 31-25
979 (FCSR & 0x00000002); // bit 1-0
980 break;
981 case 28:
982 FCSR = (FCSR & 0xFE000000) | // move 31-25
982 Rt_uw<2:2> << 24 | // bit 24
983 Rt<2:2> << 24 | // bit 24
983 (FCSR & 0x00FFF000) << 23 | // bit 23-12
984 (FCSR & 0x00FFF000) << 23 | // bit 23-12
984 Rt_uw<11:7> << 7 | // bit 24
985 Rt<11:7> << 7 | // bit 24
985 (FCSR & 0x000007E) |
986 (FCSR & 0x000007E) |
986 Rt_uw<1:0>; // bit 22-0
987 Rt<1:0>; // bit 22-0
987 break;
988 case 31:
988 break;
989 case 31:
989 FCSR = Rt_uw;
990 FCSR = Rt;
990 break;
991
992 default:
993 panic("FP Control Value (%d) "
994 "Not Available. Ignoring Access "
995 "to Floating Control Status "
996 "Register", FS);
997 }
998 }});
999
1000 0x7: mthc1({{
991 break;
992
993 default:
994 panic("FP Control Value (%d) "
995 "Not Available. Ignoring Access "
996 "to Floating Control Status "
997 "Register", FS);
998 }
999 }});
1000
1001 0x7: mthc1({{
1001 uint64_t fs_hi = Rt_uw;
1002 uint64_t fs_hi = Rt;
1002 uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF;
1003 Fs_ud = (fs_hi << 32) | fs_lo;
1004 }});
1005
1006 }
1007 format CP1Unimpl {
1008 0x1: dmfc1();
1009 0x5: dmtc1();

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1109 0x4: decode FUNCTION_LO {
1110 format FloatConvertOp {
1111 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble);
1112 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord);
1113 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong);
1114 }
1115
1116 0x6: FloatOp::cvt_ps_s({{
1003 uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF;
1004 Fs_ud = (fs_hi << 32) | fs_lo;
1005 }});
1006
1007 }
1008 format CP1Unimpl {
1009 0x1: dmfc1();
1010 0x5: dmtc1();

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1110 0x4: decode FUNCTION_LO {
1111 format FloatConvertOp {
1112 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble);
1113 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord);
1114 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong);
1115 }
1116
1117 0x6: FloatOp::cvt_ps_s({{
1117 Fd_ud = (uint64_t) Fs_uw << 32 |
1118 (uint64_t) Ft_uw;
1118 Fd_ud = (uint64_t)Fs_uw << 32 |
1119 (uint64_t)Ft_uw;
1119 }});
1120 format CP1Unimpl {
1121 default: unknown();
1122 }
1123 }
1124 0x5: CP1Unimpl::unknown();
1125
1126 0x6: decode FUNCTION_LO {

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1505 }
1506
1507 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1508 //Note: "COP1X instructions are legal only if 64-bit floating point
1509 //operations are enabled."
1510 0x3: decode FUNCTION_HI {
1511 0x0: decode FUNCTION_LO {
1512 format LoadIndexedMemory {
1120 }});
1121 format CP1Unimpl {
1122 default: unknown();
1123 }
1124 }
1125 0x5: CP1Unimpl::unknown();
1126
1127 0x6: decode FUNCTION_LO {

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1506 }
1507
1508 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1509 //Note: "COP1X instructions are legal only if 64-bit floating point
1510 //operations are enabled."
1511 0x3: decode FUNCTION_HI {
1512 0x0: decode FUNCTION_LO {
1513 format LoadIndexedMemory {
1513 0x0: lwxc1({{ Fd_uw = Mem_uw; }});
1514 0x0: lwxc1({{ Fd_uw = Mem; }});
1514 0x1: ldxc1({{ Fd_ud = Mem_ud; }});
1515 0x5: luxc1({{ Fd_ud = Mem_ud; }},
1516 {{ EA = (Rs + Rt) & ~7; }});
1517 }
1518 }
1519
1520 0x1: decode FUNCTION_LO {
1521 format StoreIndexedMemory {
1515 0x1: ldxc1({{ Fd_ud = Mem_ud; }});
1516 0x5: luxc1({{ Fd_ud = Mem_ud; }},
1517 {{ EA = (Rs + Rt) & ~7; }});
1518 }
1519 }
1520
1521 0x1: decode FUNCTION_LO {
1522 format StoreIndexedMemory {
1522 0x0: swxc1({{ Mem_uw = Fs_uw; }});
1523 0x0: swxc1({{ Mem = Fs_uw; }});
1523 0x1: sdxc1({{ Mem_ud = Fs_ud; }});
1524 0x5: suxc1({{ Mem_ud = Fs_ud; }},
1525 {{ EA = (Rs + Rt) & ~7; }});
1526 }
1527 0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
1528 }
1529
1530 0x3: decode FUNCTION_LO {

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1590 }
1591
1592 0x3: decode OPCODE_LO {
1593 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1594 0x4: decode FUNCTION_HI {
1595 0x0: decode FUNCTION_LO {
1596 0x2: IntOp::mul({{
1597 int64_t temp1 = Rs_sd * Rt_sd;
1524 0x1: sdxc1({{ Mem_ud = Fs_ud; }});
1525 0x5: suxc1({{ Mem_ud = Fs_ud; }},
1526 {{ EA = (Rs + Rt) & ~7; }});
1527 }
1528 0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
1529 }
1530
1531 0x3: decode FUNCTION_LO {

--- 59 unchanged lines hidden (view full) ---

1591 }
1592
1593 0x3: decode OPCODE_LO {
1594 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1595 0x4: decode FUNCTION_HI {
1596 0x0: decode FUNCTION_LO {
1597 0x2: IntOp::mul({{
1598 int64_t temp1 = Rs_sd * Rt_sd;
1598 Rd_sw = temp1<31:0>;
1599 Rd = temp1<31:0>;
1599 }}, IntMultOp);
1600
1601 format HiLoRdSelValOp {
1602 0x0: madd({{
1603 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) +
1604 (Rs_sd * Rt_sd);
1605 }}, IntMultOp);
1606 0x1: maddu({{

--- 16 unchanged lines hidden (view full) ---

1623 0x0: clz({{
1624 int cnt = 32;
1625 for (int idx = 31; idx >= 0; idx--) {
1626 if (Rs<idx:idx> == 1) {
1627 cnt = 31 - idx;
1628 break;
1629 }
1630 }
1600 }}, IntMultOp);
1601
1602 format HiLoRdSelValOp {
1603 0x0: madd({{
1604 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) +
1605 (Rs_sd * Rt_sd);
1606 }}, IntMultOp);
1607 0x1: maddu({{

--- 16 unchanged lines hidden (view full) ---

1624 0x0: clz({{
1625 int cnt = 32;
1626 for (int idx = 31; idx >= 0; idx--) {
1627 if (Rs<idx:idx> == 1) {
1628 cnt = 31 - idx;
1629 break;
1630 }
1631 }
1631 Rd_uw = cnt;
1632 Rd = cnt;
1632 }});
1633 0x1: clo({{
1634 int cnt = 32;
1635 for (int idx = 31; idx >= 0; idx--) {
1636 if (Rs<idx:idx> == 0) {
1637 cnt = 31 - idx;
1638 break;
1639 }
1640 }
1633 }});
1634 0x1: clo({{
1635 int cnt = 32;
1636 for (int idx = 31; idx >= 0; idx--) {
1637 if (Rs<idx:idx> == 0) {
1638 cnt = 31 - idx;
1639 break;
1640 }
1641 }
1641 Rd_uw = cnt;
1642 Rd = cnt;
1642 }});
1643 }
1644 }
1645
1646 0x7: decode FUNCTION_LO {
1647 0x7: FailUnimpl::sdbbp();
1648 }
1649 }
1650
1651 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
1652 //of the Architecture
1653 0x7: decode FUNCTION_HI {
1654 0x0: decode FUNCTION_LO {
1655 format BasicOp {
1643 }});
1644 }
1645 }
1646
1647 0x7: decode FUNCTION_LO {
1648 0x7: FailUnimpl::sdbbp();
1649 }
1650 }
1651
1652 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
1653 //of the Architecture
1654 0x7: decode FUNCTION_HI {
1655 0x0: decode FUNCTION_LO {
1656 format BasicOp {
1656 0x0: ext({{ Rt_uw = bits(Rs_uw, MSB+LSB, LSB); }});
1657 0x0: ext({{ Rt = bits(Rs, MSB + LSB, LSB); }});
1657 0x4: ins({{
1658 0x4: ins({{
1658 Rt_uw = bits(Rt_uw, 31, MSB+1) << (MSB+1) |
1659 bits(Rs_uw, MSB-LSB, 0) << LSB |
1660 bits(Rt_uw, LSB-1, 0);
1659 Rt = bits(Rt, 31, MSB + 1) << (MSB + 1) |
1660 bits(Rs, MSB - LSB, 0) << LSB |
1661 bits(Rt, LSB - 1, 0);
1661 }});
1662 }
1663 }
1664
1665 0x1: decode FUNCTION_LO {
1666 format MT_Control {
1667 0x0: fork({{
1668 forkThread(xc->tcBase(), fault, RD, Rs, Rt);
1669 }}, UserMode);
1670 0x1: yield({{
1662 }});
1663 }
1664 }
1665
1666 0x1: decode FUNCTION_LO {
1667 format MT_Control {
1668 0x0: fork({{
1669 forkThread(xc->tcBase(), fault, RD, Rs, Rt);
1670 }}, UserMode);
1671 0x1: yield({{
1671 Rd_sw = yieldThread(xc->tcBase(), fault, Rs_sw,
1672 Rd = yieldThread(xc->tcBase(), fault, Rs_sw,
1672 YQMask);
1673 }}, UserMode);
1674 }
1675
1676 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL)
1677 0x2: decode OP_HI {
1678 0x0: decode OP_LO {
1679 format LoadIndexedMemory {
1673 YQMask);
1674 }}, UserMode);
1675 }
1676
1677 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL)
1678 0x2: decode OP_HI {
1679 0x0: decode OP_LO {
1680 format LoadIndexedMemory {
1680 0x0: lwx({{ Rd_sw = Mem_sw; }});
1681 0x4: lhx({{ Rd_sw = Mem_sh; }});
1682 0x6: lbux({{ Rd_uw = Mem_ub; }});
1681 0x0: lwx({{ Rd = Mem; }});
1682 0x4: lhx({{ Rd = Mem_sh; }});
1683 0x6: lbux({{ Rd = Mem_ub; }});
1683 }
1684 }
1685 }
1686 0x4: DspIntOp::insv({{
1687 int pos = dspctl<5:0>;
1688 int size = dspctl<12:7> - 1;
1684 }
1685 }
1686 }
1687 0x4: DspIntOp::insv({{
1688 int pos = dspctl<5:0>;
1689 int size = dspctl<12:7> - 1;
1689 Rt_uw = insertBits(Rt_uw, pos+size,
1690 pos, Rs_uw<size:0>);
1690 Rt = insertBits(Rt, pos + size, pos, Rs<size:0>);
1691 }});
1692 }
1693
1694 0x2: decode FUNCTION_LO {
1695
1696 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field
1697 //(DSP ASE MANUAL)
1698 0x0: decode OP_HI {
1699 0x0: decode OP_LO {
1700 format DspIntOp {
1701 0x0: addu_qb({{
1691 }});
1692 }
1693
1694 0x2: decode FUNCTION_LO {
1695
1696 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field
1697 //(DSP ASE MANUAL)
1698 0x0: decode OP_HI {
1699 0x0: decode OP_LO {
1700 format DspIntOp {
1701 0x0: addu_qb({{
1702 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1703 NOSATURATE, UNSIGNED, &dspctl);
1702 Rd = dspAdd(Rs, Rt, SIMD_FMT_QB,
1703 NOSATURATE, UNSIGNED, &dspctl);
1704 }});
1705 0x1: subu_qb({{
1704 }});
1705 0x1: subu_qb({{
1706 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB,
1707 NOSATURATE, UNSIGNED, &dspctl);
1706 Rd = dspSub(Rs, Rt, SIMD_FMT_QB,
1707 NOSATURATE, UNSIGNED, &dspctl);
1708 }});
1709 0x4: addu_s_qb({{
1708 }});
1709 0x4: addu_s_qb({{
1710 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1711 SATURATE, UNSIGNED, &dspctl);
1710 Rd = dspAdd(Rs, Rt, SIMD_FMT_QB,
1711 SATURATE, UNSIGNED, &dspctl);
1712 }});
1713 0x5: subu_s_qb({{
1712 }});
1713 0x5: subu_s_qb({{
1714 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB,
1715 SATURATE, UNSIGNED, &dspctl);
1714 Rd = dspSub(Rs, Rt, SIMD_FMT_QB,
1715 SATURATE, UNSIGNED, &dspctl);
1716 }});
1717 0x6: muleu_s_ph_qbl({{
1716 }});
1717 0x6: muleu_s_ph_qbl({{
1718 Rd_uw = dspMuleu(Rs_uw, Rt_uw,
1719 MODE_L, &dspctl);
1718 Rd = dspMuleu(Rs, Rt, MODE_L, &dspctl);
1720 }}, IntMultOp);
1721 0x7: muleu_s_ph_qbr({{
1719 }}, IntMultOp);
1720 0x7: muleu_s_ph_qbr({{
1722 Rd_uw = dspMuleu(Rs_uw, Rt_uw,
1723 MODE_R, &dspctl);
1721 Rd = dspMuleu(Rs, Rt, MODE_R, &dspctl);
1724 }}, IntMultOp);
1725 }
1726 }
1727 0x1: decode OP_LO {
1728 format DspIntOp {
1729 0x0: addu_ph({{
1722 }}, IntMultOp);
1723 }
1724 }
1725 0x1: decode OP_LO {
1726 format DspIntOp {
1727 0x0: addu_ph({{
1730 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH,
1731 NOSATURATE, UNSIGNED, &dspctl);
1728 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH,
1729 NOSATURATE, UNSIGNED, &dspctl);
1732 }});
1733 0x1: subu_ph({{
1730 }});
1731 0x1: subu_ph({{
1734 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH,
1735 NOSATURATE, UNSIGNED, &dspctl);
1732 Rd = dspSub(Rs, Rt, SIMD_FMT_PH,
1733 NOSATURATE, UNSIGNED, &dspctl);
1736 }});
1737 0x2: addq_ph({{
1734 }});
1735 0x2: addq_ph({{
1738 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH,
1739 NOSATURATE, SIGNED, &dspctl);
1736 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH,
1737 NOSATURATE, SIGNED, &dspctl);
1740 }});
1741 0x3: subq_ph({{
1738 }});
1739 0x3: subq_ph({{
1742 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH,
1743 NOSATURATE, SIGNED, &dspctl);
1740 Rd = dspSub(Rs, Rt, SIMD_FMT_PH,
1741 NOSATURATE, SIGNED, &dspctl);
1744 }});
1745 0x4: addu_s_ph({{
1742 }});
1743 0x4: addu_s_ph({{
1746 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH,
1747 SATURATE, UNSIGNED, &dspctl);
1744 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH,
1745 SATURATE, UNSIGNED, &dspctl);
1748 }});
1749 0x5: subu_s_ph({{
1746 }});
1747 0x5: subu_s_ph({{
1750 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH,
1751 SATURATE, UNSIGNED, &dspctl);
1748 Rd = dspSub(Rs, Rt, SIMD_FMT_PH,
1749 SATURATE, UNSIGNED, &dspctl);
1752 }});
1753 0x6: addq_s_ph({{
1750 }});
1751 0x6: addq_s_ph({{
1754 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH,
1755 SATURATE, SIGNED, &dspctl);
1752 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH,
1753 SATURATE, SIGNED, &dspctl);
1756 }});
1757 0x7: subq_s_ph({{
1754 }});
1755 0x7: subq_s_ph({{
1758 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH,
1759 SATURATE, SIGNED, &dspctl);
1756 Rd = dspSub(Rs, Rt, SIMD_FMT_PH,
1757 SATURATE, SIGNED, &dspctl);
1760 }});
1761 }
1762 }
1763 0x2: decode OP_LO {
1764 format DspIntOp {
1765 0x0: addsc({{
1766 int64_t dresult;
1767 dresult = Rs_ud + Rt_ud;
1758 }});
1759 }
1760 }
1761 0x2: decode OP_LO {
1762 format DspIntOp {
1763 0x0: addsc({{
1764 int64_t dresult;
1765 dresult = Rs_ud + Rt_ud;
1768 Rd_sw = dresult<31:0>;
1766 Rd = dresult<31:0>;
1769 dspctl = insertBits(dspctl, 13, 13,
1770 dresult<32:32>);
1771 }});
1772 0x1: addwc({{
1773 int64_t dresult;
1774 dresult = Rs_sd + Rt_sd + dspctl<13:13>;
1767 dspctl = insertBits(dspctl, 13, 13,
1768 dresult<32:32>);
1769 }});
1770 0x1: addwc({{
1771 int64_t dresult;
1772 dresult = Rs_sd + Rt_sd + dspctl<13:13>;
1775 Rd_sw = dresult<31:0>;
1773 Rd = dresult<31:0>;
1776 if (dresult<32:32> != dresult<31:31>)
1777 dspctl = insertBits(dspctl, 20, 20, 1);
1778 }});
1779 0x2: modsub({{
1774 if (dresult<32:32> != dresult<31:31>)
1775 dspctl = insertBits(dspctl, 20, 20, 1);
1776 }});
1777 0x2: modsub({{
1780 Rd_sw = (Rs_sw == 0) ? Rt_sw<23:8> :
1778 Rd = (Rs_sw == 0) ? Rt_sw<23:8> :
1781 Rs_sw - Rt_sw<7:0>;
1782 }});
1783 0x4: raddu_w_qb({{
1779 Rs_sw - Rt_sw<7:0>;
1780 }});
1781 0x4: raddu_w_qb({{
1784 Rd_uw = Rs_uw<31:24> + Rs_uw<23:16> +
1785 Rs_uw<15:8> + Rs_uw<7:0>;
1782 Rd = Rs<31:24> + Rs<23:16> +
1783 Rs<15:8> + Rs<7:0>;
1786 }});
1787 0x6: addq_s_w({{
1784 }});
1785 0x6: addq_s_w({{
1788 Rd_sw = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W,
1786 Rd = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W,
1789 SATURATE, SIGNED, &dspctl);
1790 }});
1791 0x7: subq_s_w({{
1787 SATURATE, SIGNED, &dspctl);
1788 }});
1789 0x7: subq_s_w({{
1792 Rd_sw = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W,
1790 Rd = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W,
1793 SATURATE, SIGNED, &dspctl);
1794 }});
1795 }
1796 }
1797 0x3: decode OP_LO {
1798 format DspIntOp {
1799 0x4: muleq_s_w_phl({{
1791 SATURATE, SIGNED, &dspctl);
1792 }});
1793 }
1794 }
1795 0x3: decode OP_LO {
1796 format DspIntOp {
1797 0x4: muleq_s_w_phl({{
1800 Rd_sw = dspMuleq(Rs_sw, Rt_sw,
1798 Rd = dspMuleq(Rs_sw, Rt_sw,
1801 MODE_L, &dspctl);
1802 }}, IntMultOp);
1803 0x5: muleq_s_w_phr({{
1799 MODE_L, &dspctl);
1800 }}, IntMultOp);
1801 0x5: muleq_s_w_phr({{
1804 Rd_sw = dspMuleq(Rs_sw, Rt_sw,
1802 Rd = dspMuleq(Rs_sw, Rt_sw,
1805 MODE_R, &dspctl);
1806 }}, IntMultOp);
1807 0x6: mulq_s_ph({{
1803 MODE_R, &dspctl);
1804 }}, IntMultOp);
1805 0x6: mulq_s_ph({{
1808 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH,
1806 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH,
1809 SATURATE, NOROUND, &dspctl);
1810 }}, IntMultOp);
1811 0x7: mulq_rs_ph({{
1807 SATURATE, NOROUND, &dspctl);
1808 }}, IntMultOp);
1809 0x7: mulq_rs_ph({{
1812 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH,
1810 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH,
1813 SATURATE, ROUND, &dspctl);
1814 }}, IntMultOp);
1815 }
1816 }
1817 }
1818
1819 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field
1820 //(DSP ASE MANUAL)
1821 0x1: decode OP_HI {
1822 0x0: decode OP_LO {
1823 format DspIntOp {
1824 0x0: cmpu_eq_qb({{
1811 SATURATE, ROUND, &dspctl);
1812 }}, IntMultOp);
1813 }
1814 }
1815 }
1816
1817 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field
1818 //(DSP ASE MANUAL)
1819 0x1: decode OP_HI {
1820 0x0: decode OP_LO {
1821 format DspIntOp {
1822 0x0: cmpu_eq_qb({{
1825 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB,
1823 dspCmp(Rs, Rt, SIMD_FMT_QB,
1826 UNSIGNED, CMP_EQ, &dspctl);
1827 }});
1828 0x1: cmpu_lt_qb({{
1824 UNSIGNED, CMP_EQ, &dspctl);
1825 }});
1826 0x1: cmpu_lt_qb({{
1829 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB,
1827 dspCmp(Rs, Rt, SIMD_FMT_QB,
1830 UNSIGNED, CMP_LT, &dspctl);
1831 }});
1832 0x2: cmpu_le_qb({{
1828 UNSIGNED, CMP_LT, &dspctl);
1829 }});
1830 0x2: cmpu_le_qb({{
1833 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB,
1831 dspCmp(Rs, Rt, SIMD_FMT_QB,
1834 UNSIGNED, CMP_LE, &dspctl);
1835 }});
1836 0x3: pick_qb({{
1832 UNSIGNED, CMP_LE, &dspctl);
1833 }});
1834 0x3: pick_qb({{
1837 Rd_uw = dspPick(Rs_uw, Rt_uw,
1838 SIMD_FMT_QB, &dspctl);
1835 Rd = dspPick(Rs, Rt, SIMD_FMT_QB, &dspctl);
1839 }});
1840 0x4: cmpgu_eq_qb({{
1836 }});
1837 0x4: cmpgu_eq_qb({{
1841 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB,
1842 UNSIGNED, CMP_EQ );
1838 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB,
1839 UNSIGNED, CMP_EQ );
1843 }});
1844 0x5: cmpgu_lt_qb({{
1840 }});
1841 0x5: cmpgu_lt_qb({{
1845 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB,
1846 UNSIGNED, CMP_LT);
1842 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB,
1843 UNSIGNED, CMP_LT);
1847 }});
1848 0x6: cmpgu_le_qb({{
1844 }});
1845 0x6: cmpgu_le_qb({{
1849 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB,
1850 UNSIGNED, CMP_LE);
1846 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB,
1847 UNSIGNED, CMP_LE);
1851 }});
1852 }
1853 }
1854 0x1: decode OP_LO {
1855 format DspIntOp {
1856 0x0: cmp_eq_ph({{
1848 }});
1849 }
1850 }
1851 0x1: decode OP_LO {
1852 format DspIntOp {
1853 0x0: cmp_eq_ph({{
1857 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH,
1854 dspCmp(Rs, Rt, SIMD_FMT_PH,
1858 SIGNED, CMP_EQ, &dspctl);
1859 }});
1860 0x1: cmp_lt_ph({{
1855 SIGNED, CMP_EQ, &dspctl);
1856 }});
1857 0x1: cmp_lt_ph({{
1861 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH,
1858 dspCmp(Rs, Rt, SIMD_FMT_PH,
1862 SIGNED, CMP_LT, &dspctl);
1863 }});
1864 0x2: cmp_le_ph({{
1859 SIGNED, CMP_LT, &dspctl);
1860 }});
1861 0x2: cmp_le_ph({{
1865 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH,
1862 dspCmp(Rs, Rt, SIMD_FMT_PH,
1866 SIGNED, CMP_LE, &dspctl);
1867 }});
1868 0x3: pick_ph({{
1863 SIGNED, CMP_LE, &dspctl);
1864 }});
1865 0x3: pick_ph({{
1869 Rd_uw = dspPick(Rs_uw, Rt_uw,
1870 SIMD_FMT_PH, &dspctl);
1866 Rd = dspPick(Rs, Rt, SIMD_FMT_PH, &dspctl);
1871 }});
1872 0x4: precrq_qb_ph({{
1867 }});
1868 0x4: precrq_qb_ph({{
1873 Rd_uw = Rs_uw<31:24> << 24 |
1874 Rs_uw<15:8> << 16 |
1875 Rt_uw<31:24> << 8 |
1876 Rt_uw<15:8>;
1869 Rd = Rs<31:24> << 24 | Rs<15:8> << 16 |
1870 Rt<31:24> << 8 | Rt<15:8>;
1877 }});
1878 0x5: precr_qb_ph({{
1871 }});
1872 0x5: precr_qb_ph({{
1879 Rd_uw = Rs_uw<23:16> << 24 |
1880 Rs_uw<7:0> << 16 |
1881 Rt_uw<23:16> << 8 |
1882 Rt_uw<7:0>;
1873 Rd = Rs<23:16> << 24 | Rs<7:0> << 16 |
1874 Rt<23:16> << 8 | Rt<7:0>;
1883 }});
1884 0x6: packrl_ph({{
1875 }});
1876 0x6: packrl_ph({{
1885 Rd_uw = dspPack(Rs_uw, Rt_uw, SIMD_FMT_PH);
1877 Rd = dspPack(Rs, Rt, SIMD_FMT_PH);
1886 }});
1887 0x7: precrqu_s_qb_ph({{
1878 }});
1879 0x7: precrqu_s_qb_ph({{
1888 Rd_uw = dspPrecrqu(Rs_uw, Rt_uw, &dspctl);
1880 Rd = dspPrecrqu(Rs, Rt, &dspctl);
1889 }});
1890 }
1891 }
1892 0x2: decode OP_LO {
1893 format DspIntOp {
1894 0x4: precrq_ph_w({{
1881 }});
1882 }
1883 }
1884 0x2: decode OP_LO {
1885 format DspIntOp {
1886 0x4: precrq_ph_w({{
1895 Rd_uw = Rs_uw<31:16> << 16 | Rt_uw<31:16>;
1887 Rd = Rs<31:16> << 16 | Rt<31:16>;
1896 }});
1897 0x5: precrq_rs_ph_w({{
1888 }});
1889 0x5: precrq_rs_ph_w({{
1898 Rd_uw = dspPrecrq(Rs_uw, Rt_uw,
1899 SIMD_FMT_W, &dspctl);
1890 Rd = dspPrecrq(Rs, Rt, SIMD_FMT_W, &dspctl);
1900 }});
1901 }
1902 }
1903 0x3: decode OP_LO {
1904 format DspIntOp {
1905 0x0: cmpgdu_eq_qb({{
1891 }});
1892 }
1893 }
1894 0x3: decode OP_LO {
1895 format DspIntOp {
1896 0x0: cmpgdu_eq_qb({{
1906 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1907 UNSIGNED, CMP_EQ, &dspctl);
1897 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB,
1898 UNSIGNED, CMP_EQ, &dspctl);
1908 }});
1909 0x1: cmpgdu_lt_qb({{
1899 }});
1900 0x1: cmpgdu_lt_qb({{
1910 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1911 UNSIGNED, CMP_LT, &dspctl);
1901 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB,
1902 UNSIGNED, CMP_LT, &dspctl);
1912 }});
1913 0x2: cmpgdu_le_qb({{
1903 }});
1904 0x2: cmpgdu_le_qb({{
1914 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1915 UNSIGNED, CMP_LE, &dspctl);
1905 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB,
1906 UNSIGNED, CMP_LE, &dspctl);
1916 }});
1917 0x6: precr_sra_ph_w({{
1907 }});
1908 0x6: precr_sra_ph_w({{
1918 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
1919 SIMD_FMT_W, NOROUND);
1909 Rt = dspPrecrSra(Rt, Rs, RD,
1910 SIMD_FMT_W, NOROUND);
1920 }});
1921 0x7: precr_sra_r_ph_w({{
1911 }});
1912 0x7: precr_sra_r_ph_w({{
1922 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
1923 SIMD_FMT_W, ROUND);
1913 Rt = dspPrecrSra(Rt, Rs, RD,
1914 SIMD_FMT_W, ROUND);
1924 }});
1925 }
1926 }
1927 }
1928
1929 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field
1930 //(DSP ASE MANUAL)
1931 0x2: decode OP_HI {
1932 0x0: decode OP_LO {
1933 format DspIntOp {
1934 0x1: absq_s_qb({{
1915 }});
1916 }
1917 }
1918 }
1919
1920 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field
1921 //(DSP ASE MANUAL)
1922 0x2: decode OP_HI {
1923 0x0: decode OP_LO {
1924 format DspIntOp {
1925 0x1: absq_s_qb({{
1935 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl);
1926 Rd = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl);
1936 }});
1937 0x2: repl_qb({{
1927 }});
1928 0x2: repl_qb({{
1938 Rd_uw = RS_RT<7:0> << 24 |
1939 RS_RT<7:0> << 16 |
1940 RS_RT<7:0> << 8 |
1941 RS_RT<7:0>;
1929 Rd = RS_RT<7:0> << 24 | RS_RT<7:0> << 16 |
1930 RS_RT<7:0> << 8 | RS_RT<7:0>;
1942 }});
1943 0x3: replv_qb({{
1931 }});
1932 0x3: replv_qb({{
1944 Rd_sw = Rt_uw<7:0> << 24 |
1945 Rt_uw<7:0> << 16 |
1946 Rt_uw<7:0> << 8 |
1947 Rt_uw<7:0>;
1933 Rd = Rt<7:0> << 24 | Rt<7:0> << 16 |
1934 Rt<7:0> << 8 | Rt<7:0>;
1948 }});
1949 0x4: precequ_ph_qbl({{
1935 }});
1936 0x4: precequ_ph_qbl({{
1950 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED,
1951 SIMD_FMT_PH, SIGNED, MODE_L);
1937 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED,
1938 SIMD_FMT_PH, SIGNED, MODE_L);
1952 }});
1953 0x5: precequ_ph_qbr({{
1939 }});
1940 0x5: precequ_ph_qbr({{
1954 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED,
1955 SIMD_FMT_PH, SIGNED, MODE_R);
1941 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED,
1942 SIMD_FMT_PH, SIGNED, MODE_R);
1956 }});
1957 0x6: precequ_ph_qbla({{
1943 }});
1944 0x6: precequ_ph_qbla({{
1958 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED,
1959 SIMD_FMT_PH, SIGNED, MODE_LA);
1945 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED,
1946 SIMD_FMT_PH, SIGNED, MODE_LA);
1960 }});
1961 0x7: precequ_ph_qbra({{
1947 }});
1948 0x7: precequ_ph_qbra({{
1962 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED,
1963 SIMD_FMT_PH, SIGNED, MODE_RA);
1949 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED,
1950 SIMD_FMT_PH, SIGNED, MODE_RA);
1964 }});
1965 }
1966 }
1967 0x1: decode OP_LO {
1968 format DspIntOp {
1969 0x1: absq_s_ph({{
1951 }});
1952 }
1953 }
1954 0x1: decode OP_LO {
1955 format DspIntOp {
1956 0x1: absq_s_ph({{
1970 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl);
1957 Rd = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl);
1971 }});
1972 0x2: repl_ph({{
1958 }});
1959 0x2: repl_ph({{
1973 Rd_uw = (sext<10>(RS_RT))<15:0> << 16 |
1960 Rd = (sext<10>(RS_RT))<15:0> << 16 |
1974 (sext<10>(RS_RT))<15:0>;
1975 }});
1976 0x3: replv_ph({{
1961 (sext<10>(RS_RT))<15:0>;
1962 }});
1963 0x3: replv_ph({{
1977 Rd_uw = Rt_uw<15:0> << 16 |
1978 Rt_uw<15:0>;
1964 Rd = Rt<15:0> << 16 | Rt<15:0>;
1979 }});
1980 0x4: preceq_w_phl({{
1965 }});
1966 0x4: preceq_w_phl({{
1981 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED,
1982 SIMD_FMT_W, SIGNED, MODE_L);
1967 Rd = dspPrece(Rt, SIMD_FMT_PH, SIGNED,
1968 SIMD_FMT_W, SIGNED, MODE_L);
1983 }});
1984 0x5: preceq_w_phr({{
1969 }});
1970 0x5: preceq_w_phr({{
1985 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED,
1986 SIMD_FMT_W, SIGNED, MODE_R);
1971 Rd = dspPrece(Rt, SIMD_FMT_PH, SIGNED,
1972 SIMD_FMT_W, SIGNED, MODE_R);
1987 }});
1988 }
1989 }
1990 0x2: decode OP_LO {
1991 format DspIntOp {
1992 0x1: absq_s_w({{
1973 }});
1974 }
1975 }
1976 0x2: decode OP_LO {
1977 format DspIntOp {
1978 0x1: absq_s_w({{
1993 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl);
1979 Rd = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl);
1994 }});
1995 }
1996 }
1997 0x3: decode OP_LO {
1998 0x3: IntOp::bitrev({{
1980 }});
1981 }
1982 }
1983 0x3: decode OP_LO {
1984 0x3: IntOp::bitrev({{
1999 Rd_uw = bitrev( Rt_uw<15:0> );
1985 Rd = bitrev(Rt<15:0>);
2000 }});
2001 format DspIntOp {
2002 0x4: preceu_ph_qbl({{
1986 }});
1987 format DspIntOp {
1988 0x4: preceu_ph_qbl({{
2003 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB,
2004 UNSIGNED, SIMD_FMT_PH,
1989 Rd = dspPrece(Rt, SIMD_FMT_QB,
1990 UNSIGNED, SIMD_FMT_PH,
2005 UNSIGNED, MODE_L);
2006 }});
2007 0x5: preceu_ph_qbr({{
1991 UNSIGNED, MODE_L);
1992 }});
1993 0x5: preceu_ph_qbr({{
2008 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB,
2009 UNSIGNED, SIMD_FMT_PH,
1994 Rd = dspPrece(Rt, SIMD_FMT_QB,
1995 UNSIGNED, SIMD_FMT_PH,
2010 UNSIGNED, MODE_R );
2011 }});
2012 0x6: preceu_ph_qbla({{
1996 UNSIGNED, MODE_R );
1997 }});
1998 0x6: preceu_ph_qbla({{
2013 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB,
2014 UNSIGNED, SIMD_FMT_PH,
2015 UNSIGNED, MODE_LA );
1999 Rd = dspPrece(Rt, SIMD_FMT_QB,
2000 UNSIGNED, SIMD_FMT_PH,
2001 UNSIGNED, MODE_LA );
2016 }});
2017 0x7: preceu_ph_qbra({{
2002 }});
2003 0x7: preceu_ph_qbra({{
2018 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB,
2019 UNSIGNED, SIMD_FMT_PH,
2004 Rd = dspPrece(Rt, SIMD_FMT_QB,
2005 UNSIGNED, SIMD_FMT_PH,
2020 UNSIGNED, MODE_RA);
2021 }});
2022 }
2023 }
2024 }
2025
2026 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field
2027 //(DSP ASE MANUAL)
2028 0x3: decode OP_HI {
2029 0x0: decode OP_LO {
2030 format DspIntOp {
2031 0x0: shll_qb({{
2006 UNSIGNED, MODE_RA);
2007 }});
2008 }
2009 }
2010 }
2011
2012 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field
2013 //(DSP ASE MANUAL)
2014 0x3: decode OP_HI {
2015 0x0: decode OP_LO {
2016 format DspIntOp {
2017 0x0: shll_qb({{
2032 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_QB,
2033 NOSATURATE, UNSIGNED, &dspctl);
2018 Rd = dspShll(Rt_sw, RS, SIMD_FMT_QB,
2019 NOSATURATE, UNSIGNED, &dspctl);
2034 }});
2035 0x1: shrl_qb({{
2020 }});
2021 0x1: shrl_qb({{
2036 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_QB,
2037 UNSIGNED);
2022 Rd = dspShrl(Rt_sw, RS, SIMD_FMT_QB,
2023 UNSIGNED);
2038 }});
2039 0x2: shllv_qb({{
2024 }});
2025 0x2: shllv_qb({{
2040 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB,
2041 NOSATURATE, UNSIGNED, &dspctl);
2026 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB,
2027 NOSATURATE, UNSIGNED, &dspctl);
2042 }});
2043 0x3: shrlv_qb({{
2028 }});
2029 0x3: shrlv_qb({{
2044 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB,
2045 UNSIGNED);
2030 Rd = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB,
2031 UNSIGNED);
2046 }});
2047 0x4: shra_qb({{
2032 }});
2033 0x4: shra_qb({{
2048 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB,
2049 NOROUND, SIGNED, &dspctl);
2034 Rd = dspShra(Rt_sw, RS, SIMD_FMT_QB,
2035 NOROUND, SIGNED, &dspctl);
2050 }});
2051 0x5: shra_r_qb({{
2036 }});
2037 0x5: shra_r_qb({{
2052 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB,
2053 ROUND, SIGNED, &dspctl);
2038 Rd = dspShra(Rt_sw, RS, SIMD_FMT_QB,
2039 ROUND, SIGNED, &dspctl);
2054 }});
2055 0x6: shrav_qb({{
2040 }});
2041 0x6: shrav_qb({{
2056 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB,
2057 NOROUND, SIGNED, &dspctl);
2042 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB,
2043 NOROUND, SIGNED, &dspctl);
2058 }});
2059 0x7: shrav_r_qb({{
2044 }});
2045 0x7: shrav_r_qb({{
2060 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB,
2061 ROUND, SIGNED, &dspctl);
2046 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB,
2047 ROUND, SIGNED, &dspctl);
2062 }});
2063 }
2064 }
2065 0x1: decode OP_LO {
2066 format DspIntOp {
2067 0x0: shll_ph({{
2048 }});
2049 }
2050 }
2051 0x1: decode OP_LO {
2052 format DspIntOp {
2053 0x0: shll_ph({{
2068 Rd_uw = dspShll(Rt_uw, RS, SIMD_FMT_PH,
2069 NOSATURATE, SIGNED, &dspctl);
2054 Rd = dspShll(Rt, RS, SIMD_FMT_PH,
2055 NOSATURATE, SIGNED, &dspctl);
2070 }});
2071 0x1: shra_ph({{
2056 }});
2057 0x1: shra_ph({{
2072 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH,
2073 NOROUND, SIGNED, &dspctl);
2058 Rd = dspShra(Rt_sw, RS, SIMD_FMT_PH,
2059 NOROUND, SIGNED, &dspctl);
2074 }});
2075 0x2: shllv_ph({{
2060 }});
2061 0x2: shllv_ph({{
2076 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH,
2077 NOSATURATE, SIGNED, &dspctl);
2062 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH,
2063 NOSATURATE, SIGNED, &dspctl);
2078 }});
2079 0x3: shrav_ph({{
2064 }});
2065 0x3: shrav_ph({{
2080 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH,
2081 NOROUND, SIGNED, &dspctl);
2066 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH,
2067 NOROUND, SIGNED, &dspctl);
2082 }});
2083 0x4: shll_s_ph({{
2068 }});
2069 0x4: shll_s_ph({{
2084 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_PH,
2085 SATURATE, SIGNED, &dspctl);
2070 Rd = dspShll(Rt_sw, RS, SIMD_FMT_PH,
2071 SATURATE, SIGNED, &dspctl);
2086 }});
2087 0x5: shra_r_ph({{
2072 }});
2073 0x5: shra_r_ph({{
2088 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH,
2089 ROUND, SIGNED, &dspctl);
2074 Rd = dspShra(Rt_sw, RS, SIMD_FMT_PH,
2075 ROUND, SIGNED, &dspctl);
2090 }});
2091 0x6: shllv_s_ph({{
2076 }});
2077 0x6: shllv_s_ph({{
2092 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH,
2093 SATURATE, SIGNED, &dspctl);
2078 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH,
2079 SATURATE, SIGNED, &dspctl);
2094 }});
2095 0x7: shrav_r_ph({{
2080 }});
2081 0x7: shrav_r_ph({{
2096 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH,
2097 ROUND, SIGNED, &dspctl);
2082 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH,
2083 ROUND, SIGNED, &dspctl);
2098 }});
2099 }
2100 }
2101 0x2: decode OP_LO {
2102 format DspIntOp {
2103 0x4: shll_s_w({{
2084 }});
2085 }
2086 }
2087 0x2: decode OP_LO {
2088 format DspIntOp {
2089 0x4: shll_s_w({{
2104 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_W,
2105 SATURATE, SIGNED, &dspctl);
2090 Rd = dspShll(Rt_sw, RS, SIMD_FMT_W,
2091 SATURATE, SIGNED, &dspctl);
2106 }});
2107 0x5: shra_r_w({{
2092 }});
2093 0x5: shra_r_w({{
2108 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_W,
2109 ROUND, SIGNED, &dspctl);
2094 Rd = dspShra(Rt_sw, RS, SIMD_FMT_W,
2095 ROUND, SIGNED, &dspctl);
2110 }});
2111 0x6: shllv_s_w({{
2096 }});
2097 0x6: shllv_s_w({{
2112 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W,
2113 SATURATE, SIGNED, &dspctl);
2098 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W,
2099 SATURATE, SIGNED, &dspctl);
2114 }});
2115 0x7: shrav_r_w({{
2100 }});
2101 0x7: shrav_r_w({{
2116 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W,
2117 ROUND, SIGNED, &dspctl);
2102 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W,
2103 ROUND, SIGNED, &dspctl);
2118 }});
2119 }
2120 }
2121 0x3: decode OP_LO {
2122 format DspIntOp {
2123 0x1: shrl_ph({{
2104 }});
2105 }
2106 }
2107 0x3: decode OP_LO {
2108 format DspIntOp {
2109 0x1: shrl_ph({{
2124 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_PH,
2125 UNSIGNED);
2110 Rd = dspShrl(Rt_sw, RS, SIMD_FMT_PH,
2111 UNSIGNED);
2126 }});
2127 0x3: shrlv_ph({{
2112 }});
2113 0x3: shrlv_ph({{
2128 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH,
2129 UNSIGNED);
2114 Rd = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH,
2115 UNSIGNED);
2130 }});
2131 }
2132 }
2133 }
2134 }
2135
2136 0x3: decode FUNCTION_LO {
2137
2138 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field
2139 //(DSP ASE Rev2 Manual)
2140 0x0: decode OP_HI {
2141 0x0: decode OP_LO {
2142 format DspIntOp {
2143 0x0: adduh_qb({{
2116 }});
2117 }
2118 }
2119 }
2120 }
2121
2122 0x3: decode FUNCTION_LO {
2123
2124 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field
2125 //(DSP ASE Rev2 Manual)
2126 0x0: decode OP_HI {
2127 0x0: decode OP_LO {
2128 format DspIntOp {
2129 0x0: adduh_qb({{
2144 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2145 NOROUND, UNSIGNED);
2130 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2131 NOROUND, UNSIGNED);
2146 }});
2147 0x1: subuh_qb({{
2132 }});
2133 0x1: subuh_qb({{
2148 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2149 NOROUND, UNSIGNED);
2134 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2135 NOROUND, UNSIGNED);
2150 }});
2151 0x2: adduh_r_qb({{
2136 }});
2137 0x2: adduh_r_qb({{
2152 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2153 ROUND, UNSIGNED);
2138 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2139 ROUND, UNSIGNED);
2154 }});
2155 0x3: subuh_r_qb({{
2140 }});
2141 0x3: subuh_r_qb({{
2156 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2157 ROUND, UNSIGNED);
2142 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2143 ROUND, UNSIGNED);
2158 }});
2159 }
2160 }
2161 0x1: decode OP_LO {
2162 format DspIntOp {
2163 0x0: addqh_ph({{
2144 }});
2145 }
2146 }
2147 0x1: decode OP_LO {
2148 format DspIntOp {
2149 0x0: addqh_ph({{
2164 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2165 NOROUND, SIGNED);
2150 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2151 NOROUND, SIGNED);
2166 }});
2167 0x1: subqh_ph({{
2152 }});
2153 0x1: subqh_ph({{
2168 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2169 NOROUND, SIGNED);
2154 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2155 NOROUND, SIGNED);
2170 }});
2171 0x2: addqh_r_ph({{
2156 }});
2157 0x2: addqh_r_ph({{
2172 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2173 ROUND, SIGNED);
2158 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2159 ROUND, SIGNED);
2174 }});
2175 0x3: subqh_r_ph({{
2160 }});
2161 0x3: subqh_r_ph({{
2176 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2177 ROUND, SIGNED);
2162 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2163 ROUND, SIGNED);
2178 }});
2179 0x4: mul_ph({{
2164 }});
2165 0x4: mul_ph({{
2180 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH,
2181 NOSATURATE, &dspctl);
2166 Rd = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH,
2167 NOSATURATE, &dspctl);
2182 }}, IntMultOp);
2183 0x6: mul_s_ph({{
2168 }}, IntMultOp);
2169 0x6: mul_s_ph({{
2184 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH,
2185 SATURATE, &dspctl);
2170 Rd = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH,
2171 SATURATE, &dspctl);
2186 }}, IntMultOp);
2187 }
2188 }
2189 0x2: decode OP_LO {
2190 format DspIntOp {
2191 0x0: addqh_w({{
2172 }}, IntMultOp);
2173 }
2174 }
2175 0x2: decode OP_LO {
2176 format DspIntOp {
2177 0x0: addqh_w({{
2192 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W,
2193 NOROUND, SIGNED);
2178 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W,
2179 NOROUND, SIGNED);
2194 }});
2195 0x1: subqh_w({{
2180 }});
2181 0x1: subqh_w({{
2196 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W,
2197 NOROUND, SIGNED);
2182 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W,
2183 NOROUND, SIGNED);
2198 }});
2199 0x2: addqh_r_w({{
2184 }});
2185 0x2: addqh_r_w({{
2200 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W,
2201 ROUND, SIGNED);
2186 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W,
2187 ROUND, SIGNED);
2202 }});
2203 0x3: subqh_r_w({{
2188 }});
2189 0x3: subqh_r_w({{
2204 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W,
2205 ROUND, SIGNED);
2190 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W,
2191 ROUND, SIGNED);
2206 }});
2207 0x6: mulq_s_w({{
2192 }});
2193 0x6: mulq_s_w({{
2208 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W,
2209 SATURATE, NOROUND, &dspctl);
2194 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W,
2195 SATURATE, NOROUND, &dspctl);
2210 }}, IntMultOp);
2211 0x7: mulq_rs_w({{
2196 }}, IntMultOp);
2197 0x7: mulq_rs_w({{
2212 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W,
2213 SATURATE, ROUND, &dspctl);
2198 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W,
2199 SATURATE, ROUND, &dspctl);
2214 }}, IntMultOp);
2215 }
2216 }
2217 }
2218 }
2219
2220 //Table A-10 MIPS32 BSHFL Encoding of sa Field
2221 0x4: decode SA {
2222 format BasicOp {
2223 0x02: wsbh({{
2200 }}, IntMultOp);
2201 }
2202 }
2203 }
2204 }
2205
2206 //Table A-10 MIPS32 BSHFL Encoding of sa Field
2207 0x4: decode SA {
2208 format BasicOp {
2209 0x02: wsbh({{
2224 Rd_uw = Rt_uw<23:16> << 24 |
2225 Rt_uw<31:24> << 16 |
2226 Rt_uw<7:0> << 8 |
2227 Rt_uw<15:8>;
2210 Rd = Rt<23:16> << 24 | Rt<31:24> << 16 |
2211 Rt<7:0> << 8 | Rt<15:8>;
2228 }});
2212 }});
2229 0x10: seb({{ Rd_sw = Rt_sb; }});
2230 0x18: seh({{ Rd_sw = Rt_sh; }});
2213 0x10: seb({{ Rd = Rt_sb; }});
2214 0x18: seh({{ Rd = Rt_sh; }});
2231 }
2232 }
2233
2234 0x6: decode FUNCTION_LO {
2235
2236 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field
2237 //(DSP ASE MANUAL)
2238 0x0: decode OP_HI {

--- 68 unchanged lines hidden (view full) ---

2307 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2308 SIMD_FMT_QB, UNSIGNED, MODE_R);
2309 }}, IntMultOp);
2310 }
2311 }
2312 0x2: decode OP_LO {
2313 format DspHiLoOp {
2314 0x0: maq_sa_w_phl({{
2215 }
2216 }
2217
2218 0x6: decode FUNCTION_LO {
2219
2220 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field
2221 //(DSP ASE MANUAL)
2222 0x0: decode OP_HI {

--- 68 unchanged lines hidden (view full) ---

2291 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2292 SIMD_FMT_QB, UNSIGNED, MODE_R);
2293 }}, IntMultOp);
2294 }
2295 }
2296 0x2: decode OP_LO {
2297 format DspHiLoOp {
2298 0x0: maq_sa_w_phl({{
2315 dspac = dspMaq(dspac, Rs_uw, Rt_uw,
2299 dspac = dspMaq(dspac, Rs, Rt,
2316 ACDST, SIMD_FMT_PH,
2317 MODE_L, SATURATE, &dspctl);
2318 }}, IntMultOp);
2319 0x2: maq_sa_w_phr({{
2300 ACDST, SIMD_FMT_PH,
2301 MODE_L, SATURATE, &dspctl);
2302 }}, IntMultOp);
2303 0x2: maq_sa_w_phr({{
2320 dspac = dspMaq(dspac, Rs_uw, Rt_uw,
2304 dspac = dspMaq(dspac, Rs, Rt,
2321 ACDST, SIMD_FMT_PH,
2322 MODE_R, SATURATE, &dspctl);
2323 }}, IntMultOp);
2324 0x4: maq_s_w_phl({{
2305 ACDST, SIMD_FMT_PH,
2306 MODE_R, SATURATE, &dspctl);
2307 }}, IntMultOp);
2308 0x4: maq_s_w_phl({{
2325 dspac = dspMaq(dspac, Rs_uw, Rt_uw,
2309 dspac = dspMaq(dspac, Rs, Rt,
2326 ACDST, SIMD_FMT_PH,
2327 MODE_L, NOSATURATE, &dspctl);
2328 }}, IntMultOp);
2329 0x6: maq_s_w_phr({{
2310 ACDST, SIMD_FMT_PH,
2311 MODE_L, NOSATURATE, &dspctl);
2312 }}, IntMultOp);
2313 0x6: maq_s_w_phr({{
2330 dspac = dspMaq(dspac, Rs_uw, Rt_uw,
2314 dspac = dspMaq(dspac, Rs, Rt,
2331 ACDST, SIMD_FMT_PH,
2332 MODE_R, NOSATURATE, &dspctl);
2333 }}, IntMultOp);
2334 }
2335 }
2336 0x3: decode OP_LO {
2337 format DspHiLoOp {
2338 0x0: dpaqx_s_w_ph({{

--- 24 unchanged lines hidden (view full) ---

2363 }
2364 }
2365
2366 //Table 3.3 MIPS32 APPEND Encoding of the op Field
2367 0x1: decode OP_HI {
2368 0x0: decode OP_LO {
2369 format IntOp {
2370 0x0: append({{
2315 ACDST, SIMD_FMT_PH,
2316 MODE_R, NOSATURATE, &dspctl);
2317 }}, IntMultOp);
2318 }
2319 }
2320 0x3: decode OP_LO {
2321 format DspHiLoOp {
2322 0x0: dpaqx_s_w_ph({{

--- 24 unchanged lines hidden (view full) ---

2347 }
2348 }
2349
2350 //Table 3.3 MIPS32 APPEND Encoding of the op Field
2351 0x1: decode OP_HI {
2352 0x0: decode OP_LO {
2353 format IntOp {
2354 0x0: append({{
2371 Rt_uw = (Rt_uw << RD) | bits(Rs_uw, RD - 1, 0);
2355 Rt = (Rt << RD) | bits(Rs, RD - 1, 0);
2372 }});
2373 0x1: prepend({{
2356 }});
2357 0x1: prepend({{
2374 Rt_uw = (Rt_uw >> RD) |
2375 (bits(Rs_uw, RD - 1, 0) << (32 - RD));
2358 Rt = (Rt >> RD) |
2359 (bits(Rs, RD - 1, 0) << (32 - RD));
2376 }});
2377 }
2378 }
2379 0x2: decode OP_LO {
2380 format IntOp {
2381 0x0: balign({{
2360 }});
2361 }
2362 }
2363 0x2: decode OP_LO {
2364 format IntOp {
2365 0x0: balign({{
2382 Rt_uw = (Rt_uw << (8 * BP)) |
2383 (Rs_uw >> (8 * (4 - BP)));
2366 Rt = (Rt << (8 * BP)) | (Rs >> (8 * (4 - BP)));
2384 }});
2385 }
2386 }
2387 }
2388
2389 }
2390 0x7: decode FUNCTION_LO {
2391
2392 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field
2393 //(DSP ASE MANUAL)
2394 0x0: decode OP_HI {
2395 0x0: decode OP_LO {
2396 format DspHiLoOp {
2397 0x0: extr_w({{
2367 }});
2368 }
2369 }
2370 }
2371
2372 }
2373 0x7: decode FUNCTION_LO {
2374
2375 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field
2376 //(DSP ASE MANUAL)
2377 0x0: decode OP_HI {
2378 0x0: decode OP_LO {
2379 format DspHiLoOp {
2380 0x0: extr_w({{
2398 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS,
2399 NOROUND, NOSATURATE, &dspctl);
2381 Rt = dspExtr(dspac, SIMD_FMT_W, RS,
2382 NOROUND, NOSATURATE, &dspctl);
2400 }});
2401 0x1: extrv_w({{
2383 }});
2384 0x1: extrv_w({{
2402 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw,
2403 NOROUND, NOSATURATE, &dspctl);
2385 Rt = dspExtr(dspac, SIMD_FMT_W, Rs,
2386 NOROUND, NOSATURATE, &dspctl);
2404 }});
2405 0x2: extp({{
2387 }});
2388 0x2: extp({{
2406 Rt_uw = dspExtp(dspac, RS, &dspctl);
2389 Rt = dspExtp(dspac, RS, &dspctl);
2407 }});
2408 0x3: extpv({{
2390 }});
2391 0x3: extpv({{
2409 Rt_uw = dspExtp(dspac, Rs_uw, &dspctl);
2392 Rt = dspExtp(dspac, Rs, &dspctl);
2410 }});
2411 0x4: extr_r_w({{
2393 }});
2394 0x4: extr_r_w({{
2412 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS,
2413 ROUND, NOSATURATE, &dspctl);
2395 Rt = dspExtr(dspac, SIMD_FMT_W, RS,
2396 ROUND, NOSATURATE, &dspctl);
2414 }});
2415 0x5: extrv_r_w({{
2397 }});
2398 0x5: extrv_r_w({{
2416 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw,
2417 ROUND, NOSATURATE, &dspctl);
2399 Rt = dspExtr(dspac, SIMD_FMT_W, Rs,
2400 ROUND, NOSATURATE, &dspctl);
2418 }});
2419 0x6: extr_rs_w({{
2401 }});
2402 0x6: extr_rs_w({{
2420 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS,
2421 ROUND, SATURATE, &dspctl);
2403 Rt = dspExtr(dspac, SIMD_FMT_W, RS,
2404 ROUND, SATURATE, &dspctl);
2422 }});
2423 0x7: extrv_rs_w({{
2405 }});
2406 0x7: extrv_rs_w({{
2424 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw,
2425 ROUND, SATURATE, &dspctl);
2407 Rt = dspExtr(dspac, SIMD_FMT_W, Rs,
2408 ROUND, SATURATE, &dspctl);
2426 }});
2427 }
2428 }
2429 0x1: decode OP_LO {
2430 format DspHiLoOp {
2431 0x2: extpdp({{
2409 }});
2410 }
2411 }
2412 0x1: decode OP_LO {
2413 format DspHiLoOp {
2414 0x2: extpdp({{
2432 Rt_uw = dspExtpd(dspac, RS, &dspctl);
2415 Rt = dspExtpd(dspac, RS, &dspctl);
2433 }});
2434 0x3: extpdpv({{
2416 }});
2417 0x3: extpdpv({{
2435 Rt_uw = dspExtpd(dspac, Rs_uw, &dspctl);
2418 Rt = dspExtpd(dspac, Rs, &dspctl);
2436 }});
2437 0x6: extr_s_h({{
2419 }});
2420 0x6: extr_s_h({{
2438 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, RS,
2439 NOROUND, SATURATE, &dspctl);
2421 Rt = dspExtr(dspac, SIMD_FMT_PH, RS,
2422 NOROUND, SATURATE, &dspctl);
2440 }});
2441 0x7: extrv_s_h({{
2423 }});
2424 0x7: extrv_s_h({{
2442 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, Rs_uw,
2443 NOROUND, SATURATE, &dspctl);
2425 Rt = dspExtr(dspac, SIMD_FMT_PH, Rs,
2426 NOROUND, SATURATE, &dspctl);
2444 }});
2445 }
2446 }
2447 0x2: decode OP_LO {
2448 format DspIntOp {
2449 0x2: rddsp({{
2427 }});
2428 }
2429 }
2430 0x2: decode OP_LO {
2431 format DspIntOp {
2432 0x2: rddsp({{
2450 Rd_uw = readDSPControl(&dspctl, RDDSPMASK);
2433 Rd = readDSPControl(&dspctl, RDDSPMASK);
2451 }});
2452 0x3: wrdsp({{
2434 }});
2435 0x3: wrdsp({{
2453 writeDSPControl(&dspctl, Rs_uw, WRDSPMASK);
2436 writeDSPControl(&dspctl, Rs, WRDSPMASK);
2454 }});
2455 }
2456 }
2457 0x3: decode OP_LO {
2458 format DspHiLoOp {
2459 0x2: shilo({{
2460 if ((int64_t)sext<6>(HILOSA) < 0) {
2461 dspac = (uint64_t)dspac <<

--- 9 unchanged lines hidden (view full) ---

2471 -sext<6>(Rs_sw<5:0>);
2472 } else {
2473 dspac = (uint64_t)dspac >>
2474 sext<6>(Rs_sw<5:0>);
2475 }
2476 }});
2477 0x7: mthlip({{
2478 dspac = dspac << 32;
2437 }});
2438 }
2439 }
2440 0x3: decode OP_LO {
2441 format DspHiLoOp {
2442 0x2: shilo({{
2443 if ((int64_t)sext<6>(HILOSA) < 0) {
2444 dspac = (uint64_t)dspac <<

--- 9 unchanged lines hidden (view full) ---

2454 -sext<6>(Rs_sw<5:0>);
2455 } else {
2456 dspac = (uint64_t)dspac >>
2457 sext<6>(Rs_sw<5:0>);
2458 }
2459 }});
2460 0x7: mthlip({{
2461 dspac = dspac << 32;
2479 dspac |= Rs_uw;
2462 dspac |= Rs;
2480 dspctl = insertBits(dspctl, 5, 0,
2481 dspctl<5:0> + 32);
2482 }});
2483 }
2484 }
2485 }
2486 0x3: decode OP default FailUnimpl::rdhwr() {
2487 0x0: decode FullSystemInt {
2488 0: decode RD {
2489 29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
2490 }
2491 }
2492 }
2493 }
2494 }
2495 }
2496
2497 0x4: decode OPCODE_LO {
2498 format LoadMemory {
2463 dspctl = insertBits(dspctl, 5, 0,
2464 dspctl<5:0> + 32);
2465 }});
2466 }
2467 }
2468 }
2469 0x3: decode OP default FailUnimpl::rdhwr() {
2470 0x0: decode FullSystemInt {
2471 0: decode RD {
2472 29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
2473 }
2474 }
2475 }
2476 }
2477 }
2478 }
2479
2480 0x4: decode OPCODE_LO {
2481 format LoadMemory {
2499 0x0: lb({{ Rt_sw = Mem_sb; }});
2500 0x1: lh({{ Rt_sw = Mem_sh; }});
2501 0x3: lw({{ Rt_sw = Mem_sw; }});
2502 0x4: lbu({{ Rt_uw = Mem_ub;}});
2503 0x5: lhu({{ Rt_uw = Mem_uh; }});
2482 0x0: lb({{ Rt = Mem_sb; }});
2483 0x1: lh({{ Rt = Mem_sh; }});
2484 0x3: lw({{ Rt = Mem_sw; }});
2485 0x4: lbu({{ Rt = Mem_ub;}});
2486 0x5: lhu({{ Rt = Mem_uh; }});
2504 }
2505
2506 format LoadUnalignedMemory {
2507 0x2: lwl({{
2508 uint32_t mem_shift = 24 - (8 * byte_offset);
2487 }
2488
2489 format LoadUnalignedMemory {
2490 0x2: lwl({{
2491 uint32_t mem_shift = 24 - (8 * byte_offset);
2509 Rt_uw = mem_word << mem_shift | (Rt_uw & mask(mem_shift));
2492 Rt = mem_word << mem_shift | (Rt & mask(mem_shift));
2510 }});
2511 0x6: lwr({{
2512 uint32_t mem_shift = 8 * byte_offset;
2493 }});
2494 0x6: lwr({{
2495 uint32_t mem_shift = 8 * byte_offset;
2513 Rt_uw = (Rt_uw & (mask(mem_shift) << (32 - mem_shift))) |
2496 Rt = (Rt & (mask(mem_shift) << (32 - mem_shift))) |
2514 (mem_word >> mem_shift);
2515 }});
2516 }
2517 }
2518
2519 0x5: decode OPCODE_LO {
2520 format StoreMemory {
2521 0x0: sb({{ Mem_ub = Rt<7:0>; }});
2522 0x1: sh({{ Mem_uh = Rt<15:0>; }});
2497 (mem_word >> mem_shift);
2498 }});
2499 }
2500 }
2501
2502 0x5: decode OPCODE_LO {
2503 format StoreMemory {
2504 0x0: sb({{ Mem_ub = Rt<7:0>; }});
2505 0x1: sh({{ Mem_uh = Rt<15:0>; }});
2523 0x3: sw({{ Mem_uw = Rt<31:0>; }});
2506 0x3: sw({{ Mem = Rt<31:0>; }});
2524 }
2525
2526 format StoreUnalignedMemory {
2527 0x2: swl({{
2528 uint32_t reg_shift = 24 - (8 * byte_offset);
2529 uint32_t mem_shift = 32 - reg_shift;
2530 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |
2507 }
2508
2509 format StoreUnalignedMemory {
2510 0x2: swl({{
2511 uint32_t reg_shift = 24 - (8 * byte_offset);
2512 uint32_t mem_shift = 32 - reg_shift;
2513 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |
2531 (Rt_uw >> reg_shift);
2514 (Rt >> reg_shift);
2532 }});
2533 0x6: swr({{
2534 uint32_t reg_shift = 8 * byte_offset;
2515 }});
2516 0x6: swr({{
2517 uint32_t reg_shift = 8 * byte_offset;
2535 mem_word = Rt_uw << reg_shift |
2518 mem_word = Rt << reg_shift |
2536 (mem_word & (mask(reg_shift)));
2537 }});
2538 }
2539 format CP0Control {
2540 0x7: cache({{
2519 (mem_word & (mask(reg_shift)));
2520 }});
2521 }
2522 format CP0Control {
2523 0x7: cache({{
2541 //Addr CacheEA = Rs_uw + OFFSET;
2524 //Addr CacheEA = Rs + OFFSET;
2542 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
2543 }});
2544 }
2545 }
2546
2547 0x6: decode OPCODE_LO {
2548 format LoadMemory {
2525 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
2526 }});
2527 }
2528 }
2529
2530 0x6: decode OPCODE_LO {
2531 format LoadMemory {
2549 0x0: ll({{ Rt_uw = Mem_uw; }}, mem_flags=LLSC);
2550 0x1: lwc1({{ Ft_uw = Mem_uw; }});
2532 0x0: ll({{ Rt = Mem; }}, mem_flags=LLSC);
2533 0x1: lwc1({{ Ft_uw = Mem; }});
2551 0x5: ldc1({{ Ft_ud = Mem_ud; }});
2552 }
2553 0x2: CP2Unimpl::lwc2();
2554 0x6: CP2Unimpl::ldc2();
2555 0x3: Prefetch::pref();
2556 }
2557
2558
2559 0x7: decode OPCODE_LO {
2534 0x5: ldc1({{ Ft_ud = Mem_ud; }});
2535 }
2536 0x2: CP2Unimpl::lwc2();
2537 0x6: CP2Unimpl::ldc2();
2538 0x3: Prefetch::pref();
2539 }
2540
2541
2542 0x7: decode OPCODE_LO {
2560 0x0: StoreCond::sc({{ Mem_uw = Rt_uw; }},
2543 0x0: StoreCond::sc({{ Mem = Rt; }},
2561 {{ uint64_t tmp = write_result;
2544 {{ uint64_t tmp = write_result;
2562 Rt_uw = (tmp == 0 || tmp == 1) ? tmp : Rt_uw;
2545 Rt = (tmp == 0 || tmp == 1) ? tmp : Rt;
2563 }}, mem_flags=LLSC,
2564 inst_flags = IsStoreConditional);
2565 format StoreMemory {
2546 }}, mem_flags=LLSC,
2547 inst_flags = IsStoreConditional);
2548 format StoreMemory {
2566 0x1: swc1({{ Mem_uw = Ft_uw; }});
2549 0x1: swc1({{ Mem = Ft_uw; }});
2567 0x5: sdc1({{ Mem_ud = Ft_ud; }});
2568 }
2569 0x2: CP2Unimpl::swc2();
2570 0x6: CP2Unimpl::sdc2();
2571 }
2572}
2573
2574
2550 0x5: sdc1({{ Mem_ud = Ft_ud; }});
2551 }
2552 0x2: CP2Unimpl::swc2();
2553 0x6: CP2Unimpl::sdc2();
2554 }
2555}
2556
2557