decoder.isa (11294:a368064a2ab5) decoder.isa (11320:42ecb523c64a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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354 Rt = CP0_RD_SEL;
355 /* Hack for PageMask */
356 if (RD == 5) {
357 // PageMask
358 if (config3.sp == 0 || pageGrain.esp == 0)
359 Rt &= 0xFFFFE7FF;
360 }
361 }});
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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354 Rt = CP0_RD_SEL;
355 /* Hack for PageMask */
356 if (RD == 5) {
357 // PageMask
358 if (config3.sp == 0 || pageGrain.esp == 0)
359 Rt &= 0xFFFFE7FF;
360 }
361 }});
362 0x4: mtc0({{
362 0x4: mtc0({{
363 CP0_RD_SEL = Rt;
364 CauseReg cause = Cause;
365 IntCtlReg intCtl = IntCtl;
366 if (RD == 11) {
367 // Compare
368 if (cause.ti == 1) {
369 cause.ti = 0;
370 int offset = 10; // corresponding to cause.ip0

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1233 }
1234 }
1235 default: CP1Unimpl::unknown();
1236 }
1237 0x2: CP1Unimpl::unknown();
1238 0x3: CP1Unimpl::unknown();
1239 0x7: CP1Unimpl::unknown();
1240
363 CP0_RD_SEL = Rt;
364 CauseReg cause = Cause;
365 IntCtlReg intCtl = IntCtl;
366 if (RD == 11) {
367 // Compare
368 if (cause.ti == 1) {
369 cause.ti = 0;
370 int offset = 10; // corresponding to cause.ip0

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1233 }
1234 }
1235 default: CP1Unimpl::unknown();
1236 }
1237 0x2: CP1Unimpl::unknown();
1238 0x3: CP1Unimpl::unknown();
1239 0x7: CP1Unimpl::unknown();
1240
1241 //Table A-16 MIPS32 COP1 Encoding of Function
1241 //Table A-16 MIPS32 COP1 Encoding of Function
1242 //Field When rs=W
1243 0x4: decode FUNCTION {
1244 format FloatConvertOp {
1245 0x20: cvt_s_w({{ val = Fs_sw; }}, ToSingle);
1246 0x21: cvt_d_w({{ val = Fs_sw; }}, ToDouble);
1247 0x26: CP1Unimpl::cvt_ps_w();
1248 }
1249 default: CP1Unimpl::unknown();

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1862 UNSIGNED, CMP_LE, &dspctl);
1863 }});
1864 0x6: precr_sra_ph_w({{
1865 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
1866 SIMD_FMT_W, NOROUND);
1867 }});
1868 0x7: precr_sra_r_ph_w({{
1869 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
1242 //Field When rs=W
1243 0x4: decode FUNCTION {
1244 format FloatConvertOp {
1245 0x20: cvt_s_w({{ val = Fs_sw; }}, ToSingle);
1246 0x21: cvt_d_w({{ val = Fs_sw; }}, ToDouble);
1247 0x26: CP1Unimpl::cvt_ps_w();
1248 }
1249 default: CP1Unimpl::unknown();

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1862 UNSIGNED, CMP_LE, &dspctl);
1863 }});
1864 0x6: precr_sra_ph_w({{
1865 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
1866 SIMD_FMT_W, NOROUND);
1867 }});
1868 0x7: precr_sra_r_ph_w({{
1869 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
1870 SIMD_FMT_W, ROUND);
1870 SIMD_FMT_W, ROUND);
1871 }});
1872 }
1873 }
1874 }
1875
1876 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field
1877 //(DSP ASE MANUAL)
1878 0x2: decode OP_HI {

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1872 }
1873 }
1874 }
1875
1876 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field
1877 //(DSP ASE MANUAL)
1878 0x2: decode OP_HI {

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