1259 format FloatConvertOp { 1260 0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle); 1261 0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble); 1262 0x26: CP1Unimpl::cvt_ps_l(); 1263 } 1264 default: CP1Unimpl::unknown(); 1265 } 1266 1267 //Table A-17 MIPS64 COP1 Encoding of Function Field 1268 //When rs=PS1 1269 //Note: "1. Format type PS is legal only if 64-bit 1270 //floating point operations are enabled. " 1271 0x6: decode FUNCTION_HI { 1272 0x0: decode FUNCTION_LO { 1273 format Float64Op { 1274 0x0: add_ps({{ 1275 Fd1_sf = Fs1_sf + Ft2_sf; 1276 Fd2_sf = Fs2_sf + Ft2_sf; 1277 }}); 1278 0x1: sub_ps({{ 1279 Fd1_sf = Fs1_sf - Ft2_sf; 1280 Fd2_sf = Fs2_sf - Ft2_sf; 1281 }}); 1282 0x2: mul_ps({{ 1283 Fd1_sf = Fs1_sf * Ft2_sf; 1284 Fd2_sf = Fs2_sf * Ft2_sf; 1285 }}); 1286 0x5: abs_ps({{ 1287 Fd1_sf = fabs(Fs1_sf); 1288 Fd2_sf = fabs(Fs2_sf); 1289 }}); 1290 0x6: mov_ps({{ 1291 Fd1_sf = Fs1_sf; 1292 Fd2_sf = Fs2_sf; 1293 }}); 1294 0x7: neg_ps({{ 1295 Fd1_sf = -(Fs1_sf); 1296 Fd2_sf = -(Fs2_sf); 1297 }}); 1298 default: CP1Unimpl::unknown(); 1299 } 1300 } 1301 0x1: CP1Unimpl::unknown(); 1302 0x2: decode FUNCTION_LO { 1303 0x1: decode MOVCF { 1304 format Float64Op { 1305 0x0: movf_ps({{ 1306 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1307 Fs1 : Fd1; 1308 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1309 Fs2 : Fd2; 1310 }}); 1311 0x1: movt_ps({{ 1312 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1313 Fs1 : Fd1; 1314 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1315 Fs2 : Fd2; 1316 }}); 1317 } 1318 } 1319 1320 format Float64Op { 1321 0x2: movz_ps({{ 1322 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1323 Fs1 : Fd1; 1324 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1325 Fs2 : Fd2; 1326 }}); 1327 0x3: movn_ps({{ 1328 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1329 Fs1 : Fd1; 1330 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1331 Fs2 : Fd2; 1332 }}); 1333 } 1334 default: CP1Unimpl::unknown(); 1335 } 1336 0x3: CP1Unimpl::unknown(); 1337 0x4: decode FUNCTION_LO { 1338 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }}); 1339 default: CP1Unimpl::unknown(); 1340 } 1341 1342 0x5: decode FUNCTION_LO { 1343 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }}); 1344 format Float64Op { 1345 0x4: pll({{ 1346 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw; 1347 }}); 1348 0x5: plu({{ 1349 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw; 1350 }}); 1351 0x6: pul({{ 1352 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw; 1353 }}); 1354 0x7: puu({{ 1355 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw; 1356 }}); 1357 } 1358 default: CP1Unimpl::unknown(); 1359 } 1360 1361 0x6: decode FUNCTION_LO { 1362 format FloatPSCompareOp { 1363 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1364 UnorderedFalse); 1365 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1366 UnorderedTrue); 1367 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1368 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1369 UnorderedFalse); 1370 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1371 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1372 UnorderedTrue); 1373 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1374 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1375 UnorderedFalse); 1376 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }}, 1377 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1378 UnorderedTrue); 1379 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }}, 1380 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1381 UnorderedFalse); 1382 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1383 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1384 UnorderedTrue); 1385 } 1386 } 1387 1388 0x7: decode FUNCTION_LO { 1389 format FloatPSCompareOp { 1390 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1391 UnorderedFalse, QnanException); 1392 0x1: c_ngle_ps({{ cond1 = 0; }}, 1393 {{ cond2 = 0; }}, 1394 UnorderedTrue, QnanException); 1395 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1396 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1397 UnorderedFalse, QnanException); 1398 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1399 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1400 UnorderedTrue, QnanException); 1401 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1402 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1403 UnorderedFalse, QnanException); 1404 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1405 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1406 UnorderedTrue, QnanException); 1407 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1408 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1409 UnorderedFalse, QnanException); 1410 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1411 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1412 UnorderedTrue, QnanException); 1413 } 1414 } 1415 } 1416 } 1417 default: CP1Unimpl::unknown(); 1418 } 1419 } 1420 1421 //Table A-19 MIPS32 COP2 Encoding of rs Field 1422 0x2: decode RS_MSB { 1423 format CP2Unimpl { 1424 0x0: decode RS_HI { 1425 0x0: decode RS_LO { 1426 0x0: mfc2(); 1427 0x2: cfc2(); 1428 0x3: mfhc2(); 1429 0x4: mtc2(); 1430 0x6: ctc2(); 1431 0x7: mftc2(); 1432 default: unknown(); 1433 } 1434 1435 0x1: decode ND { 1436 0x0: decode TF { 1437 0x0: bc2f(); 1438 0x1: bc2t(); 1439 default: unknown(); 1440 } 1441 1442 0x1: decode TF { 1443 0x0: bc2fl(); 1444 0x1: bc2tl(); 1445 default: unknown(); 1446 } 1447 default: unknown(); 1448 1449 } 1450 default: unknown(); 1451 } 1452 default: unknown(); 1453 } 1454 } 1455 1456 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1457 //Note: "COP1X instructions are legal only if 64-bit floating point 1458 //operations are enabled." 1459 0x3: decode FUNCTION_HI { 1460 0x0: decode FUNCTION_LO { 1461 format LoadIndexedMemory { 1462 0x0: lwxc1({{ Fd_uw = Mem_uw; }}); 1463 0x1: ldxc1({{ Fd_ud = Mem_ud; }}); 1464 0x5: luxc1({{ Fd_ud = Mem_ud; }}, 1465 {{ EA = (Rs + Rt) & ~7; }}); 1466 } 1467 } 1468 1469 0x1: decode FUNCTION_LO { 1470 format StoreIndexedMemory { 1471 0x0: swxc1({{ Mem_uw = Fs_uw; }}); 1472 0x1: sdxc1({{ Mem_ud = Fs_ud; }}); 1473 0x5: suxc1({{ Mem_ud = Fs_ud; }}, 1474 {{ EA = (Rs + Rt) & ~7; }}); 1475 } 1476 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1477 } 1478 1479 0x3: decode FUNCTION_LO { 1480 0x6: Float64Op::alnv_ps({{ 1481 if (Rs<2:0> == 0) { 1482 Fd_ud = Fs_ud; 1483 } else if (Rs<2:0> == 4) { 1484 if (GuestByteOrder == BigEndianByteOrder) 1485 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; 1486 else 1487 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; 1488 } else { 1489 Fd_ud = Fd_ud; 1490 } 1491 }}); 1492 } 1493 1494 format FloatAccOp { 1495 0x4: decode FUNCTION_LO { 1496 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }}); 1497 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }}); 1498 0x6: madd_ps({{ 1499 Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df; 1500 Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df; 1501 }}); 1502 } 1503 1504 0x5: decode FUNCTION_LO { 1505 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }}); 1506 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }}); 1507 0x6: msub_ps({{ 1508 Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df; 1509 Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df; 1510 }}); 1511 } 1512 1513 0x6: decode FUNCTION_LO { 1514 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }}); 1515 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }}); 1516 0x6: nmadd_ps({{ 1517 Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df); 1518 Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df); 1519 }}); 1520 } 1521 1522 0x7: decode FUNCTION_LO { 1523 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }}); 1524 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }}); 1525 0x6: nmsub_ps({{ 1526 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df); 1527 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df); 1528 }}); 1529 } 1530 } 1531 } 1532 1533 format Branch { 1534 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely); 1535 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely); 1536 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely); 1537 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely); 1538 } 1539 } 1540 1541 0x3: decode OPCODE_LO { 1542 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1543 0x4: decode FUNCTION_HI { 1544 0x0: decode FUNCTION_LO { 1545 0x2: IntOp::mul({{ 1546 int64_t temp1 = Rs_sd * Rt_sd; 1547 Rd_sw = temp1<31:0>; 1548 }}, IntMultOp); 1549 1550 format HiLoRdSelValOp { 1551 0x0: madd({{ 1552 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1553 (Rs_sd * Rt_sd); 1554 }}, IntMultOp); 1555 0x1: maddu({{ 1556 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1557 (Rs_ud * Rt_ud); 1558 }}, IntMultOp); 1559 0x4: msub({{ 1560 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1561 (Rs_sd * Rt_sd); 1562 }}, IntMultOp); 1563 0x5: msubu({{ 1564 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1565 (Rs_ud * Rt_ud); 1566 }}, IntMultOp); 1567 } 1568 } 1569 1570 0x4: decode FUNCTION_LO { 1571 format BasicOp { 1572 0x0: clz({{ 1573 int cnt = 32; 1574 for (int idx = 31; idx >= 0; idx--) { 1575 if (Rs<idx:idx> == 1) { 1576 cnt = 31 - idx; 1577 break; 1578 } 1579 } 1580 Rd_uw = cnt; 1581 }}); 1582 0x1: clo({{ 1583 int cnt = 32; 1584 for (int idx = 31; idx >= 0; idx--) { 1585 if (Rs<idx:idx> == 0) { 1586 cnt = 31 - idx; 1587 break; 1588 } 1589 } 1590 Rd_uw = cnt; 1591 }}); 1592 } 1593 } 1594 1595 0x7: decode FUNCTION_LO { 1596 0x7: FailUnimpl::sdbbp(); 1597 } 1598 } 1599 1600 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1601 //of the Architecture 1602 0x7: decode FUNCTION_HI { 1603 0x0: decode FUNCTION_LO { 1604 format BasicOp { 1605 0x0: ext({{ Rt_uw = bits(Rs_uw, MSB+LSB, LSB); }}); 1606 0x4: ins({{ 1607 Rt_uw = bits(Rt_uw, 31, MSB+1) << (MSB+1) | 1608 bits(Rs_uw, MSB-LSB, 0) << LSB | 1609 bits(Rt_uw, LSB-1, 0); 1610 }}); 1611 } 1612 } 1613 1614 0x1: decode FUNCTION_LO { 1615 format MT_Control { 1616 0x0: fork({{ 1617 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1618 }}, UserMode); 1619 0x1: yield({{ 1620 Rd_sw = yieldThread(xc->tcBase(), fault, Rs_sw, 1621 YQMask); 1622 }}, UserMode); 1623 } 1624 1625 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1626 0x2: decode OP_HI { 1627 0x0: decode OP_LO { 1628 format LoadIndexedMemory { 1629 0x0: lwx({{ Rd_sw = Mem_sw; }}); 1630 0x4: lhx({{ Rd_sw = Mem_sh; }}); 1631 0x6: lbux({{ Rd_uw = Mem_ub; }}); 1632 } 1633 } 1634 } 1635 0x4: DspIntOp::insv({{ 1636 int pos = dspctl<5:0>; 1637 int size = dspctl<12:7> - 1; 1638 Rt_uw = insertBits(Rt_uw, pos+size, 1639 pos, Rs_uw<size:0>); 1640 }}); 1641 } 1642 1643 0x2: decode FUNCTION_LO { 1644 1645 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1646 //(DSP ASE MANUAL) 1647 0x0: decode OP_HI { 1648 0x0: decode OP_LO { 1649 format DspIntOp { 1650 0x0: addu_qb({{ 1651 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1652 NOSATURATE, UNSIGNED, &dspctl); 1653 }}); 1654 0x1: subu_qb({{ 1655 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1656 NOSATURATE, UNSIGNED, &dspctl); 1657 }}); 1658 0x4: addu_s_qb({{ 1659 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1660 SATURATE, UNSIGNED, &dspctl); 1661 }}); 1662 0x5: subu_s_qb({{ 1663 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1664 SATURATE, UNSIGNED, &dspctl); 1665 }}); 1666 0x6: muleu_s_ph_qbl({{ 1667 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1668 MODE_L, &dspctl); 1669 }}, IntMultOp); 1670 0x7: muleu_s_ph_qbr({{ 1671 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1672 MODE_R, &dspctl); 1673 }}, IntMultOp); 1674 } 1675 } 1676 0x1: decode OP_LO { 1677 format DspIntOp { 1678 0x0: addu_ph({{ 1679 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1680 NOSATURATE, UNSIGNED, &dspctl); 1681 }}); 1682 0x1: subu_ph({{ 1683 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1684 NOSATURATE, UNSIGNED, &dspctl); 1685 }}); 1686 0x2: addq_ph({{ 1687 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1688 NOSATURATE, SIGNED, &dspctl); 1689 }}); 1690 0x3: subq_ph({{ 1691 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1692 NOSATURATE, SIGNED, &dspctl); 1693 }}); 1694 0x4: addu_s_ph({{ 1695 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1696 SATURATE, UNSIGNED, &dspctl); 1697 }}); 1698 0x5: subu_s_ph({{ 1699 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1700 SATURATE, UNSIGNED, &dspctl); 1701 }}); 1702 0x6: addq_s_ph({{ 1703 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1704 SATURATE, SIGNED, &dspctl); 1705 }}); 1706 0x7: subq_s_ph({{ 1707 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1708 SATURATE, SIGNED, &dspctl); 1709 }}); 1710 } 1711 } 1712 0x2: decode OP_LO { 1713 format DspIntOp { 1714 0x0: addsc({{ 1715 int64_t dresult; 1716 dresult = Rs_ud + Rt_ud; 1717 Rd_sw = dresult<31:0>; 1718 dspctl = insertBits(dspctl, 13, 13, 1719 dresult<32:32>); 1720 }}); 1721 0x1: addwc({{ 1722 int64_t dresult; 1723 dresult = Rs_sd + Rt_sd + dspctl<13:13>; 1724 Rd_sw = dresult<31:0>; 1725 if (dresult<32:32> != dresult<31:31>) 1726 dspctl = insertBits(dspctl, 20, 20, 1); 1727 }}); 1728 0x2: modsub({{ 1729 Rd_sw = (Rs_sw == 0) ? Rt_sw<23:8> : 1730 Rs_sw - Rt_sw<7:0>; 1731 }}); 1732 0x4: raddu_w_qb({{ 1733 Rd_uw = Rs_uw<31:24> + Rs_uw<23:16> + 1734 Rs_uw<15:8> + Rs_uw<7:0>; 1735 }}); 1736 0x6: addq_s_w({{ 1737 Rd_sw = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W, 1738 SATURATE, SIGNED, &dspctl); 1739 }}); 1740 0x7: subq_s_w({{ 1741 Rd_sw = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W, 1742 SATURATE, SIGNED, &dspctl); 1743 }}); 1744 } 1745 } 1746 0x3: decode OP_LO { 1747 format DspIntOp { 1748 0x4: muleq_s_w_phl({{ 1749 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1750 MODE_L, &dspctl); 1751 }}, IntMultOp); 1752 0x5: muleq_s_w_phr({{ 1753 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1754 MODE_R, &dspctl); 1755 }}, IntMultOp); 1756 0x6: mulq_s_ph({{ 1757 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1758 SATURATE, NOROUND, &dspctl); 1759 }}, IntMultOp); 1760 0x7: mulq_rs_ph({{ 1761 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1762 SATURATE, ROUND, &dspctl); 1763 }}, IntMultOp); 1764 } 1765 } 1766 } 1767 1768 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1769 //(DSP ASE MANUAL) 1770 0x1: decode OP_HI { 1771 0x0: decode OP_LO { 1772 format DspIntOp { 1773 0x0: cmpu_eq_qb({{ 1774 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1775 UNSIGNED, CMP_EQ, &dspctl); 1776 }}); 1777 0x1: cmpu_lt_qb({{ 1778 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1779 UNSIGNED, CMP_LT, &dspctl); 1780 }}); 1781 0x2: cmpu_le_qb({{ 1782 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1783 UNSIGNED, CMP_LE, &dspctl); 1784 }}); 1785 0x3: pick_qb({{ 1786 Rd_uw = dspPick(Rs_uw, Rt_uw, 1787 SIMD_FMT_QB, &dspctl); 1788 }}); 1789 0x4: cmpgu_eq_qb({{ 1790 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1791 UNSIGNED, CMP_EQ ); 1792 }}); 1793 0x5: cmpgu_lt_qb({{ 1794 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1795 UNSIGNED, CMP_LT); 1796 }}); 1797 0x6: cmpgu_le_qb({{ 1798 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1799 UNSIGNED, CMP_LE); 1800 }}); 1801 } 1802 } 1803 0x1: decode OP_LO { 1804 format DspIntOp { 1805 0x0: cmp_eq_ph({{ 1806 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1807 SIGNED, CMP_EQ, &dspctl); 1808 }}); 1809 0x1: cmp_lt_ph({{ 1810 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1811 SIGNED, CMP_LT, &dspctl); 1812 }}); 1813 0x2: cmp_le_ph({{ 1814 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1815 SIGNED, CMP_LE, &dspctl); 1816 }}); 1817 0x3: pick_ph({{ 1818 Rd_uw = dspPick(Rs_uw, Rt_uw, 1819 SIMD_FMT_PH, &dspctl); 1820 }}); 1821 0x4: precrq_qb_ph({{ 1822 Rd_uw = Rs_uw<31:24> << 24 | 1823 Rs_uw<15:8> << 16 | 1824 Rt_uw<31:24> << 8 | 1825 Rt_uw<15:8>; 1826 }}); 1827 0x5: precr_qb_ph({{ 1828 Rd_uw = Rs_uw<23:16> << 24 | 1829 Rs_uw<7:0> << 16 | 1830 Rt_uw<23:16> << 8 | 1831 Rt_uw<7:0>; 1832 }}); 1833 0x6: packrl_ph({{ 1834 Rd_uw = dspPack(Rs_uw, Rt_uw, SIMD_FMT_PH); 1835 }}); 1836 0x7: precrqu_s_qb_ph({{ 1837 Rd_uw = dspPrecrqu(Rs_uw, Rt_uw, &dspctl); 1838 }}); 1839 } 1840 } 1841 0x2: decode OP_LO { 1842 format DspIntOp { 1843 0x4: precrq_ph_w({{ 1844 Rd_uw = Rs_uw<31:16> << 16 | Rt_uw<31:16>; 1845 }}); 1846 0x5: precrq_rs_ph_w({{ 1847 Rd_uw = dspPrecrq(Rs_uw, Rt_uw, 1848 SIMD_FMT_W, &dspctl); 1849 }}); 1850 } 1851 } 1852 0x3: decode OP_LO { 1853 format DspIntOp { 1854 0x0: cmpgdu_eq_qb({{ 1855 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1856 UNSIGNED, CMP_EQ, &dspctl); 1857 }}); 1858 0x1: cmpgdu_lt_qb({{ 1859 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1860 UNSIGNED, CMP_LT, &dspctl); 1861 }}); 1862 0x2: cmpgdu_le_qb({{ 1863 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1864 UNSIGNED, CMP_LE, &dspctl); 1865 }}); 1866 0x6: precr_sra_ph_w({{ 1867 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1868 SIMD_FMT_W, NOROUND); 1869 }}); 1870 0x7: precr_sra_r_ph_w({{ 1871 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1872 SIMD_FMT_W, ROUND); 1873 }}); 1874 } 1875 } 1876 } 1877 1878 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1879 //(DSP ASE MANUAL) 1880 0x2: decode OP_HI { 1881 0x0: decode OP_LO { 1882 format DspIntOp { 1883 0x1: absq_s_qb({{ 1884 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl); 1885 }}); 1886 0x2: repl_qb({{ 1887 Rd_uw = RS_RT<7:0> << 24 | 1888 RS_RT<7:0> << 16 | 1889 RS_RT<7:0> << 8 | 1890 RS_RT<7:0>; 1891 }}); 1892 0x3: replv_qb({{ 1893 Rd_sw = Rt_uw<7:0> << 24 | 1894 Rt_uw<7:0> << 16 | 1895 Rt_uw<7:0> << 8 | 1896 Rt_uw<7:0>; 1897 }}); 1898 0x4: precequ_ph_qbl({{ 1899 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1900 SIMD_FMT_PH, SIGNED, MODE_L); 1901 }}); 1902 0x5: precequ_ph_qbr({{ 1903 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1904 SIMD_FMT_PH, SIGNED, MODE_R); 1905 }}); 1906 0x6: precequ_ph_qbla({{ 1907 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1908 SIMD_FMT_PH, SIGNED, MODE_LA); 1909 }}); 1910 0x7: precequ_ph_qbra({{ 1911 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1912 SIMD_FMT_PH, SIGNED, MODE_RA); 1913 }}); 1914 } 1915 } 1916 0x1: decode OP_LO { 1917 format DspIntOp { 1918 0x1: absq_s_ph({{ 1919 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl); 1920 }}); 1921 0x2: repl_ph({{ 1922 Rd_uw = (sext<10>(RS_RT))<15:0> << 16 | 1923 (sext<10>(RS_RT))<15:0>; 1924 }}); 1925 0x3: replv_ph({{ 1926 Rd_uw = Rt_uw<15:0> << 16 | 1927 Rt_uw<15:0>; 1928 }}); 1929 0x4: preceq_w_phl({{ 1930 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1931 SIMD_FMT_W, SIGNED, MODE_L); 1932 }}); 1933 0x5: preceq_w_phr({{ 1934 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1935 SIMD_FMT_W, SIGNED, MODE_R); 1936 }}); 1937 } 1938 } 1939 0x2: decode OP_LO { 1940 format DspIntOp { 1941 0x1: absq_s_w({{ 1942 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl); 1943 }}); 1944 } 1945 } 1946 0x3: decode OP_LO { 1947 0x3: IntOp::bitrev({{ 1948 Rd_uw = bitrev( Rt_uw<15:0> ); 1949 }}); 1950 format DspIntOp { 1951 0x4: preceu_ph_qbl({{ 1952 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1953 UNSIGNED, SIMD_FMT_PH, 1954 UNSIGNED, MODE_L); 1955 }}); 1956 0x5: preceu_ph_qbr({{ 1957 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1958 UNSIGNED, SIMD_FMT_PH, 1959 UNSIGNED, MODE_R ); 1960 }}); 1961 0x6: preceu_ph_qbla({{ 1962 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1963 UNSIGNED, SIMD_FMT_PH, 1964 UNSIGNED, MODE_LA ); 1965 }}); 1966 0x7: preceu_ph_qbra({{ 1967 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1968 UNSIGNED, SIMD_FMT_PH, 1969 UNSIGNED, MODE_RA); 1970 }}); 1971 } 1972 } 1973 } 1974 1975 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 1976 //(DSP ASE MANUAL) 1977 0x3: decode OP_HI { 1978 0x0: decode OP_LO { 1979 format DspIntOp { 1980 0x0: shll_qb({{ 1981 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_QB, 1982 NOSATURATE, UNSIGNED, &dspctl); 1983 }}); 1984 0x1: shrl_qb({{ 1985 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_QB, 1986 UNSIGNED); 1987 }}); 1988 0x2: shllv_qb({{ 1989 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB, 1990 NOSATURATE, UNSIGNED, &dspctl); 1991 }}); 1992 0x3: shrlv_qb({{ 1993 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB, 1994 UNSIGNED); 1995 }}); 1996 0x4: shra_qb({{ 1997 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 1998 NOROUND, SIGNED, &dspctl); 1999 }}); 2000 0x5: shra_r_qb({{ 2001 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2002 ROUND, SIGNED, &dspctl); 2003 }}); 2004 0x6: shrav_qb({{ 2005 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2006 NOROUND, SIGNED, &dspctl); 2007 }}); 2008 0x7: shrav_r_qb({{ 2009 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2010 ROUND, SIGNED, &dspctl); 2011 }}); 2012 } 2013 } 2014 0x1: decode OP_LO { 2015 format DspIntOp { 2016 0x0: shll_ph({{ 2017 Rd_uw = dspShll(Rt_uw, RS, SIMD_FMT_PH, 2018 NOSATURATE, SIGNED, &dspctl); 2019 }}); 2020 0x1: shra_ph({{ 2021 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2022 NOROUND, SIGNED, &dspctl); 2023 }}); 2024 0x2: shllv_ph({{ 2025 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2026 NOSATURATE, SIGNED, &dspctl); 2027 }}); 2028 0x3: shrav_ph({{ 2029 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2030 NOROUND, SIGNED, &dspctl); 2031 }}); 2032 0x4: shll_s_ph({{ 2033 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_PH, 2034 SATURATE, SIGNED, &dspctl); 2035 }}); 2036 0x5: shra_r_ph({{ 2037 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2038 ROUND, SIGNED, &dspctl); 2039 }}); 2040 0x6: shllv_s_ph({{ 2041 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2042 SATURATE, SIGNED, &dspctl); 2043 }}); 2044 0x7: shrav_r_ph({{ 2045 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2046 ROUND, SIGNED, &dspctl); 2047 }}); 2048 } 2049 } 2050 0x2: decode OP_LO { 2051 format DspIntOp { 2052 0x4: shll_s_w({{ 2053 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_W, 2054 SATURATE, SIGNED, &dspctl); 2055 }}); 2056 0x5: shra_r_w({{ 2057 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_W, 2058 ROUND, SIGNED, &dspctl); 2059 }}); 2060 0x6: shllv_s_w({{ 2061 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W, 2062 SATURATE, SIGNED, &dspctl); 2063 }}); 2064 0x7: shrav_r_w({{ 2065 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W, 2066 ROUND, SIGNED, &dspctl); 2067 }}); 2068 } 2069 } 2070 0x3: decode OP_LO { 2071 format DspIntOp { 2072 0x1: shrl_ph({{ 2073 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_PH, 2074 UNSIGNED); 2075 }}); 2076 0x3: shrlv_ph({{ 2077 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH, 2078 UNSIGNED); 2079 }}); 2080 } 2081 } 2082 } 2083 } 2084 2085 0x3: decode FUNCTION_LO { 2086 2087 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2088 //(DSP ASE Rev2 Manual) 2089 0x0: decode OP_HI { 2090 0x0: decode OP_LO { 2091 format DspIntOp { 2092 0x0: adduh_qb({{ 2093 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2094 NOROUND, UNSIGNED); 2095 }}); 2096 0x1: subuh_qb({{ 2097 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2098 NOROUND, UNSIGNED); 2099 }}); 2100 0x2: adduh_r_qb({{ 2101 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2102 ROUND, UNSIGNED); 2103 }}); 2104 0x3: subuh_r_qb({{ 2105 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2106 ROUND, UNSIGNED); 2107 }}); 2108 } 2109 } 2110 0x1: decode OP_LO { 2111 format DspIntOp { 2112 0x0: addqh_ph({{ 2113 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2114 NOROUND, SIGNED); 2115 }}); 2116 0x1: subqh_ph({{ 2117 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2118 NOROUND, SIGNED); 2119 }}); 2120 0x2: addqh_r_ph({{ 2121 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2122 ROUND, SIGNED); 2123 }}); 2124 0x3: subqh_r_ph({{ 2125 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2126 ROUND, SIGNED); 2127 }}); 2128 0x4: mul_ph({{ 2129 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2130 NOSATURATE, &dspctl); 2131 }}, IntMultOp); 2132 0x6: mul_s_ph({{ 2133 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2134 SATURATE, &dspctl); 2135 }}, IntMultOp); 2136 } 2137 } 2138 0x2: decode OP_LO { 2139 format DspIntOp { 2140 0x0: addqh_w({{ 2141 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2142 NOROUND, SIGNED); 2143 }}); 2144 0x1: subqh_w({{ 2145 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2146 NOROUND, SIGNED); 2147 }}); 2148 0x2: addqh_r_w({{ 2149 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2150 ROUND, SIGNED); 2151 }}); 2152 0x3: subqh_r_w({{ 2153 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2154 ROUND, SIGNED); 2155 }}); 2156 0x6: mulq_s_w({{ 2157 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2158 SATURATE, NOROUND, &dspctl); 2159 }}, IntMultOp); 2160 0x7: mulq_rs_w({{ 2161 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2162 SATURATE, ROUND, &dspctl); 2163 }}, IntMultOp); 2164 } 2165 } 2166 } 2167 } 2168 2169 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2170 0x4: decode SA { 2171 format BasicOp { 2172 0x02: wsbh({{ 2173 Rd_uw = Rt_uw<23:16> << 24 | 2174 Rt_uw<31:24> << 16 | 2175 Rt_uw<7:0> << 8 | 2176 Rt_uw<15:8>; 2177 }}); 2178 0x10: seb({{ Rd_sw = Rt_sb; }}); 2179 0x18: seh({{ Rd_sw = Rt_sh; }}); 2180 } 2181 } 2182 2183 0x6: decode FUNCTION_LO { 2184 2185 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2186 //(DSP ASE MANUAL) 2187 0x0: decode OP_HI { 2188 0x0: decode OP_LO { 2189 format DspHiLoOp { 2190 0x0: dpa_w_ph({{ 2191 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2192 SIMD_FMT_PH, SIGNED, MODE_L); 2193 }}, IntMultOp); 2194 0x1: dps_w_ph({{ 2195 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2196 SIMD_FMT_PH, SIGNED, MODE_L); 2197 }}, IntMultOp); 2198 0x2: mulsa_w_ph({{ 2199 dspac = dspMulsa(dspac, Rs_sw, Rt_sw, 2200 ACDST, SIMD_FMT_PH ); 2201 }}, IntMultOp); 2202 0x3: dpau_h_qbl({{ 2203 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2204 SIMD_FMT_QB, UNSIGNED, MODE_L); 2205 }}, IntMultOp); 2206 0x4: dpaq_s_w_ph({{ 2207 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2208 ACDST, SIMD_FMT_PH, 2209 SIMD_FMT_W, NOSATURATE, 2210 MODE_L, &dspctl); 2211 }}, IntMultOp); 2212 0x5: dpsq_s_w_ph({{ 2213 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2214 ACDST, SIMD_FMT_PH, 2215 SIMD_FMT_W, NOSATURATE, 2216 MODE_L, &dspctl); 2217 }}, IntMultOp); 2218 0x6: mulsaq_s_w_ph({{ 2219 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw, 2220 ACDST, SIMD_FMT_PH, 2221 &dspctl); 2222 }}, IntMultOp); 2223 0x7: dpau_h_qbr({{ 2224 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2225 SIMD_FMT_QB, UNSIGNED, MODE_R); 2226 }}, IntMultOp); 2227 } 2228 } 2229 0x1: decode OP_LO { 2230 format DspHiLoOp { 2231 0x0: dpax_w_ph({{ 2232 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2233 SIMD_FMT_PH, SIGNED, MODE_X); 2234 }}, IntMultOp); 2235 0x1: dpsx_w_ph({{ 2236 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2237 SIMD_FMT_PH, SIGNED, MODE_X); 2238 }}, IntMultOp); 2239 0x3: dpsu_h_qbl({{ 2240 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2241 SIMD_FMT_QB, UNSIGNED, MODE_L); 2242 }}, IntMultOp); 2243 0x4: dpaq_sa_l_w({{ 2244 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2245 ACDST, SIMD_FMT_W, 2246 SIMD_FMT_L, SATURATE, 2247 MODE_L, &dspctl); 2248 }}, IntMultOp); 2249 0x5: dpsq_sa_l_w({{ 2250 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2251 ACDST, SIMD_FMT_W, 2252 SIMD_FMT_L, SATURATE, 2253 MODE_L, &dspctl); 2254 }}, IntMultOp); 2255 0x7: dpsu_h_qbr({{ 2256 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2257 SIMD_FMT_QB, UNSIGNED, MODE_R); 2258 }}, IntMultOp); 2259 } 2260 } 2261 0x2: decode OP_LO { 2262 format DspHiLoOp { 2263 0x0: maq_sa_w_phl({{ 2264 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2265 ACDST, SIMD_FMT_PH, 2266 MODE_L, SATURATE, &dspctl); 2267 }}, IntMultOp); 2268 0x2: maq_sa_w_phr({{ 2269 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2270 ACDST, SIMD_FMT_PH, 2271 MODE_R, SATURATE, &dspctl); 2272 }}, IntMultOp); 2273 0x4: maq_s_w_phl({{ 2274 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2275 ACDST, SIMD_FMT_PH, 2276 MODE_L, NOSATURATE, &dspctl); 2277 }}, IntMultOp); 2278 0x6: maq_s_w_phr({{ 2279 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2280 ACDST, SIMD_FMT_PH, 2281 MODE_R, NOSATURATE, &dspctl); 2282 }}, IntMultOp); 2283 } 2284 } 2285 0x3: decode OP_LO { 2286 format DspHiLoOp { 2287 0x0: dpaqx_s_w_ph({{ 2288 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2289 ACDST, SIMD_FMT_PH, 2290 SIMD_FMT_W, NOSATURATE, 2291 MODE_X, &dspctl); 2292 }}, IntMultOp); 2293 0x1: dpsqx_s_w_ph({{ 2294 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2295 ACDST, SIMD_FMT_PH, 2296 SIMD_FMT_W, NOSATURATE, 2297 MODE_X, &dspctl); 2298 }}, IntMultOp); 2299 0x2: dpaqx_sa_w_ph({{ 2300 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2301 ACDST, SIMD_FMT_PH, 2302 SIMD_FMT_W, SATURATE, 2303 MODE_X, &dspctl); 2304 }}, IntMultOp); 2305 0x3: dpsqx_sa_w_ph({{ 2306 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2307 ACDST, SIMD_FMT_PH, 2308 SIMD_FMT_W, SATURATE, 2309 MODE_X, &dspctl); 2310 }}, IntMultOp); 2311 } 2312 } 2313 } 2314 2315 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2316 0x1: decode OP_HI { 2317 0x0: decode OP_LO { 2318 format IntOp { 2319 0x0: append({{ 2320 Rt_uw = (Rt_uw << RD) | bits(Rs_uw, RD - 1, 0); 2321 }}); 2322 0x1: prepend({{ 2323 Rt_uw = (Rt_uw >> RD) | 2324 (bits(Rs_uw, RD - 1, 0) << (32 - RD)); 2325 }}); 2326 } 2327 } 2328 0x2: decode OP_LO { 2329 format IntOp { 2330 0x0: balign({{ 2331 Rt_uw = (Rt_uw << (8 * BP)) | 2332 (Rs_uw >> (8 * (4 - BP))); 2333 }}); 2334 } 2335 } 2336 } 2337 2338 } 2339 0x7: decode FUNCTION_LO { 2340 2341 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2342 //(DSP ASE MANUAL) 2343 0x0: decode OP_HI { 2344 0x0: decode OP_LO { 2345 format DspHiLoOp { 2346 0x0: extr_w({{ 2347 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2348 NOROUND, NOSATURATE, &dspctl); 2349 }}); 2350 0x1: extrv_w({{ 2351 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2352 NOROUND, NOSATURATE, &dspctl); 2353 }}); 2354 0x2: extp({{ 2355 Rt_uw = dspExtp(dspac, RS, &dspctl); 2356 }}); 2357 0x3: extpv({{ 2358 Rt_uw = dspExtp(dspac, Rs_uw, &dspctl); 2359 }}); 2360 0x4: extr_r_w({{ 2361 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2362 ROUND, NOSATURATE, &dspctl); 2363 }}); 2364 0x5: extrv_r_w({{ 2365 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2366 ROUND, NOSATURATE, &dspctl); 2367 }}); 2368 0x6: extr_rs_w({{ 2369 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2370 ROUND, SATURATE, &dspctl); 2371 }}); 2372 0x7: extrv_rs_w({{ 2373 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2374 ROUND, SATURATE, &dspctl); 2375 }}); 2376 } 2377 } 2378 0x1: decode OP_LO { 2379 format DspHiLoOp { 2380 0x2: extpdp({{ 2381 Rt_uw = dspExtpd(dspac, RS, &dspctl); 2382 }}); 2383 0x3: extpdpv({{ 2384 Rt_uw = dspExtpd(dspac, Rs_uw, &dspctl); 2385 }}); 2386 0x6: extr_s_h({{ 2387 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2388 NOROUND, SATURATE, &dspctl); 2389 }}); 2390 0x7: extrv_s_h({{ 2391 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, Rs_uw, 2392 NOROUND, SATURATE, &dspctl); 2393 }}); 2394 } 2395 } 2396 0x2: decode OP_LO { 2397 format DspIntOp { 2398 0x2: rddsp({{ 2399 Rd_uw = readDSPControl(&dspctl, RDDSPMASK); 2400 }}); 2401 0x3: wrdsp({{ 2402 writeDSPControl(&dspctl, Rs_uw, WRDSPMASK); 2403 }}); 2404 } 2405 } 2406 0x3: decode OP_LO { 2407 format DspHiLoOp { 2408 0x2: shilo({{ 2409 if (sext<6>(HILOSA) < 0) { 2410 dspac = (uint64_t)dspac << 2411 -sext<6>(HILOSA); 2412 } else { 2413 dspac = (uint64_t)dspac >> 2414 sext<6>(HILOSA); 2415 } 2416 }}); 2417 0x3: shilov({{ 2418 if (sext<6>(Rs_sw<5:0>) < 0) { 2419 dspac = (uint64_t)dspac << 2420 -sext<6>(Rs_sw<5:0>); 2421 } else { 2422 dspac = (uint64_t)dspac >> 2423 sext<6>(Rs_sw<5:0>); 2424 } 2425 }}); 2426 0x7: mthlip({{ 2427 dspac = dspac << 32; 2428 dspac |= Rs_uw; 2429 dspctl = insertBits(dspctl, 5, 0, 2430 dspctl<5:0> + 32); 2431 }}); 2432 } 2433 } 2434 } 2435 0x3: decode OP default FailUnimpl::rdhwr() {
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