1 // -*- mode:c++ -*-
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1// -*- mode:c++ -*- |
2 3//////////////////////////////////////////////////////////////////// 4// 5// The actual MIPS32 ISA decoder 6// ----------------------------- 7// The following instructions are specified in the MIPS32 ISA 8// Specification. Decoding closely follows the style specified
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9// in the MIPS32 ISAthe specification document starting with Table
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9// in the MIPS32 ISA specification document starting with Table |
10// A-2 (document available @ www.mips.com) 11//
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12//@todo: Distinguish "unknown/future" use insts from "reserved"
13// ones
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12decode OPCODE_HI default Unknown::unknown() {
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15
16 // Derived From ... Table A-2 MIPS32 ISA Manual
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13 //Table A-2 |
14 0x0: decode OPCODE_LO {
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18
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15 0x0: decode FUNCTION_HI { 16 0x0: decode FUNCTION_LO { 17 0x1: decode MOVCI { 18 format BasicOp {
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23 0: movf({{ if (getFPConditionCode(FCSR, CC) == 0) Rd = Rs}});
24 1: movt({{ if (getFPConditionCode(FCSR, CC) == 1) Rd = Rs}});
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19 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }}); 20 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }}); |
21 } 22 } 23 24 format BasicOp {
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29
30 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
31 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions.
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25 //Table A-3 Note: "Specific encodings of the rd, rs, and 26 //rt fields are used to distinguish SLL, SSNOP, and EHB 27 //functions |
28 0x0: decode RS {
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33 0x0: decode RT { //fix Nop traditional vs. Nop converted disassembly later
34 0x0: decode RD default Nop::nop(){
35 0x0: decode SA {
36 0x1: ssnop({{ ; }}); //really sll r0,r0,1
37 0x3: ehb({{ ; }}); //really sll r0,r0,3
38 }
39 }
40
41 default: sll({{ Rd = Rt.uw << SA; }});
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29 0x0: decode RT_RD { 30 0x0: decode SA default Nop::nop(){ 31 0x1: WarnUnimpl::ssnop(); 32 0x3: WarnUnimpl::ehb(); 33 } 34 default: sll({{ Rd = Rt.uw << SA; }}); |
35 }
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43
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36 } 37 38 0x2: decode RS_SRL { 39 0x0:decode SRL { 40 0: srl({{ Rd = Rt.uw >> SA; }}); 41 42 //Hardcoded assuming 32-bit ISA, probably need parameter here 43 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 44 } 45 } 46 47 0x3: decode RS { 48 0x0: sra({{ 49 uint32_t temp = Rt >> SA;
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58
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50 if ( (Rt & 0x80000000) > 0 ) { 51 uint32_t mask = 0x80000000; 52 for(int i=0; i < SA; i++) { 53 temp |= mask; 54 mask = mask >> 1; 55 } 56 }
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66
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57 Rd = temp; 58 }}); 59 } 60 61 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 62 63 0x6: decode SRLV { 64 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 65 66 //Hardcoded assuming 32-bit ISA, probably need parameter here 67 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 68 } 69 70 0x7: srav({{ 71 int shift_amt = Rs<4:0>; 72 73 uint32_t temp = Rt >> shift_amt; 74 75 if ( (Rt & 0x80000000) > 0 ) { 76 uint32_t mask = 0x80000000; 77 for(int i=0; i < shift_amt; i++) { 78 temp |= mask; 79 mask = mask >> 1; 80 } 81 } 82 83 Rd = temp; 84 }}); 85 } 86 } 87 88 0x1: decode FUNCTION_LO {
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99
100 //Table A-3 Note: "Specific encodings of the hint field are used
101 //to distinguish JR from JR.HB and JALR from JALR.HB"
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89 //Table A-3 Note: "Specific encodings of the hint field are 90 //used to distinguish JR from JR.HB and JALR from JALR.HB" |
91 format Jump { 92 0x0: decode HINT {
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104 0:jr({{ NNPC = Rs & ~1; }},IsReturn);
105
106 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn);
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93 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards); 94 default: jr({{ NNPC = Rs & ~1; }}, IsReturn); |
95 } 96 97 0x1: decode HINT {
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110 0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn);
111
112 1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn);
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98 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall, Link 99 , ClearHazards); 100 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall, 101 Link); |
102 } 103 } 104 105 format BasicOp {
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117 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
118 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
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106 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 107 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 108 0x4: syscall({{ xc->syscall(R2); }}, IsNonSpeculative); 109 0x7: sync({{ ; }}, IsMemBarrier); |
110 } 111
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121 format BasicOp {
122 0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative);
123 0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative);
124 0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative);
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112 format FailUnimpl { 113 0x5: break(); |
114 } 115 } 116 117 0x2: decode FUNCTION_LO {
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129 format BasicOp {
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118 format HiLoMiscOp { |
119 0x0: mfhi({{ Rd = HI; }}); 120 0x1: mthi({{ HI = Rs; }}); 121 0x2: mflo({{ Rd = LO; }}); 122 0x3: mtlo({{ LO = Rs; }}); 123 } 124 } 125 126 0x3: decode FUNCTION_LO {
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138 format IntOp {
139 0x0: mult({{
140 int64_t temp1 = Rs.sd * Rt.sd;
141 HI = temp1<63:32>;
142 LO = temp1<31:0>;
143 }});
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127 format HiLoOp { 128 0x0: mult({{ val = Rs.sd * Rt.sd; }}); 129 0x1: multu({{ val = Rs.ud * Rt.ud; }}); 130 } |
131
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145 0x1: multu({{
146 uint64_t temp1 = Rs.ud * Rt.ud;
147 HI = temp1<63:32>;
148 LO = temp1<31:0>;
149 }});
150
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132 format HiLoMiscOp { |
133 0x2: div({{ 134 HI = Rs.sd % Rt.sd; 135 LO = Rs.sd / Rt.sd; 136 }});
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155
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137 0x3: divu({{ 138 HI = Rs.ud % Rt.ud; 139 LO = Rs.ud / Rt.ud; 140 }}); 141 } 142 } 143 144 0x4: decode HINT { 145 0x0: decode FUNCTION_LO { 146 format IntOp { 147 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}}); 148 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 149 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 150 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 151 0x4: and({{ Rd = Rs & Rt;}}); 152 0x5: or({{ Rd = Rs | Rt;}}); 153 0x6: xor({{ Rd = Rs ^ Rt;}}); 154 0x7: nor({{ Rd = ~(Rs | Rt);}}); 155 } 156 } 157 } 158 159 0x5: decode HINT { 160 0x0: decode FUNCTION_LO { 161 format IntOp{ 162 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 163 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 164 } 165 } 166 } 167 168 0x6: decode FUNCTION_LO { 169 format Trap { 170 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 171 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 172 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 173 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 174 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 175 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 176 } 177 } 178 } 179 180 0x1: decode REGIMM_HI { 181 0x0: decode REGIMM_LO { 182 format Branch { 183 0x0: bltz({{ cond = (Rs.sw < 0); }}); 184 0x1: bgez({{ cond = (Rs.sw >= 0); }});
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185 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 186 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); |
187 }
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205
206 format BranchLikely {
207 0x2: bltzl({{ cond = (Rs.sw < 0); }});
208 0x3: bgezl({{ cond = (Rs.sw >= 0); }});
209 }
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188 } 189 190 0x1: decode REGIMM_LO { 191 format Trap { 192 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 193 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 194 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 195 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 196 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 197 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 198 } 199 } 200 201 0x2: decode REGIMM_LO { 202 format Branch {
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225 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn);
226 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn);
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203 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 204 0x1: decode RS { 205 0x0: bal ({{ cond = 1; }}, IsCall, Link); 206 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 207 } 208 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 209 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); |
210 }
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228
229 format BranchLikely {
230 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn);
231 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn);
232 }
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211 } 212 213 0x3: decode REGIMM_LO { 214 format WarnUnimpl { 215 0x7: synci(); 216 } 217 } 218 } 219 220 format Jump { 221 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
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244
245 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn);
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222 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall, 223 Link); |
224 } 225 226 format Branch {
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249 0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
250 0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
251 0x6: decode RT {
252 0x0: blez({{ cond = (Rs.sw <= 0); }});
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227 0x4: decode RS_RT { 228 0x0: b({{ cond = 1; }}); 229 default: beq({{ cond = (Rs.sw == Rt.sw); }}); |
230 }
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254
255 0x7: decode RT {
256 0x0: bgtz({{ cond = (Rs.sw > 0); }});
257 }
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231 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 232 0x6: blez({{ cond = (Rs.sw <= 0); }}); 233 0x7: bgtz({{ cond = (Rs.sw > 0); }}); |
234 } 235 } 236 237 0x1: decode OPCODE_LO {
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262 format IntOp {
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238 format IntImmOp { |
239 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 240 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 241 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 242 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 243 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 244 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 245 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 246 247 0x7: decode RS { 248 0x0: lui({{ Rt = imm << 16}}); 249 } 250 } 251 } 252 253 0x2: decode OPCODE_LO {
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278
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254 //Table A-11 MIPS32 COP0 Encoding of rs Field 255 0x0: decode RS_MSB { 256 0x0: decode RS {
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282 format System {
283 0x0: mfc0({{
284 //uint64_t reg_num = Rd.uw;
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257 format CP0Control { 258 0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }}); 259 0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }}); 260 } |
261
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286 Rt = xc->readMiscReg(RD << 5 | SEL);
287 }});
288
289 0x4: mtc0({{
290 //uint64_t reg_num = Rd.uw;
291
292 xc->setMiscReg(RD << 5 | SEL,Rt);
293 }});
294
295 0x8: mftr({{
296 //The contents of the coprocessor 0 register specified by the
297 //combination of rd and sel are loaded into general register
298 //rt. Note that not all coprocessor 0 registers support the
299 //sel field. In those instances, the sel field must be zero.
300
301 //MT Code Needed Here
302
303 }});
304
305 0xC: mttr({{
306 //The contents of the coprocessor 0 register specified by the
307 //combination of rd and sel are loaded into general register
308 //rt. Note that not all coprocessor 0 registers support the
309 //sel field. In those instances, the sel field must be zero.
310
311 //MT Code Needed Here
312 }});
313
314
315 0xA: rdpgpr({{
316 //Accessing Previous Shadow Set Register Number
317 //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/;
318 //uint64_t reg_num = Rt.uw;
319
320 //Rd = xc->regs.IntRegFile[prev];
321 //Rd = xc->shadowIntRegFile[prev][reg_num];
322 }});
323
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262 format MipsMT { 263 0x8: mftr(); 264 0xC: mttr(); |
265 0xB: decode RD {
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325
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266 0x0: decode SC {
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327 0x0: dvpe({{
328 Rt.sw = xc->readMiscReg(MVPControl);
329 xc->setMiscReg(MVPControl,0);
330 }});
331
332 0x1: evpe({{
333 Rt.sw = xc->readMiscReg(MVPControl);
334 xc->setMiscReg(MVPControl,1);
335 }});
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267 0x0: dvpe(); 268 0x1: evpe(); |
269 }
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337
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270 0x1: decode SC {
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339 0x0: dmt({{
340 Rt.sw = xc->readMiscReg(VPEControl);
341 xc->setMiscReg(VPEControl,0);
342 }});
343
344 0x1: emt({{
345 Rt.sw = xc->readMiscReg(VPEControl);
346 xc->setMiscReg(VPEControl,1);
347 }});
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271 0x0: dmt(); 272 0x1: emt(); 273 0xC: decode SC { 274 0x0: di(); 275 0x1: ei(); 276 } |
277 }
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349
350 0xC: decode SC {
351 0x0: di({{
352 Rt.sw = xc->readMiscReg(Status);
353 xc->setMiscReg(Status,0);
354 }});
355
356 0x1: ei({{
357 Rt.sw = xc->readMiscReg(Status);
358 xc->setMiscReg(Status,1);
359 }});
360 }
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278 }
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279 } |
280
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363 0xE: wrpgpr({{
364 //Accessing Previous Shadow Set Register Number
365 //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/);
366 //uint64_t reg_num = Rd.uw;
367
368 //xc->regs.IntRegFile[prev];
369 //xc->shadowIntRegFile[prev][reg_num] = Rt;
370 }});
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281 format FailUnimpl { 282 0xA: rdpgpr(); 283 0xE: wrpgpr(); |
284 } 285 } 286 287 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 288 0x1: decode FUNCTION {
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376 format System {
377 0x01: tlbr({{ }});
378 0x02: tlbwi({{ }});
379 0x06: tlbwr({{ }});
380 0x08: tlbp({{ }});
381 }
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289 format FailUnimpl { 290 0x01: tlbr(); 291 0x02: tlbwi(); 292 0x06: tlbwr(); 293 0x08: tlbp(); |
294
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383 format WarnUnimpl {
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295 0x18: eret(); 296 0x1F: deret(); 297 0x20: wait(); 298 } 299 } 300 } 301 302 //Table A-13 MIPS32 COP1 Encoding of rs Field 303 0x1: decode RS_MSB { 304 305 0x0: decode RS_HI { 306 0x0: decode RS_LO {
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396 format FloatOp {
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307 format CP1Control { |
308 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }});
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398 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
399 0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
400 0x7: mthc1({{
401 uint64_t fs_hi = Rt.uw;
402 uint64_t fs_lo = Fs.ud & 0x0000FFFF;
403 Fs.ud = fs_hi << 32 | fs_lo;
404 }});
405 }
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309
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407 format System {
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310 0x2: cfc1({{ 311 switch (FS) 312 { 313 case 0: 314 Rt = FIR; 315 break; 316 case 25: 317 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; 318 break; 319 case 26: 320 Rt = 0 | (FCSR & 0x0003F07C); 321 break; 322 case 28: 323 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); 324 break; 325 case 31: 326 Rt = FCSR; 327 break; 328 default:
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427 panic("FP Control Value (%d) Not Available. Ignoring Access to"
428 "Floating Control Status Register",FS);
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329 panic("FP Control Value (%d) Not Valid"); |
330 } 331 }}); 332
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333 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 334 335 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 336 |
337 0x6: ctc1({{ 338 switch (FS) 339 { 340 case 25: 341 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 342 | (FCSR & 0x01000000) // bit 24 343 | (FCSR & 0x004FFFFF);// bit 22...0 344 break; 345 346 case 26: 347 FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 348 | Rt.uw<17:12> << 12 // bit 17...12 349 | (FCSR & 0x00000F80) << 7// bit 11...7 350 | Rt.uw<6:2> << 2 // bit 6...2 351 | (FCSR & 0x00000002); // bit 1...0 352 break; 353 354 case 28: 355 FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 356 | Rt.uw<2:2> << 24 // bit 24 357 | (FCSR & 0x00FFF000) << 23// bit 23...12 358 | Rt.uw<11:7> << 7 // bit 24 359 | (FCSR & 0x000007E) 360 | Rt.uw<1:0>;// bit 22...0 361 break; 362 363 case 31: 364 FCSR = Rt.uw; 365 break; 366 367 default: 368 panic("FP Control Value (%d) Not Available. Ignoring Access to" 369 "Floating Control Status Register", FS); 370 } 371 }});
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372 373 0x7: mthc1({{ 374 uint64_t fs_hi = Rt.uw; 375 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 376 Fs.ud = (fs_hi << 32) | fs_lo; 377 }}); 378 |
379 } 380 } 381 382 0x1: decode ND {
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471 0x0: decode TF {
472 format Branch {
473 0x0: bc1f({{ cond = (getFPConditionCode(FCSR,CC) == 0); }});
474 0x1: bc1t({{ cond = (getFPConditionCode(FCSR,CC) == 1); }});
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383 format Branch { 384 0x0: decode TF { 385 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 386 }}); 387 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 388 }}); |
389 }
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476 }
477
478 0x1: decode TF {
479 format BranchLikely {
480 0x0: bc1fl({{ cond = (getFPConditionCode(FCSR,CC) == 0); }});
481 0x1: bc1tl({{ cond = (getFPConditionCode(FCSR,CC) == 1); }});
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390 0x1: decode TF { 391 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 392 }}, Likely); 393 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 394 }}, Likely); |
395 } 396 } 397 } 398 } 399 400 0x1: decode RS_HI { 401 0x2: decode RS_LO {
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489
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402 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
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491 //(( single-word ))
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403 //(( single-precision floating point)) |
404 0x0: decode FUNCTION_HI { 405 0x0: decode FUNCTION_LO { 406 format FloatOp { 407 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 408 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 409 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 410 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 411 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 412 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 413 0x6: mov_s({{ Fd.sf = Fs.sf;}});
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502 0x7: neg_s({{ Fd.sf = -1 * Fs.sf;}});
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414 0x7: neg_s({{ Fd.sf = -Fs.sf;}}); |
415 } 416 } 417 418 0x1: decode FUNCTION_LO {
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507 format Float64Op {
508 0x0: round_l_s({{
509 Fd.ud = fpConvert(roundFP(Fs.sf,0), SINGLE_TO_LONG);
510 }});
511
512 0x1: trunc_l_s({{
513 Fd.ud = fpConvert(truncFP(Fs.sf), SINGLE_TO_LONG);
514 }});
515
516 0x2: ceil_l_s({{
517 Fd.ud = fpConvert(ceil(Fs.sf), SINGLE_TO_LONG);
518 }});
519
520 0x3: floor_l_s({{
521 Fd.ud = fpConvert(floor(Fs.sf), SINGLE_TO_LONG);
522 }});
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419 format FloatConvertOp { 420 0x0: round_l_s({{ val = Fs.sf; }}, ToLong, 421 Round); 422 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong, 423 Trunc); 424 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong, 425 Ceil); 426 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong, 427 Floor); 428 0x4: round_w_s({{ val = Fs.sf; }}, ToWord, 429 Round); 430 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord, 431 Trunc); 432 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord, 433 Ceil); 434 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord, 435 Floor); |
436 }
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524
525 format FloatOp {
526 0x4: round_w_s({{
527 Fd.uw = fpConvert(roundFP(Fs.sf,0), SINGLE_TO_WORD);
528 }});
529
530 0x5: trunc_w_s({{
531 Fd.uw = fpConvert(truncFP(Fs.sf), SINGLE_TO_WORD);
532 }});
533
534 0x6: ceil_w_s({{
535 Fd.uw = fpConvert(ceil(Fs.sf), SINGLE_TO_WORD);
536 }});
537
538 0x7: floor_w_s({{
539 Fd.uw = fpConvert(floor(Fs.sf), SINGLE_TO_WORD);
540 }});
541 }
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437 } 438 439 0x2: decode FUNCTION_LO { 440 0x1: decode MOVCF {
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546 format FloatOp {
547 0x0: movf_s({{if (getFPConditionCode(FCSR,CC) == 0) Fd = Fs;}});
548 0x1: movt_s({{if (getFPConditionCode(FCSR,CC) == 1) Fd = Fs;}});
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441 format BasicOp { 442 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }}); 443 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }}); |
444 } 445 } 446
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447 format BasicOp { 448 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 449 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 450 } 451 |
452 format FloatOp {
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553 0x2: movz_s({{ if (Rt == 0) Fd = Fs; }});
554 0x3: movn_s({{ if (Rt != 0) Fd = Fs; }});
|
453 0x5: recip_s({{ Fd = 1 / Fs; }}); 454 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 455 } 456 } 457 458 0x4: decode FUNCTION_LO {
|
561
|
459 format FloatConvertOp {
|
563 0x1: cvt_d_s({{
564 Fd.ud = fpConvert(Fs.sf, SINGLE_TO_DOUBLE);
565 }});
566
567 0x4: cvt_w_s({{
568 Fd.uw = fpConvert(Fs.sf, SINGLE_TO_WORD);
569 }});
|
460 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 461 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 462 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); |
463 } 464
|
572 format FloatConvertOp {
573 0x5: cvt_l_s({{
574 Fd.ud = fpConvert(Fs.sf, SINGLE_TO_LONG);
|
465 0x6: FloatOp::cvt_ps_s({{ 466 Fd.ud = (uint64_t) Fs.uw << 32 | 467 (uint64_t) Ft.uw; |
468 }});
|
576
577 0x6: cvt_ps_st({{
578 Fd.ud = (uint64_t)Fs.uw << 32 | (uint64_t)Ft.uw;
579 }});
580 }
|
469 } 470 471 0x6: decode FUNCTION_LO { 472 format FloatCompareOp {
|
585 0x0: c_f_s({{ cond = 0; }});
586
587 0x1: c_un_s({{
588 if (isnan(Fs.sf) || isnan(Ft.sf))
589 cond = 1;
590 else
591 cond = 0;
592 }});
593
594 0x2: c_eq_s({{
595 if (isnan(Fs.sf) || isnan(Ft.sf))
596 cond = 0;
597 else
598 cond = (Fs.sf == Ft.sf);
599 }});
600
601 0x3: c_ueq_s({{
602 if (isnan(Fs.sf) || isnan(Ft.sf))
603 cond = 1;
604 else
605 cond = (Fs.sf == Ft.sf);
606 }});
607
608 0x4: c_olt_s({{
609 if (isnan(Fs.sf) || isnan(Ft.sf))
610 cond = 0;
611 else
612 cond = (Fs.sf < Ft.sf);
613 }});
614
615 0x5: c_ult_s({{
616 if (isnan(Fs.sf) || isnan(Ft.sf))
617 cond = 1;
618 else
619 cond = (Fs.sf < Ft.sf);
620 }});
621
622 0x6: c_ole_s({{
623 if (isnan(Fs.sf) || isnan(Ft.sf))
624 cond = 0;
625 else
626 cond = (Fs.sf <= Ft.sf);
627 }});
628
629 0x7: c_ule_s({{
630 if (isnan(Fs.sf) || isnan(Ft.sf))
631 cond = 1;
632 else
633 cond = (Fs.sf <= Ft.sf);
634 }});
|
473 0x0: c_f_s({{ cond = 0; }}, SinglePrecision, 474 UnorderedFalse); 475 0x1: c_un_s({{ cond = 0; }}, SinglePrecision, 476 UnorderedTrue); 477 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 478 UnorderedFalse); 479 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 480 UnorderedTrue); 481 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 482 UnorderedFalse); 483 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 484 UnorderedTrue); 485 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 486 UnorderedFalse); 487 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 488 UnorderedTrue); |
489 } 490 } 491 492 0x7: decode FUNCTION_LO {
|
639 format FloatCompareWithXcptOp {
640 0x0: c_sf_s({{ cond = 0; }});
641
642 0x1: c_ngle_s({{
643 if (isnan(Fs.sf) || isnan(Ft.sf))
644 cond = 1;
645 else
646 cond = 0;
647 }});
648
649 0x2: c_seq_s({{
650 if (isnan(Fs.sf) || isnan(Ft.sf))
651 cond = 0;
652 else
653 cond = (Fs.sf == Ft.sf);
654 }});
655
656 0x3: c_ngl_s({{
657 if (isnan(Fs.sf) || isnan(Ft.sf))
658 cond = 1;
659 else
660 cond = (Fs.sf == Ft.sf);
661 }});
662
663 0x4: c_lt_s({{
664 if (isnan(Fs.sf) || isnan(Ft.sf))
665 cond = 0;
666 else
667 cond = (Fs.sf < Ft.sf);
668 }});
669
670 0x5: c_nge_s({{
671 if (isnan(Fs.sf) || isnan(Ft.sf))
672 cond = 1;
673 else
674 cond = (Fs.sf < Ft.sf);
675 }});
676
677 0x6: c_le_s({{
678 if (isnan(Fs.sf) || isnan(Ft.sf))
679 cond = 0;
680 else
681 cond = (Fs.sf <= Ft.sf);
682 }});
683
684 0x7: c_ngt_s({{
685 if (isnan(Fs.sf) || isnan(Ft.sf))
686 cond = 1;
687 else
688 cond = (Fs.sf <= Ft.sf);
689 }});
|
493 format FloatCompareOp { 494 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 495 UnorderedFalse, QnanException); 496 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 497 UnorderedTrue, QnanException); 498 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}}, 499 UnorderedFalse, QnanException); 500 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 501 UnorderedTrue, QnanException); 502 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 503 UnorderedFalse, QnanException); 504 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 505 UnorderedTrue, QnanException); 506 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 507 UnorderedFalse, QnanException); 508 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 509 UnorderedTrue, QnanException); |
510 } 511 } 512 } 513 514 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 515 0x1: decode FUNCTION_HI { 516 0x0: decode FUNCTION_LO { 517 format FloatOp {
|
698 0x0: add_d({{ Fd.df = Fs.df + Ft.df;}});
699 0x1: sub_d({{ Fd.df = Fs.df - Ft.df;}});
700 0x2: mul_d({{ Fd.df = Fs.df * Ft.df;}});
701 0x3: div_d({{ Fd.df = Fs.df / Ft.df;}});
702 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df);}});
703 0x5: abs_d({{ Fd.df = fabs(Fs.df);}});
704 0x6: mov_d({{ Fd.ud = Fs.ud;}});
705 0x7: neg_d({{ Fd.df = -1 * Fs.df;}});
|
518 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 519 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 520 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 521 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 522 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 523 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 524 0x6: mov_d({{ Fd.df = Fs.df; }}); 525 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); |
526 } 527 } 528 529 0x1: decode FUNCTION_LO {
|
710 format FloatOp {
711 0x0: round_l_d({{
712 Fd.ud = fpConvert(roundFP(Fs.df,0), DOUBLE_TO_LONG);
713 }});
714
715 0x1: trunc_l_d({{
716 Fd.ud = fpConvert(truncFP(Fs.df), DOUBLE_TO_LONG);
717 }});
718
719 0x2: ceil_l_d({{
720 Fd.ud = fpConvert(ceil(Fs.df), DOUBLE_TO_LONG);
721 }});
722
723 0x3: floor_l_d({{
724 Fd.ud = fpConvert(floor(Fs.df), DOUBLE_TO_LONG);
725 }});
|
530 format FloatConvertOp { 531 0x0: round_l_d({{ val = Fs.df; }}, ToLong, 532 Round); 533 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong, 534 Trunc); 535 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong, 536 Ceil); 537 0x3: floor_l_d({{ val = Fs.df; }}, ToLong, 538 Floor); 539 0x4: round_w_d({{ val = Fs.df; }}, ToWord, 540 Round); 541 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord, 542 Trunc); 543 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord, 544 Ceil); 545 0x7: floor_w_d({{ val = Fs.df; }}, ToWord, 546 Floor); |
547 }
|
727
728 format FloatOp {
729 0x4: round_w_d({{
730 Fd.uw = fpConvert(roundFP(Fs.df,0), DOUBLE_TO_WORD);
731 }});
732
733 0x5: trunc_w_d({{
734 Fd.uw = fpConvert(truncFP(Fs.df), DOUBLE_TO_WORD);
735 }});
736
737 0x6: ceil_w_d({{
738 Fd.uw = fpConvert(ceil(Fs.df), DOUBLE_TO_WORD);
739 }});
740
741 0x7: floor_w_d({{
742 Fd.uw = fpConvert(floor(Fs.df), DOUBLE_TO_WORD);
743 }});
744 }
|
548 } 549 550 0x2: decode FUNCTION_LO { 551 0x1: decode MOVCF {
|
749 format FloatOp {
750 0x0: movf_d({{if (getFPConditionCode(FCSR,CC) == 0) Fd.df = Fs.df; }});
751 0x1: movt_d({{if (getFPConditionCode(FCSR,CC) == 1) Fd.df = Fs.df; }});
|
552 format BasicOp { 553 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ? 554 Fs.df : Fd.df; 555 }}); 556 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ? 557 Fs.df : Fd.df; 558 }}); |
559 } 560 } 561 562 format BasicOp {
|
756 0x2: movz_d({{ if (Rt == 0) Fd.df = Fs.df; }});
757 0x3: movn_d({{ if (Rt != 0) Fd.df = Fs.df; }});
|
563 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }}); 564 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }}); |
565 } 566 567 format FloatOp {
|
761 0x5: recip_d({{ Fd.df = 1 / Fs.df}});
|
568 0x5: recip_d({{ Fd.df = 1 / Fs.df }}); |
569 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); 570 } 571 } 572 573 0x4: decode FUNCTION_LO {
|
767 format FloatOp {
768 0x0: cvt_s_d({{
769 Fd.uw = fpConvert(Fs.df, DOUBLE_TO_SINGLE);
770 }});
771
772 0x4: cvt_w_d({{
773 Fd.uw = fpConvert(Fs.df, DOUBLE_TO_WORD);
774 }});
775
776 0x5: cvt_l_d({{
777 Fd.ud = fpConvert(Fs.df, DOUBLE_TO_LONG);
778 }});
|
574 format FloatConvertOp { 575 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 576 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 577 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); |
578 } 579 } 580 581 0x6: decode FUNCTION_LO { 582 format FloatCompareOp {
|
784 0x0: c_f_d({{ cond = 0; }});
785
786 0x1: c_un_d({{
787 if (isnan(Fs.df) || isnan(Ft.df))
788 cond = 1;
789 else
790 cond = 0;
791 }});
792
793 0x2: c_eq_d({{
794 if (isnan(Fs.df) || isnan(Ft.df))
795 cond = 0;
796 else
797 cond = (Fs.df == Ft.df);
798 }});
799
800 0x3: c_ueq_d({{
801 if (isnan(Fs.df) || isnan(Ft.df))
802 cond = 1;
803 else
804 cond = (Fs.df == Ft.df);
805 }});
806
807 0x4: c_olt_d({{
808 if (isnan(Fs.df) || isnan(Ft.df))
809 cond = 0;
810 else
811 cond = (Fs.df < Ft.df);
812 }});
813
814 0x5: c_ult_d({{
815 if (isnan(Fs.df) || isnan(Ft.df))
816 cond = 1;
817 else
818 cond = (Fs.df < Ft.df);
819 }});
820
821 0x6: c_ole_d({{
822 if (isnan(Fs.df) || isnan(Ft.df))
823 cond = 0;
824 else
825 cond = (Fs.df <= Ft.df);
826 }});
827
828 0x7: c_ule_d({{
829 if (isnan(Fs.df) || isnan(Ft.df))
830 cond = 1;
831 else
832 cond = (Fs.df <= Ft.df);
833 }});
|
583 0x0: c_f_d({{ cond = 0; }}, DoublePrecision, 584 UnorderedFalse); 585 0x1: c_un_d({{ cond = 0; }}, DoublePrecision, 586 UnorderedTrue); 587 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 588 UnorderedFalse); 589 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 590 UnorderedTrue); 591 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 592 UnorderedFalse); 593 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 594 UnorderedTrue); 595 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 596 UnorderedFalse); 597 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 598 UnorderedTrue); |
599 } 600 } 601 602 0x7: decode FUNCTION_LO {
|
838 format FloatCompareWithXcptOp {
839 0x0: c_sf_d({{ cond = 0; }});
840
841 0x1: c_ngle_d({{
842 if (isnan(Fs.df) || isnan(Ft.df))
843 cond = 1;
844 else
845 cond = 0;
846 }});
847
848 0x2: c_seq_d({{
849 if (isnan(Fs.df) || isnan(Ft.df))
850 cond = 0;
851 else
852 cond = (Fs.df == Ft.df);
853 }});
854
855 0x3: c_ngl_d({{
856 if (isnan(Fs.df) || isnan(Ft.df))
857 cond = 1;
858 else
859 cond = (Fs.df == Ft.df);
860 }});
861
862 0x4: c_lt_d({{
863 if (isnan(Fs.df) || isnan(Ft.df))
864 cond = 0;
865 else
866 cond = (Fs.df < Ft.df);
867 }});
868
869 0x5: c_nge_d({{
870 if (isnan(Fs.df) || isnan(Ft.df))
871 cond = 1;
872 else
873 cond = (Fs.df < Ft.df);
874 }});
875
876 0x6: c_le_d({{
877 if (isnan(Fs.df) || isnan(Ft.df))
878 cond = 0;
879 else
880 cond = (Fs.df <= Ft.df);
881 }});
882
883 0x7: c_ngt_d({{
884 if (isnan(Fs.df) || isnan(Ft.df))
885 cond = 1;
886 else
887 cond = (Fs.df <= Ft.df);
888 }});
|
603 format FloatCompareOp { 604 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 605 UnorderedFalse, QnanException); 606 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 607 UnorderedTrue, QnanException); 608 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 609 UnorderedFalse, QnanException); 610 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 611 UnorderedTrue, QnanException); 612 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 613 UnorderedFalse, QnanException); 614 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 615 UnorderedTrue, QnanException); 616 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 617 UnorderedFalse, QnanException); 618 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 619 UnorderedTrue, QnanException); |
620 } 621 } 622 } 623 624 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 625 0x4: decode FUNCTION { 626 format FloatConvertOp {
|
896 0x20: cvt_s_w({{
897 Fd.uw = fpConvert(Fs.sf, WORD_TO_SINGLE);
898 }});
899
900 0x21: cvt_d_w({{
901 Fd.ud = fpConvert(Fs.sf, WORD_TO_DOUBLE);
902 }});
|
627 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 628 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 629 0x26: FailUnimpl::cvt_ps_w(); |
630 }
|
904
905 format Float64ConvertOp {
906 0x26: cvt_ps_pw({{
907 Fd.ud = fpConvert(Fs.ud, WORD_TO_PS);
908 }});
909 }
|
631 } 632 633 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 634 //Note: "1. Format type L is legal only if 64-bit floating point operations 635 //are enabled." 636 0x5: decode FUNCTION_HI {
|
916 format Float64ConvertOp {
917 0x20: cvt_s_l({{
918 Fd.uw = fpConvert(Fs.ud, LONG_TO_SINGLE);
919 }});
920
921 0x21: cvt_d_l({{
922 Fd.ud = fpConvert(Fs.ud, LONG_TO_DOUBLE);
923 }});
924
925 0x26: cvt_ps_l({{
926 Fd.ud = fpConvert(Fs.ud, LONG_TO_PS);
927 }});
|
637 format FloatConvertOp { 638 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 639 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 640 0x26: FailUnimpl::cvt_ps_l(); |
641 } 642 } 643 644 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 645 //Note: "1. Format type PS is legal only if 64-bit floating point operations 646 //are enabled. " 647 0x6: decode FUNCTION_HI { 648 0x0: decode FUNCTION_LO { 649 format Float64Op { 650 0x0: add_ps({{ 651 Fd1.sf = Fs1.sf + Ft2.sf; 652 Fd2.sf = Fs2.sf + Ft2.sf; 653 }});
|
941
|
654 0x1: sub_ps({{ 655 Fd1.sf = Fs1.sf - Ft2.sf; 656 Fd2.sf = Fs2.sf - Ft2.sf; 657 }});
|
946
|
658 0x2: mul_ps({{ 659 Fd1.sf = Fs1.sf * Ft2.sf; 660 Fd2.sf = Fs2.sf * Ft2.sf; 661 }});
|
951
|
662 0x5: abs_ps({{ 663 Fd1.sf = fabs(Fs1.sf); 664 Fd2.sf = fabs(Fs2.sf); 665 }});
|
956
|
666 0x6: mov_ps({{ 667 Fd1.sf = Fs1.sf; 668 Fd2.sf = Fs2.sf; 669 }});
|
961
|
670 0x7: neg_ps({{
|
963 Fd1.sf = -1 * Fs1.sf;
964 Fd2.sf = -1 * Fs2.sf;
|
671 Fd1.sf = -(Fs1.sf); 672 Fd2.sf = -(Fs2.sf); |
673 }}); 674 } 675 } 676 677 0x2: decode FUNCTION_LO { 678 0x1: decode MOVCF { 679 format Float64Op { 680 0x0: movf_ps({{
|
973 if (getFPConditionCode(FCSR, CC) == 0)
974 Fd1 = Fs1;
975 if (getFPConditionCode(FCSR, CC+1) == 0)
976 Fd2 = Fs2;
|
681 Fd1 = (getCondCode(FCSR, CC) == 0) ? 682 Fs1 : Fd1; 683 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 684 Fs2 : Fd2; |
685 }});
|
978
|
686 0x1: movt_ps({{
|
980 if (getFPConditionCode(FCSR, CC) == 1)
981 Fd1 = Fs1;
982 if (getFPConditionCode(FCSR, CC+1) == 1)
983 Fd2 = Fs2;
|
687 Fd2 = (getCondCode(FCSR, CC) == 1) ? 688 Fs1 : Fd1; 689 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 690 Fs2 : Fd2; |
691 }}); 692 } 693 } 694 695 format Float64Op { 696 0x2: movz_ps({{
|
990 if (getFPConditionCode(FCSR, CC) == 0)
991 Fd1 = Fs1;
992 if (getFPConditionCode(FCSR, CC) == 0)
993 Fd2 = Fs2;
|
697 Fd1 = (getCondCode(FCSR, CC) == 0) ? 698 Fs1 : Fd1; 699 Fd2 = (getCondCode(FCSR, CC) == 0) ? 700 Fs2 : Fd2; |
701 }});
|
995
|
702 0x3: movn_ps({{
|
997 if (getFPConditionCode(FCSR, CC) == 1)
998 Fd1 = Fs1;
999 if (getFPConditionCode(FCSR, CC) == 1)
1000 Fd2 = Fs2;
|
703 Fd1 = (getCondCode(FCSR, CC) == 1) ? 704 Fs1 : Fd1; 705 Fd2 = (getCondCode(FCSR, CC) == 1) ? 706 Fs2 : Fd2; |
707 }}); 708 } 709 710 } 711 712 0x4: decode FUNCTION_LO {
|
1007 0x0: Float64Op::cvt_s_pu({{
1008 Fd.uw = fpConvert(Fs2.uw, PU_TO_SINGLE);
1009 }});
|
713 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); |
714 } 715 716 0x5: decode FUNCTION_LO {
|
1013 format Float64Op {
1014 0x0: cvt_s_pl({{
1015 Fd.uw = fpConvert(Fs1.uw, PL_TO_SINGLE);
1016 }});
|
717 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); |
718
|
1018 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | Ft1.uw; }});
1019 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | Ft2.uw; }});
1020 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | Ft1.uw; }});
1021 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | Ft2.uw; }});
|
719 format Float64Op { 720 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 721 Ft1.uw; 722 }}); 723 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 724 Ft2.uw; 725 }}); 726 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 727 Ft1.uw; 728 }}); 729 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 730 Ft2.uw; 731 }}); |
732 } 733 } 734 735 0x6: decode FUNCTION_LO { 736 format FloatPSCompareOp {
|
1027 0x0: c_f_ps({{ cond1 = 0; cond2 = 0; }});
1028
1029 0x1: c_un_ps({{
1030 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1031 cond1 = 1;
1032 else
1033 cond1 = 0;
1034
1035 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1036 cond2 = 1;
1037 else
1038 cond2 = 0;
1039
1040 }});
1041
1042 0x2: c_eq_ps({{
1043 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1044 cond1 = 0;
1045 else
1046 cond1 = (Fs1.sf == Ft1.sf);
1047
1048 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1049 cond2 = 0;
1050 else
1051 cond2 = (Fs2.sf == Ft2.sf);
1052 }});
1053
1054 0x3: c_ueq_ps({{
1055 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1056 cond1 = 1;
1057 else
1058 cond1 = (Fs1.sf == Ft1.sf);
1059
1060 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1061 cond2 = 1;
1062 else
1063 cond2 = (Fs2.sf == Ft2.sf);
1064 }});
1065
1066 0x4: c_olt_ps({{
1067 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1068 cond1 = 0;
1069 else
1070 cond1 = (Fs1.sf < Ft1.sf);
1071
1072 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1073 cond2 = 0;
1074 else
1075 cond2 = (Fs2.sf < Ft2.sf);
1076 }});
1077
1078 0x5: c_ult_ps({{
1079 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1080 cond1 = 1;
1081 else
1082 cond1 = (Fs.sf < Ft.sf);
1083
1084 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1085 cond2 = 1;
1086 else
1087 cond2 = (Fs2.sf < Ft2.sf);
1088 }});
1089
1090 0x6: c_ole_ps({{
1091 if (isnan(Fs.sf) || isnan(Ft.sf))
1092 cond1 = 0;
1093 else
1094 cond1 = (Fs.sf <= Ft.sf);
1095
1096 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1097 cond2 = 0;
1098 else
1099 cond2 = (Fs2.sf <= Ft2.sf);
1100 }});
1101
1102 0x7: c_ule_ps({{
1103 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1104 cond1 = 1;
1105 else
1106 cond1 = (Fs1.sf <= Ft1.sf);
1107
1108 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1109 cond2 = 1;
1110 else
1111 cond2 = (Fs2.sf <= Ft2.sf);
1112 }});
|
737 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 738 UnorderedFalse); 739 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 740 UnorderedTrue); 741 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 742 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 743 UnorderedFalse); 744 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 745 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 746 UnorderedTrue); 747 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 748 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 749 UnorderedFalse); 750 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 751 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 752 UnorderedTrue); 753 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 754 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 755 UnorderedFalse); 756 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 757 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 758 UnorderedTrue); |
759 } 760 } 761 762 0x7: decode FUNCTION_LO {
|
1117 format FloatPSCompareWithXcptOp {
1118 0x0: c_sf_ps({{ cond1 = 0; cond2 = 0; }});
1119
1120 0x1: c_ngle_ps({{
1121 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1122 cond1 = 1;
1123 else
1124 cond1 = 0;
1125
1126 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1127 cond2 = 1;
1128 else
1129 cond2 = 0;
1130 }});
1131
1132 0x2: c_seq_ps({{
1133 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1134 cond1 = 0;
1135 else
1136 cond1 = (Fs1.sf == Ft1.sf);
1137
1138 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1139 cond2 = 0;
1140 else
1141 cond2 = (Fs2.sf == Ft2.sf);
1142 }});
1143
1144 0x3: c_ngl_ps({{
1145 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1146 cond1 = 1;
1147 else
1148 cond1 = (Fs1.sf == Ft1.sf);
1149
1150 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1151 cond2 = 1;
1152 else
1153 cond2 = (Fs2.sf == Ft2.sf);
1154 }});
1155
1156 0x4: c_lt_ps({{
1157 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1158 cond1 = 0;
1159 else
1160 cond1 = (Fs1.sf < Ft1.sf);
1161
1162 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1163 cond2 = 0;
1164 else
1165 cond2 = (Fs2.sf < Ft2.sf);
1166 }});
1167
1168 0x5: c_nge_ps({{
1169 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1170 cond1 = 1;
1171 else
1172 cond1 = (Fs1.sf < Ft1.sf);
1173
1174 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1175 cond2 = 1;
1176 else
1177 cond2 = (Fs2.sf < Ft2.sf);
1178 }});
1179
1180 0x6: c_le_ps({{
1181 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1182 cond1 = 0;
1183 else
1184 cond1 = (Fs1.sf <= Ft1.sf);
1185
1186 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1187 cond2 = 0;
1188 else
1189 cond2 = (Fs2.sf <= Ft2.sf);
1190 }});
1191
1192 0x7: c_ngt_ps({{
1193 if (isnan(Fs1.sf) || isnan(Ft1.sf))
1194 cond1 = 1;
1195 else
1196 cond1 = (Fs1.sf <= Ft1.sf);
1197
1198 if (isnan(Fs2.sf) || isnan(Ft2.sf))
1199 cond2 = 1;
1200 else
1201 cond2 = (Fs2.sf <= Ft2.sf);
1202 }});
|
763 format FloatPSCompareOp { 764 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 765 UnorderedFalse, QnanException); 766 0x1: c_ngle_ps({{ cond1 = 0; }}, 767 {{ cond2 = 0; }}, 768 UnorderedTrue, QnanException); 769 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 770 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 771 UnorderedFalse, QnanException); 772 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 773 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 774 UnorderedTrue, QnanException); 775 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 776 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 777 UnorderedFalse, QnanException); 778 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 779 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 780 UnorderedTrue, QnanException); 781 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 782 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 783 UnorderedFalse, QnanException); 784 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 785 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 786 UnorderedTrue, QnanException); |
787 } 788 } 789 } 790 } 791 } 792 } 793 794 //Table A-19 MIPS32 COP2 Encoding of rs Field 795 0x2: decode RS_MSB {
|
1212 0x0: decode RS_HI {
1213 0x0: decode RS_LO {
1214 format WarnUnimpl {
|
796 format FailUnimpl { 797 0x0: decode RS_HI { 798 0x0: decode RS_LO { |
799 0x0: mfc2(); 800 0x2: cfc2(); 801 0x3: mfhc2(); 802 0x4: mtc2(); 803 0x6: ctc2(); 804 0x7: mftc2(); 805 }
|
1222 }
|
806
|
1224 0x1: decode ND {
1225 0x0: decode TF {
1226 format WarnUnimpl {
|
807 0x1: decode ND { 808 0x0: decode TF { |
809 0x0: bc2f(); 810 0x1: bc2t(); 811 }
|
1230 }
|
812
|
1232 0x1: decode TF {
1233 format WarnUnimpl {
|
813 0x1: decode TF { |
814 0x0: bc2fl(); 815 0x1: bc2tl(); 816 } 817 } 818 } 819 } 820 } 821 822 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 823 //Note: "COP1X instructions are legal only if 64-bit floating point 824 //operations are enabled." 825 0x3: decode FUNCTION_HI { 826 0x0: decode FUNCTION_LO {
|
1247 format LoadFloatMemory {
1248 0x0: lwxc1({{ Ft.uw = Mem.uw;}}, {{ EA = Rs + Rt; }});
1249 0x1: ldxc1({{ Ft.ud = Mem.ud;}}, {{ EA = Rs + Rt; }});
1250 0x5: luxc1({{ Ft.uw = Mem.ud;}}, {{ EA = Rs + Rt; }});
|
827 format LoadIndexedMemory { 828 0x0: lwxc1({{ Ft.uw = Mem.uw;}}); 829 0x1: ldxc1({{ Ft.ud = Mem.ud;}}); 830 0x5: luxc1({{ Ft.uw = Mem.ud;}}); |
831 } 832 } 833 834 0x1: decode FUNCTION_LO {
|
1255 format StoreFloatMemory {
1256 0x0: swxc1({{ Mem.uw = Ft.uw;}}, {{ EA = Rs + Rt; }});
1257 0x1: sdxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }});
1258 0x5: suxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }});
|
835 format StoreIndexedMemory { 836 0x0: swxc1({{ Mem.uw = Ft.uw;}}); 837 0x1: sdxc1({{ Mem.ud = Ft.ud;}}); 838 0x5: suxc1({{ Mem.ud = Ft.ud;}}); |
839 } 840
|
1261 0x7: WarnUnimpl::prefx();
|
841 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); |
842 } 843
|
1264 format FloatOp {
1265 0x3: WarnUnimpl::alnv_ps();
|
844 0x3: decode FUNCTION_LO { 845 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) { 846 Fd.ud = Fs.ud; 847 } else if (Rs<2:0> == 4) { 848 #if BYTE_ORDER == BIG_ENDIAN 849 Fd.ud = Fs.ud<31:0> << 32 | 850 Ft.ud<63:32>; 851 #elif BYTE_ORDER == LITTLE_ENDIAN 852 Fd.ud = Ft.ud<31:0> << 32 | 853 Fs.ud<63:32>; 854 #endif 855 } else { 856 Fd.ud = Fd.ud; 857 } 858 }}); 859 } |
860
|
1267 format BasicOp {
1268 0x4: decode FUNCTION_LO {
1269 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
1270 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
1271 0x6: madd_ps({{
1272 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
1273 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
1274 }});
1275 }
|
861 format FloatAccOp { 862 0x4: decode FUNCTION_LO { 863 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 864 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 865 0x6: madd_ps({{ 866 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 867 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 868 }}); 869 } |
870
|
1277 0x5: decode FUNCTION_LO {
1278 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
1279 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
1280 0x6: msub_ps({{
1281 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
1282 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
1283 }});
1284 }
|
871 0x5: decode FUNCTION_LO { 872 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 873 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 874 0x6: msub_ps({{ 875 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 876 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 877 }}); 878 } |
879
|
1286 0x6: decode FUNCTION_LO {
1287 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1288 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
1289 0x6: nmadd_ps({{
1290 Fd1.sf = -1 * ((Fs1.df * Ft1.df) + Fr1.df);
1291 Fd2.sf = -1 * ((Fs2.df * Ft2.df) + Fr2.df);
1292 }});
1293 }
|
880 0x6: decode FUNCTION_LO { 881 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 882 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 883 0x6: nmadd_ps({{ 884 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 885 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 886 }}); 887 } |
888
|
1295 0x7: decode FUNCTION_LO {
1296 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1297 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
1298 0x6: nmsub_ps({{
1299 Fd1.sf = -1 * ((Fs1.df * Ft1.df) - Fr1.df);
1300 Fd2.sf = -1 * ((Fs2.df * Ft2.df) - Fr2.df);
1301 }});
1302 }
|
889 0x7: decode FUNCTION_LO { 890 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 891 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 892 0x6: nmsub_ps({{ 893 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 894 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 895 }}); |
896 }
|
897 |
898 } 899 } 900
|
1307 format BranchLikely {
1308 0x4: beql({{ cond = (Rs.sw == 0); }});
1309 0x5: bnel({{ cond = (Rs.sw != 0); }});
1310 0x6: blezl({{ cond = (Rs.sw <= 0); }});
1311 0x7: bgtzl({{ cond = (Rs.sw > 0); }});
|
901 format Branch { 902 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 903 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 904 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 905 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); |
906 } 907 } 908
|
1315 0x3: decode OPCODE_LO default FailUnimpl::reserved() {
1316
|
909 0x3: decode OPCODE_LO { |
910 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 911 0x4: decode FUNCTION_HI {
|
1319
|
912 0x0: decode FUNCTION_LO {
|
1321 format IntOp {
1322 0x0: madd({{
1323 int64_t temp1 = (int64_t) HI << 32 | LO;
1324 temp1 = temp1 + (Rs.sw * Rt.sw);
1325 HI = temp1<63:32>;
1326 LO = temp1<31:0>;
1327 }});
|
913 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; 914 Rd.sw = temp1<31:0> 915 }}); |
916
|
1329 0x1: maddu({{
1330 int64_t temp1 = (int64_t) HI << 32 | LO;
1331 temp1 = temp1 + (Rs.uw * Rt.uw);
1332 HI = temp1<63:32>;
1333 LO = temp1<31:0>;
1334 }});
1335
1336 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
1337
1338 0x4: msub({{
1339 int64_t temp1 = (int64_t) HI << 32 | LO;
1340 temp1 = temp1 - (Rs.sw * Rt.sw);
1341 HI = temp1<63:32>;
1342 LO = temp1<31:0>;
1343 }});
1344
1345 0x5: msubu({{
1346 int64_t temp1 = (int64_t) HI << 32 | LO;
1347 temp1 = temp1 - (Rs.uw * Rt.uw);
1348 HI = temp1<63:32>;
1349 LO = temp1<31:0>;
1350 }});
|
917 format HiLoOp { 918 0x0: madd({{ val = ((int64_t) HI << 32 | LO) + 919 (Rs.sd * Rt.sd); 920 }}); 921 0x1: maddu({{ val = ((uint64_t) HI << 32 | LO) + 922 (Rs.ud * Rt.ud); 923 }}); 924 0x4: msub({{ val = ((int64_t) HI << 32 | LO) - 925 (Rs.sd * Rt.sd); 926 }}); 927 0x5: msubu({{ val = ((uint64_t) HI << 32 | LO) - 928 (Rs.ud * Rt.ud); 929 }}); |
930 } 931 } 932 933 0x4: decode FUNCTION_LO { 934 format BasicOp {
|
1356 0x0: clz({{
1357 int cnt = 0;
1358 uint32_t mask = 0x80000000;
1359 for (int i=0; i < 32; i++) {
1360 if( (Rs & mask) == 0) {
1361 cnt++;
1362 } else {
1363 break;
1364 }
1365 }
1366 Rd.uw = cnt;
1367 }});
1368
1369 0x1: clo({{
1370 int cnt = 0;
1371 uint32_t mask = 0x80000000;
1372 for (int i=0; i < 32; i++) {
1373 if( (Rs & mask) != 0) {
1374 cnt++;
1375 } else {
1376 break;
1377 }
1378 }
1379 Rd.uw = cnt;
1380 }});
|
935 0x0: clz({{ int cnt = 32; 936 for (int idx = 31; idx >= 0; idx--) { 937 if( Rs<idx:idx> == 1) { 938 cnt = 31 - idx; 939 break; 940 } 941 } 942 Rd.uw = cnt; 943 }}); 944 0x1: clo({{ int cnt = 32; 945 for (int idx = 31; idx >= 0; idx--) { 946 if( Rs<idx:idx> == 0) { 947 cnt = 31 - idx; 948 break; 949 } 950 } 951 Rd.uw = cnt; 952 }}); |
953 } 954 } 955 956 0x7: decode FUNCTION_LO {
|
1385 0x7: WarnUnimpl::sdbbp();
|
957 0x7: FailUnimpl::sdbbp(); |
958 } 959 } 960
|
1389 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
|
961 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 962 //of the Architecture |
963 0x7: decode FUNCTION_HI {
|
1391
|
964 0x0: decode FUNCTION_LO {
|
1393 format FailUnimpl {
1394 0x1: ext();
1395 0x4: ins();
|
965 format BasicOp { 966 0x1: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 967 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 968 bits(Rs.uw, MSB-LSB, 0) << LSB | 969 bits(Rt.uw, LSB-1, 0); 970 }}); |
971 } 972 } 973 974 0x1: decode FUNCTION_LO {
|
1400 format FailUnimpl {
|
975 format MipsMT { |
976 0x0: fork(); 977 0x1: yield(); 978 } 979 } 980
|
1406
|
981 //Table A-10 MIPS32 BSHFL Encoding of sa Field 982 0x4: decode SA {
|
1409
1410 0x02: FailUnimpl::wsbh();
1411
|
983 format BasicOp {
|
984 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | 985 Rt.uw<31:24> << 16 | 986 Rt.uw<7:0> << 8 | 987 Rt.uw<15:8>; 988 }}); |
989 0x10: seb({{ Rd.sw = Rt.sw<7:0>}}); 990 0x18: seh({{ Rd.sw = Rt.sw<15:0>}}); 991 } 992 } 993 994 0x6: decode FUNCTION_LO {
|
1419 0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }}
|
995 0x7: FailUnimpl::rdhwr(); |
996 } 997 } 998 } 999
|
1424 0x4: decode OPCODE_LO default FailUnimpl::reserved() {
|
1000 0x4: decode OPCODE_LO { |
1001 format LoadMemory { 1002 0x0: lb({{ Rt.sw = Mem.sb; }}); 1003 0x1: lh({{ Rt.sw = Mem.sh; }});
|
1428
1429 0x2: lwl({{
1430 uint32_t mem_word = Mem.uw;
1431 uint32_t unalign_addr = Rs + disp;
1432 uint32_t offset = unalign_addr & 0x00000003;
1433#if BYTE_ORDER == BIG_ENDIAN
1434 switch(offset)
1435 {
1436 case 0:
1437 Rt = mem_word;
1438 break;
1439
1440 case 1:
1441 Rt &= 0x000F;
1442 Rt |= (mem_word << 4);
1443 break;
1444
1445 case 2:
1446 Rt &= 0x00FF;
1447 Rt |= (mem_word << 8);
1448 break;
1449
1450 case 3:
1451 Rt &= 0x0FFF;
1452 Rt |= (mem_word << 12);
1453 break;
1454
1455 default:
1456 panic("lwl: bad offset");
1457 }
1458#elif BYTE_ORDER == LITTLE_ENDIAN
1459 switch(offset)
1460 {
1461 case 0:
1462 Rt &= 0x0FFF;
1463 Rt |= (mem_word << 12);
1464 break;
1465
1466 case 1:
1467 Rt &= 0x00FF;
1468 Rt |= (mem_word << 8);
1469 break;
1470
1471 case 2:
1472 Rt &= 0x000F;
1473 Rt |= (mem_word << 4);
1474 break;
1475
1476 case 3:
1477 Rt = mem_word;
1478 break;
1479
1480 default:
1481 panic("lwl: bad offset");
1482 }
1483#endif
1484 }}, {{ EA = (Rs + disp) & ~3; }});
1485
|
1004 0x3: lw({{ Rt.sw = Mem.sw; }}); 1005 0x4: lbu({{ Rt.uw = Mem.ub; }}); 1006 0x5: lhu({{ Rt.uw = Mem.uh; }});
|
1489 0x6: lwr({{
1490 uint32_t mem_word = Mem.uw;
1491 uint32_t unalign_addr = Rs + disp;
1492 uint32_t offset = unalign_addr & 0x00000003;
|
1007 } |
1008
|
1494#if BYTE_ORDER == BIG_ENDIAN
1495 switch(offset)
1496 {
1497 case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break;
1498 case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break;
1499 case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break;
1500 case 3: Rt = mem_word; break;
1501 default: panic("lwr: bad offset");
1502 }
1503#elif BYTE_ORDER == LITTLE_ENDIAN
1504 switch(offset)
1505 {
1506 case 0: Rt = mem_word; break;
1507 case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break;
1508 case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break;
1509 case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break;
1510 default: panic("lwr: bad offset");
1511 }
1512#endif
1513 }},
1514 {{ EA = (Rs + disp) & ~3; }});
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1009 format LoadUnalignedMemory { 1010 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); 1011 Rt.uw = mem_word << mem_shift | 1012 Rt.uw & mask(mem_shift); 1013 }}); 1014 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; 1015 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) | 1016 mem_word >> mem_shift; 1017 }}); |
1018 } 1019 } 1020
|
1518 0x5: decode OPCODE_LO default FailUnimpl::reserved() {
|
1021 0x5: decode OPCODE_LO { |
1022 format StoreMemory { 1023 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 1024 0x1: sh({{ Mem.uh = Rt<15:0>; }});
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1522 0x2: swl({{
1523 uint32_t mem_word = 0;
1524 uint32_t aligned_addr = (Rs + disp) & ~3;
1525 uint32_t unalign_addr = Rs + disp;
1526 uint32_t offset = unalign_addr & 0x00000003;
1527
1528 DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x",
1529 aligned_addr,unalign_addr,offset);
1530
1531 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
1532
1533#if BYTE_ORDER == BIG_ENDIAN
1534 switch(offset)
1535 {
1536 case 0:
1537 Mem = Rt;
1538 break;
1539
1540 case 1:
1541 mem_word &= 0xF000;
1542 mem_word |= (Rt >> 4);
1543 Mem = mem_word;
1544 break;
1545
1546 case 2:
1547 mem_word &= 0xFF00;
1548 mem_word |= (Rt >> 8);
1549 Mem = mem_word;
1550 break;
1551
1552 case 3:
1553 mem_word &= 0xFFF0;
1554 mem_word |= (Rt >> 12);
1555 Mem = mem_word;
1556 break;
1557
1558 default:
1559 panic("swl: bad offset");
1560 }
1561#elif BYTE_ORDER == LITTLE_ENDIAN
1562 switch(offset)
1563 {
1564 case 0:
1565 mem_word &= 0xFFF0;
1566 mem_word |= (Rt >> 12);
1567 Mem = mem_word;
1568 break;
1569
1570 case 1:
1571 mem_word &= 0xFF00;
1572 mem_word |= (Rt >> 8);
1573 Mem = mem_word;
1574 break;
1575
1576 case 2:
1577 mem_word &= 0xF000;
1578 mem_word |= (Rt >> 4);
1579 Mem = mem_word;
1580 break;
1581
1582 case 3:
1583 Mem = Rt;
1584 break;
1585
1586 default:
1587 panic("swl: bad offset");
1588 }
1589#endif
1590 }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT);
1591
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1025 0x3: sw({{ Mem.uw = Rt<31:0>; }});
|
1593
1594 0x6: swr({{
1595 uint32_t mem_word = 0;
1596 uint32_t aligned_addr = (Rs + disp) & ~3;
1597 uint32_t unalign_addr = Rs + disp;
1598 uint32_t offset = unalign_addr & 0x00000003;
1599
1600 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
1601
1602#if BYTE_ORDER == BIG_ENDIAN
1603 switch(offset)
1604 {
1605 case 0:
1606 mem_word &= 0x0FFF;
1607 mem_word |= (Rt << 12);
1608 Mem = mem_word;
1609 break;
1610
1611 case 1:
1612 mem_word &= 0x00FF;
1613 mem_word |= (Rt << 8);
1614 Mem = mem_word;
1615 break;
1616
1617 case 2:
1618 mem_word &= 0x000F;
1619 mem_word |= (Rt << 4);
1620 Mem = mem_word;
1621 break;
1622
1623 case 3:
1624 Mem = Rt;
1625 break;
1626
1627 default:
1628 panic("swr: bad offset");
1629 }
1630#elif BYTE_ORDER == LITTLE_ENDIAN
1631 switch(offset)
1632 {
1633 case 0:
1634 Mem = Rt;
1635 break;
1636
1637 case 1:
1638 mem_word &= 0x000F;
1639 mem_word |= (Rt << 4);
1640 Mem = mem_word;
1641 break;
1642
1643 case 2:
1644 mem_word &= 0x00FF;
1645 mem_word |= (Rt << 8);
1646 Mem = mem_word;
1647 break;
1648
1649 case 3:
1650 mem_word &= 0x0FFF;
1651 mem_word |= (Rt << 12);
1652 Mem = mem_word;
1653 break;
1654
1655 default:
1656 panic("swr: bad offset");
1657 }
1658#endif
1659 }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT);
|
1026 } 1027
|
1662 format WarnUnimpl {
1663 0x7: cache();
|
1028 format StoreUnalignedMemory { 1029 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); 1030 uint32_t mem_shift = 32 - reg_shift; 1031 mem_word = mem_word & (mask(reg_shift) << mem_shift) | 1032 Rt.uw >> reg_shift; 1033 }}); 1034 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; 1035 mem_word = Rt.uw << reg_shift | 1036 mem_word & (mask(reg_shift)); 1037 }}); |
1038 } 1039
|
1040 0x7: FailUnimpl::cache(); |
1041 } 1042
|
1668 0x6: decode OPCODE_LO default FailUnimpl::reserved() {
1669 0x0: LoadMemory::ll({{Rt.uw = Mem.uw}},mem_flags=LOCKED);
1670
1671 format LoadFloatMemory {
1672 0x1: lwc1({{ Ft.uw = Mem.uw; }});
|
1043 0x6: decode OPCODE_LO { 1044 format LoadMemory { 1045 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED); 1046 0x1: lwc1({{ Ft.uw = Mem.uw; }}); |
1047 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 1048 }
|
1049 1050 0x3: Prefetch::pref(); |
1051 } 1052 1053
|
1678 0x7: decode OPCODE_LO default FailUnimpl::reserved() {
1679 0x0: StoreMemory::sc({{ Mem.uw = Rt.uw; Rt.uw = 1; }});
|
1054 0x7: decode OPCODE_LO { 1055 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, 1056 {{ uint64_t tmp = write_result; 1057 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 1058 }}, mem_flags=LOCKED); |
1059
|
1681 format StoreFloatMemory {
|
1060 format StoreMemory { |
1061 0x1: swc1({{ Mem.uw = Ft.uw; }}); 1062 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 1063 } 1064 } 1065} 1066 1067
|