1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 149 unchanged lines hidden (view full) --- 158 NNPC = Rs; 159 }}, IsCall); 160 } 161 } 162 163 format BasicOp { 164 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 165 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); |
166 0x4: decode FullSystem { |
167 0: syscall_se({{ xc->syscall(R2); }}, 168 IsSerializeAfter, IsNonSpeculative); 169 default: syscall({{ fault = new SystemCallFault(); }}); 170 } 171 0x7: sync({{ ; }}, IsMemBarrier); 172 0x5: break({{fault = new BreakpointFault();}}); 173 } 174 --- 32 unchanged lines hidden (view full) --- 207 } 208 209 0x4: decode HINT { 210 0x0: decode FUNCTION_LO { 211 format IntOp { 212 0x0: add({{ 213 IntReg result; 214 Rd = result = Rs + Rt; |
215 if (FullSystem && |
216 findOverflow(32, result, Rs, Rt)) { 217 fault = new IntegerOverflowFault(); 218 } 219 }}); 220 0x1: addu({{ Rd_sw = Rs_sw + Rt_sw;}}); 221 0x2: sub({{ 222 IntReg result; 223 Rd = result = Rs - Rt; |
224 if (FullSystem && |
225 findOverflow(32, result, Rs, ~Rt)) { 226 fault = new IntegerOverflowFault(); 227 } 228 }}); 229 0x3: subu({{ Rd_sw = Rs_sw - Rt_sw; }}); 230 0x4: and({{ Rd = Rs & Rt; }}); 231 0x5: or({{ Rd = Rs | Rt; }}); 232 0x6: xor({{ Rd = Rs ^ Rt; }}); --- 87 unchanged lines hidden (view full) --- 320 } 321 } 322 323 0x1: decode OPCODE_LO { 324 format IntImmOp { 325 0x0: addi({{ 326 IntReg result; 327 Rt = result = Rs + imm; |
328 if (FullSystem && |
329 findOverflow(32, result, Rs, imm)) { 330 fault = new IntegerOverflowFault(); 331 } 332 }}); 333 0x1: addiu({{ Rt_sw = Rs_sw + imm; }}); 334 0x2: slti({{ Rt_sw = (Rs_sw < imm) ? 1 : 0 }}); 335 0x3: sltiu({{ Rt_uw = (Rs_uw < (uint32_t)sextImm) ? 1 : 0;}}); 336 0x4: andi({{ Rt_sw = Rs_sw & zextImm; }}); --- 155 unchanged lines hidden (view full) --- 492 }}); 493 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); 494 default: CP0Unimpl::unknown(); 495 496 } 497 0x2: mttc1({{ 498 uint64_t data = xc->readRegOtherThread(RD + 499 FP_Base_DepTag); |
500 data = insertBits(data, top_bit, 501 bottom_bit, Rt); |
502 xc->setRegOtherThread(RD + FP_Base_DepTag, 503 data); 504 }}); 505 0x3: cttc1({{ 506 uint32_t data; 507 switch (RD) { 508 case 25: 509 data = (Rt_uw<7:1> << 25) | // move 31-25 --- 17 unchanged lines hidden (view full) --- 527 break; 528 case 31: 529 data = Rt_uw; 530 break; 531 default: 532 panic("FP Control Value (%d) " 533 "Not Available. Ignoring " 534 "Access to Floating Control " |
535 "Status Register", FS); |
536 } 537 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); 538 }}); 539 default: CP0Unimpl::unknown(); 540 } 541 } 542 } 543 0xB: decode RD { --- 227 unchanged lines hidden (view full) --- 771 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 772 Config3Reg config3 = Config3; 773 PageGrainReg pageGrain = PageGrain; 774 int SP = 0; 775 if (bits(config3, config3.sp) == 1 && 776 bits(pageGrain, pageGrain.esp) == 1) { 777 SP = 1; 778 } |
779 IndexReg index = Index; |
780 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 781 }}); 782 0x06: tlbwr({{ 783 //Create PTE 784 MipsISA::PTE newEntry; 785 //Write PTE 786 newEntry.Mask = (Addr)(PageMask >> 11); 787 newEntry.VPN = (Addr)(EntryHi >> 11); --- 49 unchanged lines hidden (view full) --- 837 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 838 Config3Reg config3 = Config3; 839 PageGrainReg pageGrain = PageGrain; 840 int SP = 0; 841 if (bits(config3, config3.sp) == 1 && 842 bits(pageGrain, pageGrain.esp) == 1) { 843 SP = 1; 844 } |
845 IndexReg index = Index; |
846 Ptr->insertAt(newEntry, Random, SP); 847 }}); 848 849 0x08: tlbp({{ 850 Config3Reg config3 = Config3; 851 PageGrainReg pageGrain = PageGrain; 852 EntryHiReg entryHi = EntryHi; 853 int tlbIndex; --- 396 unchanged lines hidden (view full) --- 1250 } 1251 default: CP1Unimpl::unknown(); 1252 } 1253 1254 //Table A-16 MIPS32 COP1 Encoding of Function Field 1255 //When rs=L1 1256 //Note: "1. Format type L is legal only if 64-bit 1257 //floating point operations are enabled." |
1258 0x5: decode FUNCTION_HI { |
1259 format FloatConvertOp { 1260 0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle); 1261 0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble); 1262 0x26: CP1Unimpl::cvt_ps_l(); 1263 } 1264 default: CP1Unimpl::unknown(); 1265 } 1266 --- 1161 unchanged lines hidden (view full) --- 2428 dspac |= Rs_uw; 2429 dspctl = insertBits(dspctl, 5, 0, 2430 dspctl<5:0> + 32); 2431 }}); 2432 } 2433 } 2434 } 2435 0x3: decode OP default FailUnimpl::rdhwr() { |
2436 0x0: decode FullSystem { |
2437 0: decode RD { 2438 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2439 } 2440 } 2441 } 2442 } 2443 } 2444 } --- 79 unchanged lines hidden --- |