1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 149 unchanged lines hidden (view full) --- 158 NNPC = Rs; 159 }}, IsCall); 160 } 161 } 162 163 format BasicOp { 164 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 165 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); |
166 0x4: decode FULL_SYSTEM { 167 0: syscall_se({{ xc->syscall(R2); }}, 168 IsSerializeAfter, IsNonSpeculative); 169 default: syscall({{ fault = new SystemCallFault(); }}); 170 } |
171 0x7: sync({{ ; }}, IsMemBarrier); 172 0x5: break({{fault = new BreakpointFault();}}); 173 } 174 175 } 176 177 0x2: decode FUNCTION_LO { 178 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, --- 26 unchanged lines hidden (view full) --- 205 }}, IntDivOp); 206 } 207 } 208 209 0x4: decode HINT { 210 0x0: decode FUNCTION_LO { 211 format IntOp { 212 0x0: add({{ |
213 IntReg result; 214 Rd = result = Rs + Rt; 215 if (FULL_SYSTEM && 216 findOverflow(32, result, Rs, Rt)) { |
217 fault = new ArithmeticFault(); 218 } |
219 }}); 220 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 221 0x2: sub({{ |
222 IntReg result; 223 Rd = result = Rs - Rt; 224 if (FULL_SYSTEM && 225 findOverflow(32, result, Rs, ~Rt)) { |
226 fault = new ArithmeticFault(); 227 } |
228 }}); 229 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw; }}); 230 0x4: and({{ Rd = Rs & Rt; }}); 231 0x5: or({{ Rd = Rs | Rt; }}); 232 0x6: xor({{ Rd = Rs ^ Rt; }}); 233 0x7: nor({{ Rd = ~(Rs | Rt); }}); 234 } 235 } --- 82 unchanged lines hidden (view full) --- 318 0x6: blez({{ cond = (Rs.sw <= 0); }}); 319 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 320 } 321 } 322 323 0x1: decode OPCODE_LO { 324 format IntImmOp { 325 0x0: addi({{ |
326 IntReg result; 327 Rt = result = Rs + imm; 328 if (FULL_SYSTEM && 329 findOverflow(32, result, Rs, imm)) { |
330 fault = new ArithmeticFault(); 331 } |
332 }}); 333 0x1: addiu({{ Rt.sw = Rs.sw + imm; }}); 334 0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }}); 335 0x3: sltiu({{ Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0;}}); 336 0x4: andi({{ Rt.sw = Rs.sw & zextImm; }}); 337 0x5: ori({{ Rt.sw = Rs.sw | zextImm; }}); 338 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm; }}); 339 --- 1136 unchanged lines hidden (view full) --- 1476 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1477 } 1478 1479 0x3: decode FUNCTION_LO { 1480 0x6: Float64Op::alnv_ps({{ 1481 if (Rs<2:0> == 0) { 1482 Fd.ud = Fs.ud; 1483 } else if (Rs<2:0> == 4) { |
1484 if (GuestByteOrder == BigEndianByteOrder) 1485 Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>; 1486 else 1487 Fd.ud = Ft.ud<31:0> << 32 | Fs.ud<63:32>; |
1488 } else { 1489 Fd.ud = Fd.ud; 1490 } 1491 }}); 1492 } 1493 1494 format FloatAccOp { 1495 0x4: decode FUNCTION_LO { --- 931 unchanged lines hidden (view full) --- 2427 dspac = dspac << 32; 2428 dspac |= Rs.uw; 2429 dspctl = insertBits(dspctl, 5, 0, 2430 dspctl<5:0> + 32); 2431 }}); 2432 } 2433 } 2434 } |
2435 0x3: decode OP default FailUnimpl::rdhwr() { 2436 0x0: decode FULL_SYSTEM { 2437 0: decode RD { 2438 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2439 } |
2440 } |
2441 } 2442 } 2443 } 2444 } 2445 2446 0x4: decode OPCODE_LO { 2447 format LoadMemory { 2448 0x0: lb({{ Rt.sw = Mem.sb; }}); --- 75 unchanged lines hidden --- |