1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 119 unchanged lines hidden (view full) --- 128 0x1: decode FUNCTION_LO { 129 //Table A-3 Note: "Specific encodings of the hint field are 130 //used to distinguish JR from JR.HB and JALR from JALR.HB" 131 format Jump { 132 0x0: decode HINT { 133 0x1: jr_hb({{ 134 Config1Reg config1 = Config1; 135 if (config1.ca == 0) { |
136 NNPC = Rs; |
137 } else { 138 panic("MIPS16e not supported\n"); 139 } |
140 }}, IsReturn, ClearHazards); 141 default: jr({{ 142 Config1Reg config1 = Config1; 143 if (config1.ca == 0) { |
144 NNPC = Rs; |
145 } else { 146 panic("MIPS16e not supported\n"); 147 } |
148 }}, IsReturn); 149 } 150 151 0x1: decode HINT { 152 0x1: jalr_hb({{ |
153 Rd = NNPC; 154 NNPC = Rs; |
155 }}, IsCall, ClearHazards); 156 default: jalr({{ |
157 Rd = NNPC; 158 NNPC = Rs; |
159 }}, IsCall); 160 } 161 } 162 163 format BasicOp { 164 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 165 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 166#if FULL_SYSTEM --- 156 unchanged lines hidden (view full) --- 323 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 324 format WarnUnimpl { 325 0x7: synci(); 326 } 327 } 328 } 329 330 format Jump { |
331 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}); 332 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, 333 IsCall, Link); |
334 } 335 336 format Branch { 337 0x4: decode RS_RT { 338 0x0: b({{ cond = 1; }}); 339 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 340 } 341 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); --- 352 unchanged lines hidden (view full) --- 694 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 695 0x1: decode FUNCTION { 696 format CP0Control { 697 0x18: eret({{ 698 StatusReg status = Status; 699 ConfigReg config = Config; 700 SRSCtlReg srsCtl = SRSCtl; 701 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); |
702 if (status.erl == 1) { 703 status.erl = 0; |
704 NPC = ErrorEPC; |
705 // Need to adjust NNPC, otherwise things break |
706 NNPC = ErrorEPC + sizeof(MachInst); |
707 } else { |
708 NPC = EPC; |
709 // Need to adjust NNPC, otherwise things break |
710 NNPC = EPC + sizeof(MachInst); |
711 status.exl = 0; 712 if (config.ar >=1 && 713 srsCtl.hss > 0 && 714 status.bev == 0) { 715 srsCtl.css = srsCtl.pss; 716 //xc->setShadowSet(srsCtl.pss); 717 } 718 } |
719 LLFlag = 0; 720 Status = status; 721 SRSCtl = srsCtl; 722 }}, IsReturn, IsSerializing, IsERET); 723 724 0x1F: deret({{ 725 DebugReg debug = Debug; |
726 if (debug.dm == 1) { 727 debug.dm = 1; 728 debug.iexi = 0; |
729 NPC = DEPC; |
730 } else { |
731 NPC = NPC; |
732 // Undefined; 733 } |
734 Debug = debug; 735 }}, IsReturn, IsSerializing, IsERET); 736 } 737 format CP0TLB { 738 0x01: tlbr({{ 739 MipsISA::PTE *PTEntry = 740 xc->tcBase()->getITBPtr()-> 741 getEntry(Index & 0x7FFFFFFF); --- 1834 unchanged lines hidden --- |