1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 723 unchanged lines hidden (view full) --- 732 // Undefined; 733 } 734 Debug = debug; 735 }}, IsReturn, IsSerializing, IsERET); 736 } 737 format CP0TLB { 738 0x01: tlbr({{ 739 MipsISA::PTE *PTEntry = |
740 dynamic_cast<MipsISA::TLB *>( 741 xc->tcBase()->getITBPtr())-> |
742 getEntry(Index & 0x7FFFFFFF); 743 if (PTEntry == NULL) { 744 fatal("Invalid PTE Entry received on " 745 "a TLBR instruction\n"); 746 } 747 /* Setup PageMask */ 748 // If 1KB pages are not enabled, a read of PageMask 749 // must return 0b00 in bits 12, 11 --- 63 unchanged lines hidden (view full) --- 813 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 814 newEntry.AddrShiftAmount = 28; 815 } else { 816 fatal("Invalid Mask Pattern Detected!\n"); 817 } 818 newEntry.OffsetMask = 819 (1 << newEntry.AddrShiftAmount) - 1; 820 |
821 auto ptr = dynamic_cast<MipsISA::TLB *>( 822 xc->tcBase()->getITBPtr()); |
823 Config3Reg config3 = Config3; 824 PageGrainReg pageGrain = PageGrain; 825 int SP = 0; 826 if (bits(config3, config3.sp) == 1 && 827 bits(pageGrain, pageGrain.esp) == 1) { 828 SP = 1; 829 } |
830 ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); |
831 }}); 832 0x06: tlbwr({{ 833 //Create PTE 834 MipsISA::PTE newEntry; 835 //Write PTE 836 newEntry.Mask = (Addr)(PageMask >> 11); 837 newEntry.VPN = (Addr)(EntryHi >> 11); 838 /* PageGrain _ ESP Config3 _ SP */ --- 40 unchanged lines hidden (view full) --- 879 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 880 newEntry.AddrShiftAmount = 28; 881 } else { 882 fatal("Invalid Mask Pattern Detected!\n"); 883 } 884 newEntry.OffsetMask = 885 (1 << newEntry.AddrShiftAmount) - 1; 886 |
887 auto ptr = dynamic_cast<MipsISA::TLB *>( 888 xc->tcBase()->getITBPtr()); |
889 Config3Reg config3 = Config3; 890 PageGrainReg pageGrain = PageGrain; 891 int SP = 0; 892 if (bits(config3, config3.sp) == 1 && 893 bits(pageGrain, pageGrain.esp) == 1) { 894 SP = 1; 895 } |
896 ptr->insertAt(newEntry, Random, SP); |
897 }}); 898 899 0x08: tlbp({{ 900 Config3Reg config3 = Config3; 901 PageGrainReg pageGrain = PageGrain; 902 EntryHiReg entryHi = EntryHi; 903 int tlbIndex; 904 Addr vpn; 905 if (pageGrain.esp == 1 && config3.sp ==1) { 906 vpn = EntryHi >> 11; 907 } else { 908 // Mask off lower 2 bits 909 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 910 } |
911 tlbIndex = dynamic_cast<MipsISA::TLB *>( 912 xc->tcBase()->getITBPtr())-> 913 probeEntry(vpn, entryHi.asid); |
914 // Check TLB for entry matching EntryHi 915 if (tlbIndex != -1) { 916 Index = tlbIndex; 917 } else { 918 // else, set Index = 1 << 31 919 Index = (1 << 31); 920 } 921 }}); --- 1653 unchanged lines hidden --- |