1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 370 unchanged lines hidden (view full) --- 379 0x1: dmfc0(); 380 0x5: dmtc0(); 381 default: unknown(); 382 } 383 format MT_MFTR { 384 // Decode MIPS MT MFTR instruction into sub-instructions 385 0x8: decode MT_U { 386 0x0: mftc0({{ |
387 data = xc->readRegOtherThread(RegId(MiscRegClass, 388 (RT << 3 | SEL))); |
389 }}); 390 0x1: decode SEL { 391 0x0: mftgpr({{ |
392 data = xc->readRegOtherThread( 393 RegId(IntRegClass, RT)); |
394 }}); 395 0x1: decode RT { |
396 0x0: mftlo_dsp0({{ 397 data = xc->readRegOtherThread( 398 RegId(IntRegClass, INTREG_DSP_LO0)); 399 }}); 400 0x1: mfthi_dsp0({{ 401 data = xc->readRegOtherThread( 402 RegId(IntRegClass, INTREG_DSP_HI0)); 403 }}); 404 0x2: mftacx_dsp0({{ 405 data = xc->readRegOtherThread( 406 RegId(IntRegClass, INTREG_DSP_ACX0)); 407 }}); 408 0x4: mftlo_dsp1({{ 409 data = xc->readRegOtherThread( 410 RegId(IntRegClass, INTREG_DSP_LO1)); 411 }}); 412 0x5: mfthi_dsp1({{ 413 data = xc->readRegOtherThread( 414 RegId(IntRegClass, INTREG_DSP_HI1)); 415 }}); 416 0x6: mftacx_dsp1({{ 417 data = xc->readRegOtherThread( 418 RegId(IntRegClass, INTREG_DSP_ACX1)); 419 }}); 420 0x8: mftlo_dsp2({{ 421 data = xc->readRegOtherThread( 422 RegId(IntRegClass, INTREG_DSP_LO2)); 423 }}); 424 0x9: mfthi_dsp2({{ 425 data = xc->readRegOtherThread( 426 RegId(IntRegClass, INTREG_DSP_HI2)); 427 }}); 428 0x10: mftacx_dsp2({{ 429 data = xc->readRegOtherThread( 430 RegId(IntRegClass, INTREG_DSP_ACX2)); 431 }}); 432 0x12: mftlo_dsp3({{ 433 data = xc->readRegOtherThread( 434 RegId(IntRegClass, INTREG_DSP_LO3)); 435 }}); 436 0x13: mfthi_dsp3({{ 437 data = xc->readRegOtherThread( 438 RegId(IntRegClass, INTREG_DSP_HI3)); 439 }}); 440 0x14: mftacx_dsp3({{ 441 data = xc->readRegOtherThread( 442 RegId(IntRegClass, INTREG_DSP_ACX3)); 443 }}); 444 0x16: mftdsp({{ 445 data = xc->readRegOtherThread( 446 RegId(IntRegClass, INTREG_DSP_CONTROL)); 447 }}); |
448 default: CP0Unimpl::unknown(); 449 } 450 0x2: decode MT_H { |
451 0x0: mftc1({{ 452 data = xc->readRegOtherThread( 453 RegId(FloatRegClass, RT)); |
454 }}); |
455 0x1: mfthc1({{ 456 data = xc->readRegOtherThread( 457 RegId(FloatRegClass, RT)); |
458 }}); 459 } 460 0x3: cftc1({{ |
461 uint32_t fcsr_val = xc->readRegOtherThread( 462 RegId(FloatRegClass, FLOATREG_FCSR)); |
463 switch (RT) { 464 case 0: |
465 data = xc->readRegOtherThread( 466 RegId(MiscRegClass, FLOATREG_FIR)); |
467 break; 468 case 25: 469 data = (fcsr_val & 0xFE000000 >> 24) | 470 (fcsr_val & 0x00800000 >> 23); 471 break; 472 case 26: 473 data = fcsr_val & 0x0003F07C; 474 break; --- 12 unchanged lines hidden (view full) --- 487 default: CP0Unimpl::unknown(); 488 } 489 } 490 } 491 492 format MT_MTTR { 493 // Decode MIPS MT MTTR instruction into sub-instructions 494 0xC: decode MT_U { |
495 0x0: mttc0({{ xc->setRegOtherThread( 496 RegId(MiscRegClass, (RD << 3 | SEL)), Rt); |
497 }}); 498 0x1: decode SEL { |
499 0x0: mttgpr({{ xc->setRegOtherThread( 500 RegId(IntRegClass, RD), Rt); 501 }}); |
502 0x1: decode RT { |
503 0x0: mttlo_dsp0({{ xc->setRegOtherThread( 504 RegId(IntRegClass, INTREG_DSP_LO0), Rt); 505 }}); 506 0x1: mtthi_dsp0({{ xc->setRegOtherThread( 507 RegId(IntRegClass, INTREG_DSP_HI0), Rt); 508 }}); 509 0x2: mttacx_dsp0({{ xc->setRegOtherThread( 510 RegId(IntRegClass, INTREG_DSP_ACX0), Rt); 511 }}); 512 0x4: mttlo_dsp1({{ xc->setRegOtherThread( 513 RegId(IntRegClass, INTREG_DSP_LO1), Rt); 514 }}); 515 0x5: mtthi_dsp1({{ xc->setRegOtherThread( 516 RegId(IntRegClass, INTREG_DSP_HI1), Rt); 517 }}); 518 0x6: mttacx_dsp1({{ xc->setRegOtherThread( 519 RegId(IntRegClass, INTREG_DSP_ACX1), Rt); 520 }}); 521 0x8: mttlo_dsp2({{ xc->setRegOtherThread( 522 RegId(IntRegClass, INTREG_DSP_LO2), Rt); 523 }}); 524 0x9: mtthi_dsp2({{ xc->setRegOtherThread( 525 RegId(IntRegClass, INTREG_DSP_HI2), Rt); 526 }}); 527 0x10: mttacx_dsp2({{ xc->setRegOtherThread( 528 RegId(IntRegClass, INTREG_DSP_ACX2), Rt); 529 }}); 530 0x12: mttlo_dsp3({{ xc->setRegOtherThread( 531 RegId(IntRegClass, INTREG_DSP_LO3), Rt); 532 }}); 533 0x13: mtthi_dsp3({{ xc->setRegOtherThread( 534 RegId(IntRegClass, INTREG_DSP_HI3), Rt); 535 }}); 536 0x14: mttacx_dsp3({{ xc->setRegOtherThread( 537 RegId(IntRegClass, INTREG_DSP_ACX3), Rt); 538 }}); 539 0x16: mttdsp({{ xc->setRegOtherThread( 540 RegId(IntRegClass, INTREG_DSP_CONTROL), Rt); 541 }}); |
542 default: CP0Unimpl::unknown(); 543 544 } 545 0x2: mttc1({{ |
546 uint64_t data = xc->readRegOtherThread( 547 RegId(FloatRegClass, RD)); |
548 data = insertBits(data, MT_H ? 63 : 31, 549 MT_H ? 32 : 0, Rt); |
550 xc->setRegOtherThread(RegId(FloatRegClass, RD), |
551 data); 552 }}); 553 0x3: cttc1({{ 554 uint32_t data; 555 switch (RD) { 556 case 25: 557 data = (Rt_uw<7:1> << 25) | // move 31-25 558 (FCSR & 0x01000000) | // bit 24 --- 18 unchanged lines hidden (view full) --- 577 data = Rt_uw; 578 break; 579 default: 580 panic("FP Control Value (%d) " 581 "Not Available. Ignoring " 582 "Access to Floating Control " 583 "S""tatus Register", FS); 584 } |
585 xc->setRegOtherThread( 586 RegId(FloatRegClass, FLOATREG_FCSR), data); |
587 }}); 588 default: CP0Unimpl::unknown(); 589 } 590 } 591 } 592 0xB: decode RD { 593 format MT_Control { 594 0x0: decode POS { --- 1976 unchanged lines hidden --- |