3,30c3
< // Copyright (c) 2006 The Regents of The University of Michigan
< // All rights reserved.
< //
< // Redistribution and use in source and binary forms, with or without
< // modification, are permitted provided that the following conditions are
< // met: redistributions of source code must retain the above copyright
< // notice, this list of conditions and the following disclaimer;
< // redistributions in binary form must reproduce the above copyright
< // notice, this list of conditions and the following disclaimer in the
< // documentation and/or other materials provided with the distribution;
< // neither the name of the copyright holders nor the names of its
< // contributors may be used to endorse or promote products derived from
< // this software without specific prior written permission.
< //
< // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
< // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
< // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
< // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
< // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
< // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
< // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
< // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
< // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
< // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
< // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
< //
< // Authors: Korey Sewell
< // Brett Miller
---
> // Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
31a5,38
> // This software is part of the M5 simulator.
>
> // THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
> // DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
> // TO THESE TERMS AND CONDITIONS.
>
> // Permission is granted to use, copy, create derivative works and
> // distribute this software and such derivative works for any purpose,
> // so long as (1) the copyright notice above, this grant of permission,
> // and the disclaimer below appear in all copies and derivative works
> // made, (2) the copyright notice above is augmented as appropriate to
> // reflect the addition of any new copyrightable work in a derivative
> // work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
> // the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
> // advertising or publicity pertaining to the use or distribution of
> // this software without specific, written prior authorization.
>
> // THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
> // DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
> // OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
> // NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
> // IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
> // INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
> // ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
> // THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
> // IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
> // STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
> // POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
>
> //Authors: Korey L. Sewell
> // Brett Miller
> // Jaidev Patwardhan
>
60,61c67,68
< 0x1: WarnUnimpl::ssnop();
< 0x3: WarnUnimpl::ehb();
---
> 0x1: ssnop({{;}});
> 0x3: ehb({{;}});
122,123c129,130
< 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
< default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
---
> 0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards);
> default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn);
135a143,147
> #if FULL_SYSTEM
> 0x4: syscall({{
> fault = new SystemCallFault();
> }});
> #else
137,138c149,150
< IsSerializeAfter, IsNonSpeculative,
< IsSyscall);
---
> IsSerializing, IsNonSpeculative);
> #endif
139a152
> 0x5: break({{fault = new BreakpointFault();}});
142,144d154
< format FailUnimpl {
< 0x5: break();
< }
148c158
< 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
---
> 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess);
150c160
< 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
---
> 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess);
156,157c166,167
< 0x0: mult({{ val = Rs.sd * Rt.sd; }});
< 0x1: multu({{ val = Rs.ud * Rt.ud; }});
---
> 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp);
> 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp);
165c175,176
< }});
---
> }}, IntDivOp);
>
170c181
< }});
---
> }}, IntDivOp);
177c188,207
< 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
---
> 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */
> int64_t Src1 = Rs.sw;
> int64_t Src2 = Rt.sw;
> int64_t temp_result;
> #if FULL_SYSTEM
> if(((Src1 >> 31) & 1) == 1)
> Src1 |= 0x100000000LL;
> #endif
> temp_result = Src1 + Src2;
> #if FULL_SYSTEM
> if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
> #endif
> Rd.sw = temp_result;
> #if FULL_SYSTEM
> } else{
> fault = new ArithmeticFault();
> }
> #endif
>
> }});
179c209,223
< 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
---
> 0x2: sub({{
> /* More complicated since an SUB can cause an arithmetic overflow exception */
> int64_t Src1 = Rs.sw;
> int64_t Src2 = Rt.sw;
> int64_t temp_result = Src1 - Src2;
> #if FULL_SYSTEM
> if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){
> #endif
> Rd.sw = temp_result;
> #if FULL_SYSTEM
> } else{
> fault = new ArithmeticFault();
> }
> #endif
> }});
203c247
< 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
---
> 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }});
221,227c265,271
< format Trap {
< 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
< 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
< 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
< 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
< 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
< 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
---
> format TrapImm {
> 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }});
> 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }});
> 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }});
> 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }});
> 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}});
> 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}});
271c315,333
< 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
---
> 0x0: addi({{
> int64_t Src1 = Rs.sw;
> int64_t Src2 = imm;
> int64_t temp_result;
> #if FULL_SYSTEM
> if(((Src1 >> 31) & 1) == 1)
> Src1 |= 0x100000000LL;
> #endif
> temp_result = Src1 + Src2;
> #if FULL_SYSTEM
> if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
> #endif
> Rt.sw = temp_result;
> #if FULL_SYSTEM
> } else{
> fault = new ArithmeticFault();
> }
> #endif
> }});
297,300c359,366
< format CP0Control {
< 0x0: mfc0({{ Rt = CP0_RD_SEL; }});
< 0x4: mtc0({{ CP0_RD_SEL = Rt; }});
< }
---
> format CP0Control {
> 0x0: mfc0({{ Rt = CP0_RD_SEL;
> /* Hack for PageMask */
> if(RD == 5) // PageMask
> if(Config3_SP == 0 || PageGrain_ESP == 0)
> Rt &= 0xFFFFE7FF;
> }});
> 0x4: mtc0({{ CP0_RD_SEL = Rt;
301a368,376
> if(RD == 11) // Compare{
> if(Cause_TI == 1){
> Cause_TI = 0;
> MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause);
> int Offset = 10; // corresponding to Cause_IP0
> Offset += ((IntCtl_IPTI) - 2);
> replaceBits(cause,Offset,Offset,0);
> xc->setMiscRegNoEffect(MipsISA::Cause,cause);
> }
302a378,384
> }});
> }
> format CP0Unimpl {
> 0x1: dmfc0();
> 0x5: dmtc0();
> default: unknown();
> }
323a406
> default: CP0Unimpl::unknown();
332c415
< }
---
> }
359a443
> default: CP0Unimpl::unknown();
361c445
< }
---
> }
406a491,492
> default: CP0Unimpl::unknown();
>
448a535
> default: CP0Unimpl::unknown();
468a556
> default:CP0Unimpl::unknown();
469a558
> default:CP0Unimpl::unknown();
471c560,561
< }
---
> default:CP0Unimpl::unknown();
> }
482c572
<
---
> default:CP0Unimpl::unknown();
483a574
> default:CP0Unimpl::unknown();
484a576
> default:CP0Unimpl::unknown();
510a603
> default:CP0Unimpl::unknown();
512a606
> default: CP0Unimpl::unknown();
514d607
<
519c612
< Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
---
> Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS);
529c622,623
< xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
---
> xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt);
> // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl);
537d630
<
540c633
< }
---
> }
545a639,643
> DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
> // Ugly hack to get the value of Status_EXL
> if(Status_EXL == 1){
> DPRINTF(MipsPRA,"ERET EXL Hack\n");
> }
548a647
> NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
550c649
< else{
---
> else {
551a651
> NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
553c653
< if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
---
> if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){
554a655
> xc->setShadowSet(SRSCtl_PSS);
557,559c658,659
< // LLFlag = 0;
< // ClearHazards(); ?
< }});
---
> LLFlag = 0;
> }},IsReturn,IsSerializing,IsERET);
562,568c662,676
< //if(Debug_DM == 1){
< //Debug_DM = 1;
< //Debug_IEXI = 0;
< //NPC = DEPC;
< //}
< panic("deret not implemented");
< }});
---
> // if(EJTagImplemented()) {
> if(Debug_DM == 1){
> Debug_DM = 1;
> Debug_IEXI = 0;
> NPC = DEPC;
> }
> else
> {
> // Undefined;
> }
> //} // EJTag Implemented
> //else {
> // Reserved Instruction Exception
> //}
> }},IsReturn,IsSerializing,IsERET);
569a678,693
> format CP0TLB {
> 0x01: tlbr({{
> MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF);
> if(PTEntry == NULL)
> {
> fatal("Invalid PTE Entry received on a TLBR instruction\n");
> }
> /* Setup PageMask */
> PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11
> /* Setup EntryHi */
> EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
> /* Setup Entry Lo0 */
> EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G);
> /* Setup Entry Lo1 */
> EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G);
> }}); // Need to hook up to TLB
571,575c695,706
< format FailUnimpl {
< 0x01: tlbr(); // Need to hook up to TLB
< 0x02: tlbwi(); // Need to hook up to TLB
< 0x06: tlbwr();// Need to hook up to TLB
< 0x08: tlbp();// Need to hook up to TLB
---
> 0x02: tlbwi({{
> //Create PTE
> MipsISA::PTE NewEntry;
> //Write PTE
> NewEntry.Mask = (Addr)(PageMask >> 11);
> NewEntry.VPN = (Addr)(EntryHi >> 11);
> /* PageGrain _ ESP Config3 _ SP */
> if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
> NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
> NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
> }
> NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
577,578c708,743
< 0x20: wait();
< }
---
> NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
> NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
> NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
> NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
> NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
> NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
> NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
> NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
> NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
> /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
> /* Addr Shift Amount for 1KB or larger pages */
> // warn("PTE->Mask: %x\n",pte->Mask);
> if((NewEntry.Mask & 0xFFFF) == 3){
> NewEntry.AddrShiftAmount = 12;
> } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
> NewEntry.AddrShiftAmount = 10;
> } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
> NewEntry.AddrShiftAmount = 14;
> } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
> NewEntry.AddrShiftAmount = 16;
> } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
> NewEntry.AddrShiftAmount = 18;
> } else if((NewEntry.Mask & 0xFF00) == 0x0300){
> NewEntry.AddrShiftAmount = 20;
> } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
> NewEntry.AddrShiftAmount = 22;
> } else if((NewEntry.Mask & 0xF000) == 0x3000){
> NewEntry.AddrShiftAmount = 24;
> } else if((NewEntry.Mask & 0xC000) == 0xC000){
> NewEntry.AddrShiftAmount = 26;
> } else if((NewEntry.Mask & 0x30000) == 0x30000){
> NewEntry.AddrShiftAmount = 28;
> } else {
> fatal("Invalid Mask Pattern Detected!\n");
> }
> NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
579a745,835
> MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
> MiscReg c3=xc->readMiscReg(MipsISA::Config3);
> MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
> int SP=0;
> if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
> SP=1;
> }
> Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP);
> }});
> 0x06: tlbwr({{
> //Create PTE
> MipsISA::PTE NewEntry;
> //Write PTE
> NewEntry.Mask = (Addr)(PageMask >> 11);
> NewEntry.VPN = (Addr)(EntryHi >> 11);
> /* PageGrain _ ESP Config3 _ SP */
> if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
> NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
> NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
> }
> NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
>
> NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
> NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
> NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
> NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
> NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
> NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
> NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
> NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
> NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
> /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
> /* Addr Shift Amount for 1KB or larger pages */
> // warn("PTE->Mask: %x\n",pte->Mask);
> if((NewEntry.Mask & 0xFFFF) == 3){
> NewEntry.AddrShiftAmount = 12;
> } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
> NewEntry.AddrShiftAmount = 10;
> } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
> NewEntry.AddrShiftAmount = 14;
> } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
> NewEntry.AddrShiftAmount = 16;
> } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
> NewEntry.AddrShiftAmount = 18;
> } else if((NewEntry.Mask & 0xFF00) == 0x0300){
> NewEntry.AddrShiftAmount = 20;
> } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
> NewEntry.AddrShiftAmount = 22;
> } else if((NewEntry.Mask & 0xF000) == 0x3000){
> NewEntry.AddrShiftAmount = 24;
> } else if((NewEntry.Mask & 0xC000) == 0xC000){
> NewEntry.AddrShiftAmount = 26;
> } else if((NewEntry.Mask & 0x30000) == 0x30000){
> NewEntry.AddrShiftAmount = 28;
> } else {
> fatal("Invalid Mask Pattern Detected!\n");
> }
> NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
>
> MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
> MiscReg c3=xc->readMiscReg(MipsISA::Config3);
> MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
> int SP=0;
> if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
> SP=1;
> }
> Ptr->insertAt(NewEntry,Random,SP);
> }});
>
> 0x08: tlbp({{
> int TLB_Index;
> Addr VPN;
> if(PageGrain_ESP == 1 && Config3_SP ==1){
> VPN = EntryHi >> 11;
> } else {
> VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits
> }
> TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID);
> if(TLB_Index != -1){ // Check TLB for entry matching EntryHi
> Index=TLB_Index;
> // warn("\ntlbp: Match Found!\n");
> } else {// else, set Index = 1<<31
> Index = (1<<31);
> }
> }});
> }
> format CP0Unimpl {
> 0x20: wait();
> }
> default: CP0Unimpl::unknown();
>
610c866
< panic("FP Control Value (%d) Not Valid");
---
> warn("FP Control Value (%d) Not Valid");
611a868
> // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt);
661,676c918,920
< }
<
< 0x1: decode ND {
< format Branch {
< 0x0: decode TF {
< 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
< }});
< 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
< }});
< }
< 0x1: decode TF {
< 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
< }}, Likely);
< 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
< }}, Likely);
< }
---
> format CP1Unimpl {
> 0x1: dmfc1();
> 0x5: dmtc1();
678c922,948
< }
---
> }
>
> 0x1:
> decode RS_LO {
> 0x0:
> decode ND {
> format Branch {
> 0x0: decode TF {
> 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
> }});
> 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
> }});
> }
> 0x1: decode TF {
> 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
> }}, Likely);
> 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
> }}, Likely);
> }
> }
> }
> format CP1Unimpl {
> 0x1: bc1any2();
> 0x2: bc1any4();
> default: unknown();
> }
> }
737a1008,1010
> format CP1Unimpl {
> default: unknown();
> }
738a1012
> 0x3: CP1Unimpl::unknown();
750a1025,1027
> format CP1Unimpl {
> default: unknown();
> }
751a1029
> 0x5: CP1Unimpl::unknown();
854c1132,1134
< }
---
> format CP1Unimpl {
> default: unknown();
> }
855a1136
> }
861a1143
> default: CP1Unimpl::unknown();
904a1187
> default: CP1Unimpl::unknown();
905a1189,1191
> 0x2: CP1Unimpl::unknown();
> 0x3: CP1Unimpl::unknown();
> 0x7: CP1Unimpl::unknown();
912c1198
< 0x26: FailUnimpl::cvt_ps_w();
---
> 0x26: CP1Unimpl::cvt_ps_w();
913a1200
> default: CP1Unimpl::unknown();
923c1210
< 0x26: FailUnimpl::cvt_ps_l();
---
> 0x26: CP1Unimpl::cvt_ps_l();
924a1212
> default: CP1Unimpl::unknown();
956a1245
> default: CP1Unimpl::unknown();
959c1248
<
---
> 0x1: CP1Unimpl::unknown();
991a1281
> default: CP1Unimpl::unknown();
994c1284
<
---
> 0x3: CP1Unimpl::unknown();
996a1287
> default: CP1Unimpl::unknown();
1015a1307
> default: CP1Unimpl::unknown();
1073a1366
> default: CP1Unimpl::unknown();
1079c1372
< format FailUnimpl {
---
> format CP2Unimpl {
1087a1381
> default: unknown();
1093a1388
> default: unknown();
1098a1394
> default: unknown();
1100,1101c1396,1402
< }
< }
---
> default: unknown();
>
> }
> default: unknown();
>
> }
> default: unknown();
1200c1501
< }});
---
> }}, IntMultOp);
1203,1206c1504,1507
< 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
< 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
< 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
< 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
---
> 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp);
> 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp);
> 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp);
> 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp);
1289c1590
< MODE_L, &dspctl ); }});
---
> MODE_L, &dspctl ); }}, IntMultOp);
1291c1592
< MODE_R, &dspctl ); }});
---
> MODE_R, &dspctl ); }}, IntMultOp);
1338c1639
< MODE_L, &dspctl ); }});
---
> MODE_L, &dspctl ); }}, IntMultOp);
1340c1641
< MODE_R, &dspctl ); }});
---
> MODE_R, &dspctl ); }}, IntMultOp);
1342c1643
< SATURATE, NOROUND, &dspctl ); }});
---
> SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
1344c1645
< SATURATE, ROUND, &dspctl ); }});
---
> SATURATE, ROUND, &dspctl ); }}, IntMultOp);
1562c1863
< NOSATURATE, &dspctl ); }});
---
> NOSATURATE, &dspctl ); }}, IntMultOp);
1564c1865,1866
< SATURATE, &dspctl ); }});
---
> SATURATE, &dspctl ); }}, IntMultOp);
>
1578c1880
< SATURATE, NOROUND, &dspctl ); }});
---
> SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
1580c1882
< SATURATE, ROUND, &dspctl ); }});
---
> SATURATE, ROUND, &dspctl ); }}, IntMultOp);
1606c1908
< SIMD_FMT_PH, SIGNED, MODE_L ); }});
---
> SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
1608c1910
< SIMD_FMT_PH, SIGNED, MODE_L ); }});
---
> SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
1610c1912
< ACDST, SIMD_FMT_PH ); }});
---
> ACDST, SIMD_FMT_PH ); }}, IntMultOp);
1612c1914
< SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
---
> SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
1614c1916
< SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
---
> SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1616c1918
< SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
---
> SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1618c1920
< ACDST, SIMD_FMT_PH, &dspctl ); }});
---
> ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp);
1620c1922
< SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
---
> SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
1626c1928
< SIMD_FMT_PH, SIGNED, MODE_X ); }});
---
> SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
1628c1930
< SIMD_FMT_PH, SIGNED, MODE_X ); }});
---
> SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
1630c1932
< SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
---
> SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
1632c1934
< SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
---
> SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1634c1936
< SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
---
> SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1636c1938
< SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
---
> SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
1642c1944
< MODE_L, SATURATE, &dspctl ); }});
---
> MODE_L, SATURATE, &dspctl ); }}, IntMultOp);
1644c1946
< MODE_R, SATURATE, &dspctl ); }});
---
> MODE_R, SATURATE, &dspctl ); }}, IntMultOp);
1646c1948
< MODE_L, NOSATURATE, &dspctl ); }});
---
> MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp);
1648c1950
< MODE_R, NOSATURATE, &dspctl ); }});
---
> MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp);
1654c1956
< SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
---
> SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1656c1958
< SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
---
> SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1658c1960
< SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
---
> SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1660c1962
< SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
---
> SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1680d1981
< 0x7: FailUnimpl::rdhwr();
1682d1982
<
1737a2038,2042
> 0x3: decode OP_HI {
> 0x2: decode OP_LO {
> 0x3: FailUnimpl::rdhwr();
> }
> }
1744,1745c2049,2050
< 0x0: lb({{ Rt.sw = Mem.sb; }});
< 0x1: lh({{ Rt.sw = Mem.sh; }});
---
> 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);
> 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
1747,1748c2052,2053
< 0x4: lbu({{ Rt.uw = Mem.ub; }});
< 0x5: lhu({{ Rt.uw = Mem.uh; }});
---
> 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT);
> 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
1754c2059
< Rt.uw & mask(mem_shift);
---
> Rt.uw & mask(mem_shift);
1758c2063
< mem_word >> mem_shift;
---
> mem_word >> mem_shift;
1765,1766c2070,2071
< 0x0: sb({{ Mem.ub = Rt<7:0>; }});
< 0x1: sh({{ Mem.uh = Rt<15:0>; }});
---
> 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT);
> 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
1781,1782c2086,2091
<
< 0x7: FailUnimpl::cache();
---
> format CP0Control {
> 0x7: cache({{
> Addr CacheEA = Rs.uw + OFFSET;
> fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
> }});
> }
1791c2100,2101
<
---
> 0x2: CP2Unimpl::lwc2();
> 0x6: CP2Unimpl::ldc2();
1803,1804c2113,2114
< 0x1: swc1({{ Mem.uw = Ft.uw; }});
< 0x5: sdc1({{ Mem.ud = Ft.ud; }});
---
> 0x1: swc1({{ Mem.uw = Ft.uw;}});
> 0x5: sdc1({{ Mem.ud = Ft.ud;}});
1805a2116,2119
>
> 0x2: CP2Unimpl::swc2();
> 0x6: CP2Unimpl::sdc2();
>
< // Copyright (c) 2006 The Regents of The University of Michigan
< // All rights reserved.
< //
< // Redistribution and use in source and binary forms, with or without
< // modification, are permitted provided that the following conditions are
< // met: redistributions of source code must retain the above copyright
< // notice, this list of conditions and the following disclaimer;
< // redistributions in binary form must reproduce the above copyright
< // notice, this list of conditions and the following disclaimer in the
< // documentation and/or other materials provided with the distribution;
< // neither the name of the copyright holders nor the names of its
< // contributors may be used to endorse or promote products derived from
< // this software without specific prior written permission.
< //
< // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
< // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
< // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
< // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
< // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
< // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
< // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
< // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
< // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
< // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
< // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
< //
< // Authors: Korey Sewell
< // Brett Miller
---
> // Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
31a5,38
> // This software is part of the M5 simulator.
>
> // THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
> // DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
> // TO THESE TERMS AND CONDITIONS.
>
> // Permission is granted to use, copy, create derivative works and
> // distribute this software and such derivative works for any purpose,
> // so long as (1) the copyright notice above, this grant of permission,
> // and the disclaimer below appear in all copies and derivative works
> // made, (2) the copyright notice above is augmented as appropriate to
> // reflect the addition of any new copyrightable work in a derivative
> // work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
> // the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
> // advertising or publicity pertaining to the use or distribution of
> // this software without specific, written prior authorization.
>
> // THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
> // DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
> // OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
> // NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
> // IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
> // INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
> // ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
> // THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
> // IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
> // STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
> // POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
>
> //Authors: Korey L. Sewell
> // Brett Miller
> // Jaidev Patwardhan
>
60,61c67,68
< 0x1: WarnUnimpl::ssnop();
< 0x3: WarnUnimpl::ehb();
---
> 0x1: ssnop({{;}});
> 0x3: ehb({{;}});
122,123c129,130
< 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
< default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
---
> 0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards);
> default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn);
135a143,147
> #if FULL_SYSTEM
> 0x4: syscall({{
> fault = new SystemCallFault();
> }});
> #else
137,138c149,150
< IsSerializeAfter, IsNonSpeculative,
< IsSyscall);
---
> IsSerializing, IsNonSpeculative);
> #endif
139a152
> 0x5: break({{fault = new BreakpointFault();}});
142,144d154
< format FailUnimpl {
< 0x5: break();
< }
148c158
< 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
---
> 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess);
150c160
< 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
---
> 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess);
156,157c166,167
< 0x0: mult({{ val = Rs.sd * Rt.sd; }});
< 0x1: multu({{ val = Rs.ud * Rt.ud; }});
---
> 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp);
> 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp);
165c175,176
< }});
---
> }}, IntDivOp);
>
170c181
< }});
---
> }}, IntDivOp);
177c188,207
< 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
---
> 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */
> int64_t Src1 = Rs.sw;
> int64_t Src2 = Rt.sw;
> int64_t temp_result;
> #if FULL_SYSTEM
> if(((Src1 >> 31) & 1) == 1)
> Src1 |= 0x100000000LL;
> #endif
> temp_result = Src1 + Src2;
> #if FULL_SYSTEM
> if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
> #endif
> Rd.sw = temp_result;
> #if FULL_SYSTEM
> } else{
> fault = new ArithmeticFault();
> }
> #endif
>
> }});
179c209,223
< 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
---
> 0x2: sub({{
> /* More complicated since an SUB can cause an arithmetic overflow exception */
> int64_t Src1 = Rs.sw;
> int64_t Src2 = Rt.sw;
> int64_t temp_result = Src1 - Src2;
> #if FULL_SYSTEM
> if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){
> #endif
> Rd.sw = temp_result;
> #if FULL_SYSTEM
> } else{
> fault = new ArithmeticFault();
> }
> #endif
> }});
203c247
< 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
---
> 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }});
221,227c265,271
< format Trap {
< 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
< 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
< 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
< 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
< 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
< 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
---
> format TrapImm {
> 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }});
> 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }});
> 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }});
> 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }});
> 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}});
> 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}});
271c315,333
< 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
---
> 0x0: addi({{
> int64_t Src1 = Rs.sw;
> int64_t Src2 = imm;
> int64_t temp_result;
> #if FULL_SYSTEM
> if(((Src1 >> 31) & 1) == 1)
> Src1 |= 0x100000000LL;
> #endif
> temp_result = Src1 + Src2;
> #if FULL_SYSTEM
> if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
> #endif
> Rt.sw = temp_result;
> #if FULL_SYSTEM
> } else{
> fault = new ArithmeticFault();
> }
> #endif
> }});
297,300c359,366
< format CP0Control {
< 0x0: mfc0({{ Rt = CP0_RD_SEL; }});
< 0x4: mtc0({{ CP0_RD_SEL = Rt; }});
< }
---
> format CP0Control {
> 0x0: mfc0({{ Rt = CP0_RD_SEL;
> /* Hack for PageMask */
> if(RD == 5) // PageMask
> if(Config3_SP == 0 || PageGrain_ESP == 0)
> Rt &= 0xFFFFE7FF;
> }});
> 0x4: mtc0({{ CP0_RD_SEL = Rt;
301a368,376
> if(RD == 11) // Compare{
> if(Cause_TI == 1){
> Cause_TI = 0;
> MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause);
> int Offset = 10; // corresponding to Cause_IP0
> Offset += ((IntCtl_IPTI) - 2);
> replaceBits(cause,Offset,Offset,0);
> xc->setMiscRegNoEffect(MipsISA::Cause,cause);
> }
302a378,384
> }});
> }
> format CP0Unimpl {
> 0x1: dmfc0();
> 0x5: dmtc0();
> default: unknown();
> }
323a406
> default: CP0Unimpl::unknown();
332c415
< }
---
> }
359a443
> default: CP0Unimpl::unknown();
361c445
< }
---
> }
406a491,492
> default: CP0Unimpl::unknown();
>
448a535
> default: CP0Unimpl::unknown();
468a556
> default:CP0Unimpl::unknown();
469a558
> default:CP0Unimpl::unknown();
471c560,561
< }
---
> default:CP0Unimpl::unknown();
> }
482c572
<
---
> default:CP0Unimpl::unknown();
483a574
> default:CP0Unimpl::unknown();
484a576
> default:CP0Unimpl::unknown();
510a603
> default:CP0Unimpl::unknown();
512a606
> default: CP0Unimpl::unknown();
514d607
<
519c612
< Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
---
> Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS);
529c622,623
< xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
---
> xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt);
> // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl);
537d630
<
540c633
< }
---
> }
545a639,643
> DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
> // Ugly hack to get the value of Status_EXL
> if(Status_EXL == 1){
> DPRINTF(MipsPRA,"ERET EXL Hack\n");
> }
548a647
> NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
550c649
< else{
---
> else {
551a651
> NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
553c653
< if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
---
> if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){
554a655
> xc->setShadowSet(SRSCtl_PSS);
557,559c658,659
< // LLFlag = 0;
< // ClearHazards(); ?
< }});
---
> LLFlag = 0;
> }},IsReturn,IsSerializing,IsERET);
562,568c662,676
< //if(Debug_DM == 1){
< //Debug_DM = 1;
< //Debug_IEXI = 0;
< //NPC = DEPC;
< //}
< panic("deret not implemented");
< }});
---
> // if(EJTagImplemented()) {
> if(Debug_DM == 1){
> Debug_DM = 1;
> Debug_IEXI = 0;
> NPC = DEPC;
> }
> else
> {
> // Undefined;
> }
> //} // EJTag Implemented
> //else {
> // Reserved Instruction Exception
> //}
> }},IsReturn,IsSerializing,IsERET);
569a678,693
> format CP0TLB {
> 0x01: tlbr({{
> MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF);
> if(PTEntry == NULL)
> {
> fatal("Invalid PTE Entry received on a TLBR instruction\n");
> }
> /* Setup PageMask */
> PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11
> /* Setup EntryHi */
> EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
> /* Setup Entry Lo0 */
> EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G);
> /* Setup Entry Lo1 */
> EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G);
> }}); // Need to hook up to TLB
571,575c695,706
< format FailUnimpl {
< 0x01: tlbr(); // Need to hook up to TLB
< 0x02: tlbwi(); // Need to hook up to TLB
< 0x06: tlbwr();// Need to hook up to TLB
< 0x08: tlbp();// Need to hook up to TLB
---
> 0x02: tlbwi({{
> //Create PTE
> MipsISA::PTE NewEntry;
> //Write PTE
> NewEntry.Mask = (Addr)(PageMask >> 11);
> NewEntry.VPN = (Addr)(EntryHi >> 11);
> /* PageGrain _ ESP Config3 _ SP */
> if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
> NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
> NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
> }
> NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
577,578c708,743
< 0x20: wait();
< }
---
> NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
> NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
> NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
> NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
> NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
> NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
> NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
> NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
> NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
> /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
> /* Addr Shift Amount for 1KB or larger pages */
> // warn("PTE->Mask: %x\n",pte->Mask);
> if((NewEntry.Mask & 0xFFFF) == 3){
> NewEntry.AddrShiftAmount = 12;
> } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
> NewEntry.AddrShiftAmount = 10;
> } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
> NewEntry.AddrShiftAmount = 14;
> } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
> NewEntry.AddrShiftAmount = 16;
> } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
> NewEntry.AddrShiftAmount = 18;
> } else if((NewEntry.Mask & 0xFF00) == 0x0300){
> NewEntry.AddrShiftAmount = 20;
> } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
> NewEntry.AddrShiftAmount = 22;
> } else if((NewEntry.Mask & 0xF000) == 0x3000){
> NewEntry.AddrShiftAmount = 24;
> } else if((NewEntry.Mask & 0xC000) == 0xC000){
> NewEntry.AddrShiftAmount = 26;
> } else if((NewEntry.Mask & 0x30000) == 0x30000){
> NewEntry.AddrShiftAmount = 28;
> } else {
> fatal("Invalid Mask Pattern Detected!\n");
> }
> NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
579a745,835
> MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
> MiscReg c3=xc->readMiscReg(MipsISA::Config3);
> MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
> int SP=0;
> if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
> SP=1;
> }
> Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP);
> }});
> 0x06: tlbwr({{
> //Create PTE
> MipsISA::PTE NewEntry;
> //Write PTE
> NewEntry.Mask = (Addr)(PageMask >> 11);
> NewEntry.VPN = (Addr)(EntryHi >> 11);
> /* PageGrain _ ESP Config3 _ SP */
> if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
> NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
> NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
> }
> NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
>
> NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
> NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
> NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
> NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
> NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
> NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
> NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
> NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
> NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
> /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
> /* Addr Shift Amount for 1KB or larger pages */
> // warn("PTE->Mask: %x\n",pte->Mask);
> if((NewEntry.Mask & 0xFFFF) == 3){
> NewEntry.AddrShiftAmount = 12;
> } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
> NewEntry.AddrShiftAmount = 10;
> } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
> NewEntry.AddrShiftAmount = 14;
> } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
> NewEntry.AddrShiftAmount = 16;
> } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
> NewEntry.AddrShiftAmount = 18;
> } else if((NewEntry.Mask & 0xFF00) == 0x0300){
> NewEntry.AddrShiftAmount = 20;
> } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
> NewEntry.AddrShiftAmount = 22;
> } else if((NewEntry.Mask & 0xF000) == 0x3000){
> NewEntry.AddrShiftAmount = 24;
> } else if((NewEntry.Mask & 0xC000) == 0xC000){
> NewEntry.AddrShiftAmount = 26;
> } else if((NewEntry.Mask & 0x30000) == 0x30000){
> NewEntry.AddrShiftAmount = 28;
> } else {
> fatal("Invalid Mask Pattern Detected!\n");
> }
> NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
>
> MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
> MiscReg c3=xc->readMiscReg(MipsISA::Config3);
> MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
> int SP=0;
> if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
> SP=1;
> }
> Ptr->insertAt(NewEntry,Random,SP);
> }});
>
> 0x08: tlbp({{
> int TLB_Index;
> Addr VPN;
> if(PageGrain_ESP == 1 && Config3_SP ==1){
> VPN = EntryHi >> 11;
> } else {
> VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits
> }
> TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID);
> if(TLB_Index != -1){ // Check TLB for entry matching EntryHi
> Index=TLB_Index;
> // warn("\ntlbp: Match Found!\n");
> } else {// else, set Index = 1<<31
> Index = (1<<31);
> }
> }});
> }
> format CP0Unimpl {
> 0x20: wait();
> }
> default: CP0Unimpl::unknown();
>
610c866
< panic("FP Control Value (%d) Not Valid");
---
> warn("FP Control Value (%d) Not Valid");
611a868
> // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt);
661,676c918,920
< }
<
< 0x1: decode ND {
< format Branch {
< 0x0: decode TF {
< 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
< }});
< 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
< }});
< }
< 0x1: decode TF {
< 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
< }}, Likely);
< 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
< }}, Likely);
< }
---
> format CP1Unimpl {
> 0x1: dmfc1();
> 0x5: dmtc1();
678c922,948
< }
---
> }
>
> 0x1:
> decode RS_LO {
> 0x0:
> decode ND {
> format Branch {
> 0x0: decode TF {
> 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
> }});
> 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
> }});
> }
> 0x1: decode TF {
> 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
> }}, Likely);
> 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
> }}, Likely);
> }
> }
> }
> format CP1Unimpl {
> 0x1: bc1any2();
> 0x2: bc1any4();
> default: unknown();
> }
> }
737a1008,1010
> format CP1Unimpl {
> default: unknown();
> }
738a1012
> 0x3: CP1Unimpl::unknown();
750a1025,1027
> format CP1Unimpl {
> default: unknown();
> }
751a1029
> 0x5: CP1Unimpl::unknown();
854c1132,1134
< }
---
> format CP1Unimpl {
> default: unknown();
> }
855a1136
> }
861a1143
> default: CP1Unimpl::unknown();
904a1187
> default: CP1Unimpl::unknown();
905a1189,1191
> 0x2: CP1Unimpl::unknown();
> 0x3: CP1Unimpl::unknown();
> 0x7: CP1Unimpl::unknown();
912c1198
< 0x26: FailUnimpl::cvt_ps_w();
---
> 0x26: CP1Unimpl::cvt_ps_w();
913a1200
> default: CP1Unimpl::unknown();
923c1210
< 0x26: FailUnimpl::cvt_ps_l();
---
> 0x26: CP1Unimpl::cvt_ps_l();
924a1212
> default: CP1Unimpl::unknown();
956a1245
> default: CP1Unimpl::unknown();
959c1248
<
---
> 0x1: CP1Unimpl::unknown();
991a1281
> default: CP1Unimpl::unknown();
994c1284
<
---
> 0x3: CP1Unimpl::unknown();
996a1287
> default: CP1Unimpl::unknown();
1015a1307
> default: CP1Unimpl::unknown();
1073a1366
> default: CP1Unimpl::unknown();
1079c1372
< format FailUnimpl {
---
> format CP2Unimpl {
1087a1381
> default: unknown();
1093a1388
> default: unknown();
1098a1394
> default: unknown();
1100,1101c1396,1402
< }
< }
---
> default: unknown();
>
> }
> default: unknown();
>
> }
> default: unknown();
1200c1501
< }});
---
> }}, IntMultOp);
1203,1206c1504,1507
< 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
< 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
< 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
< 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
---
> 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp);
> 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp);
> 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp);
> 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp);
1289c1590
< MODE_L, &dspctl ); }});
---
> MODE_L, &dspctl ); }}, IntMultOp);
1291c1592
< MODE_R, &dspctl ); }});
---
> MODE_R, &dspctl ); }}, IntMultOp);
1338c1639
< MODE_L, &dspctl ); }});
---
> MODE_L, &dspctl ); }}, IntMultOp);
1340c1641
< MODE_R, &dspctl ); }});
---
> MODE_R, &dspctl ); }}, IntMultOp);
1342c1643
< SATURATE, NOROUND, &dspctl ); }});
---
> SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
1344c1645
< SATURATE, ROUND, &dspctl ); }});
---
> SATURATE, ROUND, &dspctl ); }}, IntMultOp);
1562c1863
< NOSATURATE, &dspctl ); }});
---
> NOSATURATE, &dspctl ); }}, IntMultOp);
1564c1865,1866
< SATURATE, &dspctl ); }});
---
> SATURATE, &dspctl ); }}, IntMultOp);
>
1578c1880
< SATURATE, NOROUND, &dspctl ); }});
---
> SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
1580c1882
< SATURATE, ROUND, &dspctl ); }});
---
> SATURATE, ROUND, &dspctl ); }}, IntMultOp);
1606c1908
< SIMD_FMT_PH, SIGNED, MODE_L ); }});
---
> SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
1608c1910
< SIMD_FMT_PH, SIGNED, MODE_L ); }});
---
> SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
1610c1912
< ACDST, SIMD_FMT_PH ); }});
---
> ACDST, SIMD_FMT_PH ); }}, IntMultOp);
1612c1914
< SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
---
> SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
1614c1916
< SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
---
> SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1616c1918
< SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
---
> SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1618c1920
< ACDST, SIMD_FMT_PH, &dspctl ); }});
---
> ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp);
1620c1922
< SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
---
> SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
1626c1928
< SIMD_FMT_PH, SIGNED, MODE_X ); }});
---
> SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
1628c1930
< SIMD_FMT_PH, SIGNED, MODE_X ); }});
---
> SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
1630c1932
< SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
---
> SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
1632c1934
< SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
---
> SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1634c1936
< SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
---
> SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
1636c1938
< SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
---
> SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
1642c1944
< MODE_L, SATURATE, &dspctl ); }});
---
> MODE_L, SATURATE, &dspctl ); }}, IntMultOp);
1644c1946
< MODE_R, SATURATE, &dspctl ); }});
---
> MODE_R, SATURATE, &dspctl ); }}, IntMultOp);
1646c1948
< MODE_L, NOSATURATE, &dspctl ); }});
---
> MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp);
1648c1950
< MODE_R, NOSATURATE, &dspctl ); }});
---
> MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp);
1654c1956
< SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
---
> SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1656c1958
< SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
---
> SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1658c1960
< SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
---
> SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1660c1962
< SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
---
> SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
1680d1981
< 0x7: FailUnimpl::rdhwr();
1682d1982
<
1737a2038,2042
> 0x3: decode OP_HI {
> 0x2: decode OP_LO {
> 0x3: FailUnimpl::rdhwr();
> }
> }
1744,1745c2049,2050
< 0x0: lb({{ Rt.sw = Mem.sb; }});
< 0x1: lh({{ Rt.sw = Mem.sh; }});
---
> 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);
> 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
1747,1748c2052,2053
< 0x4: lbu({{ Rt.uw = Mem.ub; }});
< 0x5: lhu({{ Rt.uw = Mem.uh; }});
---
> 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT);
> 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
1754c2059
< Rt.uw & mask(mem_shift);
---
> Rt.uw & mask(mem_shift);
1758c2063
< mem_word >> mem_shift;
---
> mem_word >> mem_shift;
1765,1766c2070,2071
< 0x0: sb({{ Mem.ub = Rt<7:0>; }});
< 0x1: sh({{ Mem.uh = Rt<15:0>; }});
---
> 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT);
> 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
1781,1782c2086,2091
<
< 0x7: FailUnimpl::cache();
---
> format CP0Control {
> 0x7: cache({{
> Addr CacheEA = Rs.uw + OFFSET;
> fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
> }});
> }
1791c2100,2101
<
---
> 0x2: CP2Unimpl::lwc2();
> 0x6: CP2Unimpl::ldc2();
1803,1804c2113,2114
< 0x1: swc1({{ Mem.uw = Ft.uw; }});
< 0x5: sdc1({{ Mem.ud = Ft.ud; }});
---
> 0x1: swc1({{ Mem.uw = Ft.uw;}});
> 0x5: sdc1({{ Mem.ud = Ft.ud;}});
1805a2116,2119
>
> 0x2: CP2Unimpl::swc2();
> 0x6: CP2Unimpl::sdc2();
>