846 Ptr->insertAt(newEntry, Random, SP); 847 }}); 848 849 0x08: tlbp({{ 850 Config3Reg config3 = Config3; 851 PageGrainReg pageGrain = PageGrain; 852 EntryHiReg entryHi = EntryHi; 853 int tlbIndex; 854 Addr vpn; 855 if (pageGrain.esp == 1 && config3.sp ==1) { 856 vpn = EntryHi >> 11; 857 } else { 858 // Mask off lower 2 bits 859 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 860 } 861 tlbIndex = xc->tcBase()->getITBPtr()-> 862 probeEntry(vpn, entryHi.asid); 863 // Check TLB for entry matching EntryHi 864 if (tlbIndex != -1) { 865 Index = tlbIndex; 866 } else { 867 // else, set Index = 1 << 31 868 Index = (1 << 31); 869 } 870 }}); 871 } 872 format CP0Unimpl { 873 0x20: wait(); 874 } 875 default: CP0Unimpl::unknown(); 876 } 877 } 878 879 //Table A-13 MIPS32 COP1 Encoding of rs Field 880 0x1: decode RS_MSB { 881 0x0: decode RS_HI { 882 0x0: decode RS_LO { 883 format CP1Control { 884 0x0: mfc1 ({{ Rt_uw = Fs_uw; }}); 885 886 0x2: cfc1({{ 887 switch (FS) { 888 case 0: 889 Rt = FIR; 890 break; 891 case 25: 892 Rt = (FCSR & 0xFE000000) >> 24 | 893 (FCSR & 0x00800000) >> 23; 894 break; 895 case 26: 896 Rt = (FCSR & 0x0003F07C); 897 break; 898 case 28: 899 Rt = (FCSR & 0x00000F80) | 900 (FCSR & 0x01000000) >> 21 | 901 (FCSR & 0x00000003); 902 break; 903 case 31: 904 Rt = FCSR; 905 break; 906 default: 907 warn("FP Control Value (%d) Not Valid"); 908 } 909 }}); 910 911 0x3: mfhc1({{ Rt_uw = Fs_ud<63:32>; }}); 912 913 0x4: mtc1({{ Fs_uw = Rt_uw; }}); 914 915 0x6: ctc1({{ 916 switch (FS) { 917 case 25: 918 FCSR = (Rt_uw<7:1> << 25) | // move 31-25 919 (FCSR & 0x01000000) | // bit 24 920 (FCSR & 0x004FFFFF); // bit 22-0 921 break; 922 case 26: 923 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 924 Rt_uw<17:12> << 12 | // bit 17-12 925 (FCSR & 0x00000F80) << 7 | // bit 11-7 926 Rt_uw<6:2> << 2 | // bit 6-2 927 (FCSR & 0x00000002); // bit 1-0 928 break; 929 case 28: 930 FCSR = (FCSR & 0xFE000000) | // move 31-25 931 Rt_uw<2:2> << 24 | // bit 24 932 (FCSR & 0x00FFF000) << 23 | // bit 23-12 933 Rt_uw<11:7> << 7 | // bit 24 934 (FCSR & 0x000007E) | 935 Rt_uw<1:0>; // bit 22-0 936 break; 937 case 31: 938 FCSR = Rt_uw; 939 break; 940 941 default: 942 panic("FP Control Value (%d) " 943 "Not Available. Ignoring Access " 944 "to Floating Control Status " 945 "Register", FS); 946 } 947 }}); 948 949 0x7: mthc1({{ 950 uint64_t fs_hi = Rt_uw; 951 uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF; 952 Fs_ud = (fs_hi << 32) | fs_lo; 953 }}); 954 955 } 956 format CP1Unimpl { 957 0x1: dmfc1(); 958 0x5: dmtc1(); 959 } 960 } 961 962 0x1: decode RS_LO { 963 0x0: decode ND { 964 format Branch { 965 0x0: decode TF { 966 0x0: bc1f({{ 967 cond = getCondCode(FCSR, BRANCH_CC) == 0; 968 }}); 969 0x1: bc1t({{ 970 cond = getCondCode(FCSR, BRANCH_CC) == 1; 971 }}); 972 } 973 0x1: decode TF { 974 0x0: bc1fl({{ 975 cond = getCondCode(FCSR, BRANCH_CC) == 0; 976 }}, Likely); 977 0x1: bc1tl({{ 978 cond = getCondCode(FCSR, BRANCH_CC) == 1; 979 }}, Likely); 980 } 981 } 982 } 983 format CP1Unimpl { 984 0x1: bc1any2(); 985 0x2: bc1any4(); 986 default: unknown(); 987 } 988 } 989 } 990 991 0x1: decode RS_HI { 992 0x2: decode RS_LO { 993 //Table A-14 MIPS32 COP1 Encoding of Function Field When 994 //rs=S (( single-precision floating point)) 995 0x0: decode FUNCTION_HI { 996 0x0: decode FUNCTION_LO { 997 format FloatOp { 998 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }}); 999 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }}); 1000 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }}); 1001 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }}); 1002 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }}); 1003 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }}); 1004 0x7: neg_s({{ Fd_sf = -Fs_sf; }}); 1005 } 1006 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }}); 1007 } 1008 0x1: decode FUNCTION_LO { 1009 format FloatConvertOp { 1010 0x0: round_l_s({{ val = Fs_sf; }}, 1011 ToLong, Round); 1012 0x1: trunc_l_s({{ val = Fs_sf; }}, 1013 ToLong, Trunc); 1014 0x2: ceil_l_s({{ val = Fs_sf;}}, 1015 ToLong, Ceil); 1016 0x3: floor_l_s({{ val = Fs_sf; }}, 1017 ToLong, Floor); 1018 0x4: round_w_s({{ val = Fs_sf; }}, 1019 ToWord, Round); 1020 0x5: trunc_w_s({{ val = Fs_sf; }}, 1021 ToWord, Trunc); 1022 0x6: ceil_w_s({{ val = Fs_sf; }}, 1023 ToWord, Ceil); 1024 0x7: floor_w_s({{ val = Fs_sf; }}, 1025 ToWord, Floor); 1026 } 1027 } 1028 1029 0x2: decode FUNCTION_LO { 1030 0x1: decode MOVCF { 1031 format BasicOp { 1032 0x0: movf_s({{ 1033 Fd = (getCondCode(FCSR,CC) == 0) ? 1034 Fs : Fd; 1035 }}); 1036 0x1: movt_s({{ 1037 Fd = (getCondCode(FCSR,CC) == 1) ? 1038 Fs : Fd; 1039 }}); 1040 } 1041 } 1042 1043 format BasicOp { 1044 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1045 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1046 } 1047 1048 format FloatOp { 1049 0x5: recip_s({{ Fd = 1 / Fs; }}); 1050 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 1051 } 1052 format CP1Unimpl { 1053 default: unknown(); 1054 } 1055 } 1056 0x3: CP1Unimpl::unknown(); 1057 1058 0x4: decode FUNCTION_LO { 1059 format FloatConvertOp { 1060 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble); 1061 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord); 1062 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong); 1063 } 1064 1065 0x6: FloatOp::cvt_ps_s({{ 1066 Fd_ud = (uint64_t) Fs_uw << 32 | 1067 (uint64_t) Ft_uw; 1068 }}); 1069 format CP1Unimpl { 1070 default: unknown(); 1071 } 1072 } 1073 0x5: CP1Unimpl::unknown(); 1074 1075 0x6: decode FUNCTION_LO { 1076 format FloatCompareOp { 1077 0x0: c_f_s({{ cond = 0; }}, 1078 SinglePrecision, UnorderedFalse); 1079 0x1: c_un_s({{ cond = 0; }}, 1080 SinglePrecision, UnorderedTrue); 1081 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }}, 1082 UnorderedFalse); 1083 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }}, 1084 UnorderedTrue); 1085 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }}, 1086 UnorderedFalse); 1087 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }}, 1088 UnorderedTrue); 1089 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }}, 1090 UnorderedFalse); 1091 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }}, 1092 UnorderedTrue); 1093 } 1094 } 1095 1096 0x7: decode FUNCTION_LO { 1097 format FloatCompareOp { 1098 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1099 UnorderedFalse, QnanException); 1100 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1101 UnorderedTrue, QnanException); 1102 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }}, 1103 UnorderedFalse, QnanException); 1104 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }}, 1105 UnorderedTrue, QnanException); 1106 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }}, 1107 UnorderedFalse, QnanException); 1108 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }}, 1109 UnorderedTrue, QnanException); 1110 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }}, 1111 UnorderedFalse, QnanException); 1112 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }}, 1113 UnorderedTrue, QnanException); 1114 } 1115 } 1116 } 1117 1118 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1119 //rs=D 1120 0x1: decode FUNCTION_HI { 1121 0x0: decode FUNCTION_LO { 1122 format FloatOp { 1123 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }}); 1124 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }}); 1125 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }}); 1126 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }}); 1127 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }}); 1128 0x5: abs_d({{ Fd_df = fabs(Fs_df); }}); 1129 0x7: neg_d({{ Fd_df = -1 * Fs_df; }}); 1130 } 1131 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }}); 1132 } 1133 1134 0x1: decode FUNCTION_LO { 1135 format FloatConvertOp { 1136 0x0: round_l_d({{ val = Fs_df; }}, 1137 ToLong, Round); 1138 0x1: trunc_l_d({{ val = Fs_df; }}, 1139 ToLong, Trunc); 1140 0x2: ceil_l_d({{ val = Fs_df; }}, 1141 ToLong, Ceil); 1142 0x3: floor_l_d({{ val = Fs_df; }}, 1143 ToLong, Floor); 1144 0x4: round_w_d({{ val = Fs_df; }}, 1145 ToWord, Round); 1146 0x5: trunc_w_d({{ val = Fs_df; }}, 1147 ToWord, Trunc); 1148 0x6: ceil_w_d({{ val = Fs_df; }}, 1149 ToWord, Ceil); 1150 0x7: floor_w_d({{ val = Fs_df; }}, 1151 ToWord, Floor); 1152 } 1153 } 1154 1155 0x2: decode FUNCTION_LO { 1156 0x1: decode MOVCF { 1157 format BasicOp { 1158 0x0: movf_d({{ 1159 Fd_df = (getCondCode(FCSR,CC) == 0) ? 1160 Fs_df : Fd_df; 1161 }}); 1162 0x1: movt_d({{ 1163 Fd_df = (getCondCode(FCSR,CC) == 1) ? 1164 Fs_df : Fd_df; 1165 }}); 1166 } 1167 } 1168 1169 format BasicOp { 1170 0x2: movz_d({{ 1171 Fd_df = (Rt == 0) ? Fs_df : Fd_df; 1172 }}); 1173 0x3: movn_d({{ 1174 Fd_df = (Rt != 0) ? Fs_df : Fd_df; 1175 }}); 1176 } 1177 1178 format FloatOp { 1179 0x5: recip_d({{ Fd_df = 1 / Fs_df; }}); 1180 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }}); 1181 } 1182 format CP1Unimpl { 1183 default: unknown(); 1184 } 1185 1186 } 1187 0x4: decode FUNCTION_LO { 1188 format FloatConvertOp { 1189 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle); 1190 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord); 1191 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong); 1192 } 1193 default: CP1Unimpl::unknown(); 1194 } 1195 1196 0x6: decode FUNCTION_LO { 1197 format FloatCompareOp { 1198 0x0: c_f_d({{ cond = 0; }}, 1199 DoublePrecision, UnorderedFalse); 1200 0x1: c_un_d({{ cond = 0; }}, 1201 DoublePrecision, UnorderedTrue); 1202 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }}, 1203 UnorderedFalse); 1204 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }}, 1205 UnorderedTrue); 1206 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }}, 1207 UnorderedFalse); 1208 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }}, 1209 UnorderedTrue); 1210 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }}, 1211 UnorderedFalse); 1212 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }}, 1213 UnorderedTrue); 1214 } 1215 } 1216 1217 0x7: decode FUNCTION_LO { 1218 format FloatCompareOp { 1219 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1220 UnorderedFalse, QnanException); 1221 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1222 UnorderedTrue, QnanException); 1223 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }}, 1224 UnorderedFalse, QnanException); 1225 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }}, 1226 UnorderedTrue, QnanException); 1227 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }}, 1228 UnorderedFalse, QnanException); 1229 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }}, 1230 UnorderedTrue, QnanException); 1231 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }}, 1232 UnorderedFalse, QnanException); 1233 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }}, 1234 UnorderedTrue, QnanException); 1235 } 1236 } 1237 default: CP1Unimpl::unknown(); 1238 } 1239 0x2: CP1Unimpl::unknown(); 1240 0x3: CP1Unimpl::unknown(); 1241 0x7: CP1Unimpl::unknown(); 1242 1243 //Table A-16 MIPS32 COP1 Encoding of Function 1244 //Field When rs=W 1245 0x4: decode FUNCTION { 1246 format FloatConvertOp { 1247 0x20: cvt_s_w({{ val = Fs_uw; }}, ToSingle); 1248 0x21: cvt_d_w({{ val = Fs_uw; }}, ToDouble); 1249 0x26: CP1Unimpl::cvt_ps_w(); 1250 } 1251 default: CP1Unimpl::unknown(); 1252 } 1253 1254 //Table A-16 MIPS32 COP1 Encoding of Function Field 1255 //When rs=L1 1256 //Note: "1. Format type L is legal only if 64-bit 1257 //floating point operations are enabled." 1258 0x5: decode FUNCTION_HI { 1259 format FloatConvertOp { 1260 0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle); 1261 0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble); 1262 0x26: CP1Unimpl::cvt_ps_l(); 1263 } 1264 default: CP1Unimpl::unknown(); 1265 } 1266 1267 //Table A-17 MIPS64 COP1 Encoding of Function Field 1268 //When rs=PS1 1269 //Note: "1. Format type PS is legal only if 64-bit 1270 //floating point operations are enabled. " 1271 0x6: decode FUNCTION_HI { 1272 0x0: decode FUNCTION_LO { 1273 format Float64Op { 1274 0x0: add_ps({{ 1275 Fd1_sf = Fs1_sf + Ft2_sf; 1276 Fd2_sf = Fs2_sf + Ft2_sf; 1277 }}); 1278 0x1: sub_ps({{ 1279 Fd1_sf = Fs1_sf - Ft2_sf; 1280 Fd2_sf = Fs2_sf - Ft2_sf; 1281 }}); 1282 0x2: mul_ps({{ 1283 Fd1_sf = Fs1_sf * Ft2_sf; 1284 Fd2_sf = Fs2_sf * Ft2_sf; 1285 }}); 1286 0x5: abs_ps({{ 1287 Fd1_sf = fabs(Fs1_sf); 1288 Fd2_sf = fabs(Fs2_sf); 1289 }}); 1290 0x6: mov_ps({{ 1291 Fd1_sf = Fs1_sf; 1292 Fd2_sf = Fs2_sf; 1293 }}); 1294 0x7: neg_ps({{ 1295 Fd1_sf = -(Fs1_sf); 1296 Fd2_sf = -(Fs2_sf); 1297 }}); 1298 default: CP1Unimpl::unknown(); 1299 } 1300 } 1301 0x1: CP1Unimpl::unknown(); 1302 0x2: decode FUNCTION_LO { 1303 0x1: decode MOVCF { 1304 format Float64Op { 1305 0x0: movf_ps({{ 1306 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1307 Fs1 : Fd1; 1308 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1309 Fs2 : Fd2; 1310 }}); 1311 0x1: movt_ps({{ 1312 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1313 Fs1 : Fd1; 1314 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1315 Fs2 : Fd2; 1316 }}); 1317 } 1318 } 1319 1320 format Float64Op { 1321 0x2: movz_ps({{ 1322 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1323 Fs1 : Fd1; 1324 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1325 Fs2 : Fd2; 1326 }}); 1327 0x3: movn_ps({{ 1328 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1329 Fs1 : Fd1; 1330 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1331 Fs2 : Fd2; 1332 }}); 1333 } 1334 default: CP1Unimpl::unknown(); 1335 } 1336 0x3: CP1Unimpl::unknown(); 1337 0x4: decode FUNCTION_LO { 1338 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }}); 1339 default: CP1Unimpl::unknown(); 1340 } 1341 1342 0x5: decode FUNCTION_LO { 1343 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }}); 1344 format Float64Op { 1345 0x4: pll({{ 1346 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw; 1347 }}); 1348 0x5: plu({{ 1349 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw; 1350 }}); 1351 0x6: pul({{ 1352 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw; 1353 }}); 1354 0x7: puu({{ 1355 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw; 1356 }}); 1357 } 1358 default: CP1Unimpl::unknown(); 1359 } 1360 1361 0x6: decode FUNCTION_LO { 1362 format FloatPSCompareOp { 1363 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1364 UnorderedFalse); 1365 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1366 UnorderedTrue); 1367 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1368 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1369 UnorderedFalse); 1370 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1371 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1372 UnorderedTrue); 1373 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1374 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1375 UnorderedFalse); 1376 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }}, 1377 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1378 UnorderedTrue); 1379 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }}, 1380 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1381 UnorderedFalse); 1382 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1383 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1384 UnorderedTrue); 1385 } 1386 } 1387 1388 0x7: decode FUNCTION_LO { 1389 format FloatPSCompareOp { 1390 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1391 UnorderedFalse, QnanException); 1392 0x1: c_ngle_ps({{ cond1 = 0; }}, 1393 {{ cond2 = 0; }}, 1394 UnorderedTrue, QnanException); 1395 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1396 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1397 UnorderedFalse, QnanException); 1398 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1399 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1400 UnorderedTrue, QnanException); 1401 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1402 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1403 UnorderedFalse, QnanException); 1404 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1405 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1406 UnorderedTrue, QnanException); 1407 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1408 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1409 UnorderedFalse, QnanException); 1410 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1411 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1412 UnorderedTrue, QnanException); 1413 } 1414 } 1415 } 1416 } 1417 default: CP1Unimpl::unknown(); 1418 } 1419 } 1420 1421 //Table A-19 MIPS32 COP2 Encoding of rs Field 1422 0x2: decode RS_MSB { 1423 format CP2Unimpl { 1424 0x0: decode RS_HI { 1425 0x0: decode RS_LO { 1426 0x0: mfc2(); 1427 0x2: cfc2(); 1428 0x3: mfhc2(); 1429 0x4: mtc2(); 1430 0x6: ctc2(); 1431 0x7: mftc2(); 1432 default: unknown(); 1433 } 1434 1435 0x1: decode ND { 1436 0x0: decode TF { 1437 0x0: bc2f(); 1438 0x1: bc2t(); 1439 default: unknown(); 1440 } 1441 1442 0x1: decode TF { 1443 0x0: bc2fl(); 1444 0x1: bc2tl(); 1445 default: unknown(); 1446 } 1447 default: unknown(); 1448 1449 } 1450 default: unknown(); 1451 } 1452 default: unknown(); 1453 } 1454 } 1455 1456 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1457 //Note: "COP1X instructions are legal only if 64-bit floating point 1458 //operations are enabled." 1459 0x3: decode FUNCTION_HI { 1460 0x0: decode FUNCTION_LO { 1461 format LoadIndexedMemory { 1462 0x0: lwxc1({{ Fd_uw = Mem_uw; }}); 1463 0x1: ldxc1({{ Fd_ud = Mem_ud; }}); 1464 0x5: luxc1({{ Fd_ud = Mem_ud; }}, 1465 {{ EA = (Rs + Rt) & ~7; }}); 1466 } 1467 } 1468 1469 0x1: decode FUNCTION_LO { 1470 format StoreIndexedMemory { 1471 0x0: swxc1({{ Mem_uw = Fs_uw; }}); 1472 0x1: sdxc1({{ Mem_ud = Fs_ud; }}); 1473 0x5: suxc1({{ Mem_ud = Fs_ud; }}, 1474 {{ EA = (Rs + Rt) & ~7; }}); 1475 } 1476 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1477 } 1478 1479 0x3: decode FUNCTION_LO { 1480 0x6: Float64Op::alnv_ps({{ 1481 if (Rs<2:0> == 0) { 1482 Fd_ud = Fs_ud; 1483 } else if (Rs<2:0> == 4) { 1484 if (GuestByteOrder == BigEndianByteOrder) 1485 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; 1486 else 1487 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; 1488 } else { 1489 Fd_ud = Fd_ud; 1490 } 1491 }}); 1492 } 1493 1494 format FloatAccOp { 1495 0x4: decode FUNCTION_LO { 1496 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }}); 1497 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }}); 1498 0x6: madd_ps({{ 1499 Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df; 1500 Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df; 1501 }}); 1502 } 1503 1504 0x5: decode FUNCTION_LO { 1505 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }}); 1506 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }}); 1507 0x6: msub_ps({{ 1508 Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df; 1509 Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df; 1510 }}); 1511 } 1512 1513 0x6: decode FUNCTION_LO { 1514 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }}); 1515 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }}); 1516 0x6: nmadd_ps({{ 1517 Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df); 1518 Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df); 1519 }}); 1520 } 1521 1522 0x7: decode FUNCTION_LO { 1523 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }}); 1524 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }}); 1525 0x6: nmsub_ps({{ 1526 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df); 1527 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df); 1528 }}); 1529 } 1530 } 1531 } 1532 1533 format Branch { 1534 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely); 1535 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely); 1536 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely); 1537 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely); 1538 } 1539 } 1540 1541 0x3: decode OPCODE_LO { 1542 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1543 0x4: decode FUNCTION_HI { 1544 0x0: decode FUNCTION_LO { 1545 0x2: IntOp::mul({{ 1546 int64_t temp1 = Rs_sd * Rt_sd; 1547 Rd_sw = temp1<31:0>; 1548 }}, IntMultOp); 1549 1550 format HiLoRdSelValOp { 1551 0x0: madd({{ 1552 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1553 (Rs_sd * Rt_sd); 1554 }}, IntMultOp); 1555 0x1: maddu({{ 1556 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1557 (Rs_ud * Rt_ud); 1558 }}, IntMultOp); 1559 0x4: msub({{ 1560 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1561 (Rs_sd * Rt_sd); 1562 }}, IntMultOp); 1563 0x5: msubu({{ 1564 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1565 (Rs_ud * Rt_ud); 1566 }}, IntMultOp); 1567 } 1568 } 1569 1570 0x4: decode FUNCTION_LO { 1571 format BasicOp { 1572 0x0: clz({{ 1573 int cnt = 32; 1574 for (int idx = 31; idx >= 0; idx--) { 1575 if (Rs<idx:idx> == 1) { 1576 cnt = 31 - idx; 1577 break; 1578 } 1579 } 1580 Rd_uw = cnt; 1581 }}); 1582 0x1: clo({{ 1583 int cnt = 32; 1584 for (int idx = 31; idx >= 0; idx--) { 1585 if (Rs<idx:idx> == 0) { 1586 cnt = 31 - idx; 1587 break; 1588 } 1589 } 1590 Rd_uw = cnt; 1591 }}); 1592 } 1593 } 1594 1595 0x7: decode FUNCTION_LO { 1596 0x7: FailUnimpl::sdbbp(); 1597 } 1598 } 1599 1600 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1601 //of the Architecture 1602 0x7: decode FUNCTION_HI { 1603 0x0: decode FUNCTION_LO { 1604 format BasicOp { 1605 0x0: ext({{ Rt_uw = bits(Rs_uw, MSB+LSB, LSB); }}); 1606 0x4: ins({{ 1607 Rt_uw = bits(Rt_uw, 31, MSB+1) << (MSB+1) | 1608 bits(Rs_uw, MSB-LSB, 0) << LSB | 1609 bits(Rt_uw, LSB-1, 0); 1610 }}); 1611 } 1612 } 1613 1614 0x1: decode FUNCTION_LO { 1615 format MT_Control { 1616 0x0: fork({{ 1617 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1618 }}, UserMode); 1619 0x1: yield({{ 1620 Rd_sw = yieldThread(xc->tcBase(), fault, Rs_sw, 1621 YQMask); 1622 }}, UserMode); 1623 } 1624 1625 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1626 0x2: decode OP_HI { 1627 0x0: decode OP_LO { 1628 format LoadIndexedMemory { 1629 0x0: lwx({{ Rd_sw = Mem_sw; }}); 1630 0x4: lhx({{ Rd_sw = Mem_sh; }}); 1631 0x6: lbux({{ Rd_uw = Mem_ub; }}); 1632 } 1633 } 1634 } 1635 0x4: DspIntOp::insv({{ 1636 int pos = dspctl<5:0>; 1637 int size = dspctl<12:7> - 1; 1638 Rt_uw = insertBits(Rt_uw, pos+size, 1639 pos, Rs_uw<size:0>); 1640 }}); 1641 } 1642 1643 0x2: decode FUNCTION_LO { 1644 1645 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1646 //(DSP ASE MANUAL) 1647 0x0: decode OP_HI { 1648 0x0: decode OP_LO { 1649 format DspIntOp { 1650 0x0: addu_qb({{ 1651 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1652 NOSATURATE, UNSIGNED, &dspctl); 1653 }}); 1654 0x1: subu_qb({{ 1655 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1656 NOSATURATE, UNSIGNED, &dspctl); 1657 }}); 1658 0x4: addu_s_qb({{ 1659 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1660 SATURATE, UNSIGNED, &dspctl); 1661 }}); 1662 0x5: subu_s_qb({{ 1663 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1664 SATURATE, UNSIGNED, &dspctl); 1665 }}); 1666 0x6: muleu_s_ph_qbl({{ 1667 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1668 MODE_L, &dspctl); 1669 }}, IntMultOp); 1670 0x7: muleu_s_ph_qbr({{ 1671 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1672 MODE_R, &dspctl); 1673 }}, IntMultOp); 1674 } 1675 } 1676 0x1: decode OP_LO { 1677 format DspIntOp { 1678 0x0: addu_ph({{ 1679 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1680 NOSATURATE, UNSIGNED, &dspctl); 1681 }}); 1682 0x1: subu_ph({{ 1683 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1684 NOSATURATE, UNSIGNED, &dspctl); 1685 }}); 1686 0x2: addq_ph({{ 1687 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1688 NOSATURATE, SIGNED, &dspctl); 1689 }}); 1690 0x3: subq_ph({{ 1691 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1692 NOSATURATE, SIGNED, &dspctl); 1693 }}); 1694 0x4: addu_s_ph({{ 1695 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1696 SATURATE, UNSIGNED, &dspctl); 1697 }}); 1698 0x5: subu_s_ph({{ 1699 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1700 SATURATE, UNSIGNED, &dspctl); 1701 }}); 1702 0x6: addq_s_ph({{ 1703 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1704 SATURATE, SIGNED, &dspctl); 1705 }}); 1706 0x7: subq_s_ph({{ 1707 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1708 SATURATE, SIGNED, &dspctl); 1709 }}); 1710 } 1711 } 1712 0x2: decode OP_LO { 1713 format DspIntOp { 1714 0x0: addsc({{ 1715 int64_t dresult; 1716 dresult = Rs_ud + Rt_ud; 1717 Rd_sw = dresult<31:0>; 1718 dspctl = insertBits(dspctl, 13, 13, 1719 dresult<32:32>); 1720 }}); 1721 0x1: addwc({{ 1722 int64_t dresult; 1723 dresult = Rs_sd + Rt_sd + dspctl<13:13>; 1724 Rd_sw = dresult<31:0>; 1725 if (dresult<32:32> != dresult<31:31>) 1726 dspctl = insertBits(dspctl, 20, 20, 1); 1727 }}); 1728 0x2: modsub({{ 1729 Rd_sw = (Rs_sw == 0) ? Rt_sw<23:8> : 1730 Rs_sw - Rt_sw<7:0>; 1731 }}); 1732 0x4: raddu_w_qb({{ 1733 Rd_uw = Rs_uw<31:24> + Rs_uw<23:16> + 1734 Rs_uw<15:8> + Rs_uw<7:0>; 1735 }}); 1736 0x6: addq_s_w({{ 1737 Rd_sw = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W, 1738 SATURATE, SIGNED, &dspctl); 1739 }}); 1740 0x7: subq_s_w({{ 1741 Rd_sw = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W, 1742 SATURATE, SIGNED, &dspctl); 1743 }}); 1744 } 1745 } 1746 0x3: decode OP_LO { 1747 format DspIntOp { 1748 0x4: muleq_s_w_phl({{ 1749 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1750 MODE_L, &dspctl); 1751 }}, IntMultOp); 1752 0x5: muleq_s_w_phr({{ 1753 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1754 MODE_R, &dspctl); 1755 }}, IntMultOp); 1756 0x6: mulq_s_ph({{ 1757 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1758 SATURATE, NOROUND, &dspctl); 1759 }}, IntMultOp); 1760 0x7: mulq_rs_ph({{ 1761 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1762 SATURATE, ROUND, &dspctl); 1763 }}, IntMultOp); 1764 } 1765 } 1766 } 1767 1768 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1769 //(DSP ASE MANUAL) 1770 0x1: decode OP_HI { 1771 0x0: decode OP_LO { 1772 format DspIntOp { 1773 0x0: cmpu_eq_qb({{ 1774 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1775 UNSIGNED, CMP_EQ, &dspctl); 1776 }}); 1777 0x1: cmpu_lt_qb({{ 1778 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1779 UNSIGNED, CMP_LT, &dspctl); 1780 }}); 1781 0x2: cmpu_le_qb({{ 1782 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1783 UNSIGNED, CMP_LE, &dspctl); 1784 }}); 1785 0x3: pick_qb({{ 1786 Rd_uw = dspPick(Rs_uw, Rt_uw, 1787 SIMD_FMT_QB, &dspctl); 1788 }}); 1789 0x4: cmpgu_eq_qb({{ 1790 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1791 UNSIGNED, CMP_EQ ); 1792 }}); 1793 0x5: cmpgu_lt_qb({{ 1794 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1795 UNSIGNED, CMP_LT); 1796 }}); 1797 0x6: cmpgu_le_qb({{ 1798 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1799 UNSIGNED, CMP_LE); 1800 }}); 1801 } 1802 } 1803 0x1: decode OP_LO { 1804 format DspIntOp { 1805 0x0: cmp_eq_ph({{ 1806 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1807 SIGNED, CMP_EQ, &dspctl); 1808 }}); 1809 0x1: cmp_lt_ph({{ 1810 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1811 SIGNED, CMP_LT, &dspctl); 1812 }}); 1813 0x2: cmp_le_ph({{ 1814 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1815 SIGNED, CMP_LE, &dspctl); 1816 }}); 1817 0x3: pick_ph({{ 1818 Rd_uw = dspPick(Rs_uw, Rt_uw, 1819 SIMD_FMT_PH, &dspctl); 1820 }}); 1821 0x4: precrq_qb_ph({{ 1822 Rd_uw = Rs_uw<31:24> << 24 | 1823 Rs_uw<15:8> << 16 | 1824 Rt_uw<31:24> << 8 | 1825 Rt_uw<15:8>; 1826 }}); 1827 0x5: precr_qb_ph({{ 1828 Rd_uw = Rs_uw<23:16> << 24 | 1829 Rs_uw<7:0> << 16 | 1830 Rt_uw<23:16> << 8 | 1831 Rt_uw<7:0>; 1832 }}); 1833 0x6: packrl_ph({{ 1834 Rd_uw = dspPack(Rs_uw, Rt_uw, SIMD_FMT_PH); 1835 }}); 1836 0x7: precrqu_s_qb_ph({{ 1837 Rd_uw = dspPrecrqu(Rs_uw, Rt_uw, &dspctl); 1838 }}); 1839 } 1840 } 1841 0x2: decode OP_LO { 1842 format DspIntOp { 1843 0x4: precrq_ph_w({{ 1844 Rd_uw = Rs_uw<31:16> << 16 | Rt_uw<31:16>; 1845 }}); 1846 0x5: precrq_rs_ph_w({{ 1847 Rd_uw = dspPrecrq(Rs_uw, Rt_uw, 1848 SIMD_FMT_W, &dspctl); 1849 }}); 1850 } 1851 } 1852 0x3: decode OP_LO { 1853 format DspIntOp { 1854 0x0: cmpgdu_eq_qb({{ 1855 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1856 UNSIGNED, CMP_EQ, &dspctl); 1857 }}); 1858 0x1: cmpgdu_lt_qb({{ 1859 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1860 UNSIGNED, CMP_LT, &dspctl); 1861 }}); 1862 0x2: cmpgdu_le_qb({{ 1863 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1864 UNSIGNED, CMP_LE, &dspctl); 1865 }}); 1866 0x6: precr_sra_ph_w({{ 1867 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1868 SIMD_FMT_W, NOROUND); 1869 }}); 1870 0x7: precr_sra_r_ph_w({{ 1871 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1872 SIMD_FMT_W, ROUND); 1873 }}); 1874 } 1875 } 1876 } 1877 1878 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1879 //(DSP ASE MANUAL) 1880 0x2: decode OP_HI { 1881 0x0: decode OP_LO { 1882 format DspIntOp { 1883 0x1: absq_s_qb({{ 1884 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl); 1885 }}); 1886 0x2: repl_qb({{ 1887 Rd_uw = RS_RT<7:0> << 24 | 1888 RS_RT<7:0> << 16 | 1889 RS_RT<7:0> << 8 | 1890 RS_RT<7:0>; 1891 }}); 1892 0x3: replv_qb({{ 1893 Rd_sw = Rt_uw<7:0> << 24 | 1894 Rt_uw<7:0> << 16 | 1895 Rt_uw<7:0> << 8 | 1896 Rt_uw<7:0>; 1897 }}); 1898 0x4: precequ_ph_qbl({{ 1899 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1900 SIMD_FMT_PH, SIGNED, MODE_L); 1901 }}); 1902 0x5: precequ_ph_qbr({{ 1903 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1904 SIMD_FMT_PH, SIGNED, MODE_R); 1905 }}); 1906 0x6: precequ_ph_qbla({{ 1907 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1908 SIMD_FMT_PH, SIGNED, MODE_LA); 1909 }}); 1910 0x7: precequ_ph_qbra({{ 1911 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1912 SIMD_FMT_PH, SIGNED, MODE_RA); 1913 }}); 1914 } 1915 } 1916 0x1: decode OP_LO { 1917 format DspIntOp { 1918 0x1: absq_s_ph({{ 1919 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl); 1920 }}); 1921 0x2: repl_ph({{ 1922 Rd_uw = (sext<10>(RS_RT))<15:0> << 16 | 1923 (sext<10>(RS_RT))<15:0>; 1924 }}); 1925 0x3: replv_ph({{ 1926 Rd_uw = Rt_uw<15:0> << 16 | 1927 Rt_uw<15:0>; 1928 }}); 1929 0x4: preceq_w_phl({{ 1930 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1931 SIMD_FMT_W, SIGNED, MODE_L); 1932 }}); 1933 0x5: preceq_w_phr({{ 1934 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1935 SIMD_FMT_W, SIGNED, MODE_R); 1936 }}); 1937 } 1938 } 1939 0x2: decode OP_LO { 1940 format DspIntOp { 1941 0x1: absq_s_w({{ 1942 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl); 1943 }}); 1944 } 1945 } 1946 0x3: decode OP_LO { 1947 0x3: IntOp::bitrev({{ 1948 Rd_uw = bitrev( Rt_uw<15:0> ); 1949 }}); 1950 format DspIntOp { 1951 0x4: preceu_ph_qbl({{ 1952 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1953 UNSIGNED, SIMD_FMT_PH, 1954 UNSIGNED, MODE_L); 1955 }}); 1956 0x5: preceu_ph_qbr({{ 1957 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1958 UNSIGNED, SIMD_FMT_PH, 1959 UNSIGNED, MODE_R ); 1960 }}); 1961 0x6: preceu_ph_qbla({{ 1962 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1963 UNSIGNED, SIMD_FMT_PH, 1964 UNSIGNED, MODE_LA ); 1965 }}); 1966 0x7: preceu_ph_qbra({{ 1967 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1968 UNSIGNED, SIMD_FMT_PH, 1969 UNSIGNED, MODE_RA); 1970 }}); 1971 } 1972 } 1973 } 1974 1975 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 1976 //(DSP ASE MANUAL) 1977 0x3: decode OP_HI { 1978 0x0: decode OP_LO { 1979 format DspIntOp { 1980 0x0: shll_qb({{ 1981 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_QB, 1982 NOSATURATE, UNSIGNED, &dspctl); 1983 }}); 1984 0x1: shrl_qb({{ 1985 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_QB, 1986 UNSIGNED); 1987 }}); 1988 0x2: shllv_qb({{ 1989 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB, 1990 NOSATURATE, UNSIGNED, &dspctl); 1991 }}); 1992 0x3: shrlv_qb({{ 1993 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB, 1994 UNSIGNED); 1995 }}); 1996 0x4: shra_qb({{ 1997 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 1998 NOROUND, SIGNED, &dspctl); 1999 }}); 2000 0x5: shra_r_qb({{ 2001 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2002 ROUND, SIGNED, &dspctl); 2003 }}); 2004 0x6: shrav_qb({{ 2005 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2006 NOROUND, SIGNED, &dspctl); 2007 }}); 2008 0x7: shrav_r_qb({{ 2009 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2010 ROUND, SIGNED, &dspctl); 2011 }}); 2012 } 2013 } 2014 0x1: decode OP_LO { 2015 format DspIntOp { 2016 0x0: shll_ph({{ 2017 Rd_uw = dspShll(Rt_uw, RS, SIMD_FMT_PH, 2018 NOSATURATE, SIGNED, &dspctl); 2019 }}); 2020 0x1: shra_ph({{ 2021 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2022 NOROUND, SIGNED, &dspctl); 2023 }}); 2024 0x2: shllv_ph({{ 2025 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2026 NOSATURATE, SIGNED, &dspctl); 2027 }}); 2028 0x3: shrav_ph({{ 2029 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2030 NOROUND, SIGNED, &dspctl); 2031 }}); 2032 0x4: shll_s_ph({{ 2033 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_PH, 2034 SATURATE, SIGNED, &dspctl); 2035 }}); 2036 0x5: shra_r_ph({{ 2037 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2038 ROUND, SIGNED, &dspctl); 2039 }}); 2040 0x6: shllv_s_ph({{ 2041 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2042 SATURATE, SIGNED, &dspctl); 2043 }}); 2044 0x7: shrav_r_ph({{ 2045 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2046 ROUND, SIGNED, &dspctl); 2047 }}); 2048 } 2049 } 2050 0x2: decode OP_LO { 2051 format DspIntOp { 2052 0x4: shll_s_w({{ 2053 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_W, 2054 SATURATE, SIGNED, &dspctl); 2055 }}); 2056 0x5: shra_r_w({{ 2057 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_W, 2058 ROUND, SIGNED, &dspctl); 2059 }}); 2060 0x6: shllv_s_w({{ 2061 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W, 2062 SATURATE, SIGNED, &dspctl); 2063 }}); 2064 0x7: shrav_r_w({{ 2065 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W, 2066 ROUND, SIGNED, &dspctl); 2067 }}); 2068 } 2069 } 2070 0x3: decode OP_LO { 2071 format DspIntOp { 2072 0x1: shrl_ph({{ 2073 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_PH, 2074 UNSIGNED); 2075 }}); 2076 0x3: shrlv_ph({{ 2077 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH, 2078 UNSIGNED); 2079 }}); 2080 } 2081 } 2082 } 2083 } 2084 2085 0x3: decode FUNCTION_LO { 2086 2087 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2088 //(DSP ASE Rev2 Manual) 2089 0x0: decode OP_HI { 2090 0x0: decode OP_LO { 2091 format DspIntOp { 2092 0x0: adduh_qb({{ 2093 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2094 NOROUND, UNSIGNED); 2095 }}); 2096 0x1: subuh_qb({{ 2097 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2098 NOROUND, UNSIGNED); 2099 }}); 2100 0x2: adduh_r_qb({{ 2101 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2102 ROUND, UNSIGNED); 2103 }}); 2104 0x3: subuh_r_qb({{ 2105 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2106 ROUND, UNSIGNED); 2107 }}); 2108 } 2109 } 2110 0x1: decode OP_LO { 2111 format DspIntOp { 2112 0x0: addqh_ph({{ 2113 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2114 NOROUND, SIGNED); 2115 }}); 2116 0x1: subqh_ph({{ 2117 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2118 NOROUND, SIGNED); 2119 }}); 2120 0x2: addqh_r_ph({{ 2121 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2122 ROUND, SIGNED); 2123 }}); 2124 0x3: subqh_r_ph({{ 2125 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2126 ROUND, SIGNED); 2127 }}); 2128 0x4: mul_ph({{ 2129 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2130 NOSATURATE, &dspctl); 2131 }}, IntMultOp); 2132 0x6: mul_s_ph({{ 2133 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2134 SATURATE, &dspctl); 2135 }}, IntMultOp); 2136 } 2137 } 2138 0x2: decode OP_LO { 2139 format DspIntOp { 2140 0x0: addqh_w({{ 2141 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2142 NOROUND, SIGNED); 2143 }}); 2144 0x1: subqh_w({{ 2145 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2146 NOROUND, SIGNED); 2147 }}); 2148 0x2: addqh_r_w({{ 2149 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2150 ROUND, SIGNED); 2151 }}); 2152 0x3: subqh_r_w({{ 2153 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2154 ROUND, SIGNED); 2155 }}); 2156 0x6: mulq_s_w({{ 2157 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2158 SATURATE, NOROUND, &dspctl); 2159 }}, IntMultOp); 2160 0x7: mulq_rs_w({{ 2161 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2162 SATURATE, ROUND, &dspctl); 2163 }}, IntMultOp); 2164 } 2165 } 2166 } 2167 } 2168 2169 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2170 0x4: decode SA { 2171 format BasicOp { 2172 0x02: wsbh({{ 2173 Rd_uw = Rt_uw<23:16> << 24 | 2174 Rt_uw<31:24> << 16 | 2175 Rt_uw<7:0> << 8 | 2176 Rt_uw<15:8>; 2177 }}); 2178 0x10: seb({{ Rd_sw = Rt_sb; }}); 2179 0x18: seh({{ Rd_sw = Rt_sh; }}); 2180 } 2181 } 2182 2183 0x6: decode FUNCTION_LO { 2184 2185 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2186 //(DSP ASE MANUAL) 2187 0x0: decode OP_HI { 2188 0x0: decode OP_LO { 2189 format DspHiLoOp { 2190 0x0: dpa_w_ph({{ 2191 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2192 SIMD_FMT_PH, SIGNED, MODE_L); 2193 }}, IntMultOp); 2194 0x1: dps_w_ph({{ 2195 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2196 SIMD_FMT_PH, SIGNED, MODE_L); 2197 }}, IntMultOp); 2198 0x2: mulsa_w_ph({{ 2199 dspac = dspMulsa(dspac, Rs_sw, Rt_sw, 2200 ACDST, SIMD_FMT_PH ); 2201 }}, IntMultOp); 2202 0x3: dpau_h_qbl({{ 2203 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2204 SIMD_FMT_QB, UNSIGNED, MODE_L); 2205 }}, IntMultOp); 2206 0x4: dpaq_s_w_ph({{ 2207 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2208 ACDST, SIMD_FMT_PH, 2209 SIMD_FMT_W, NOSATURATE, 2210 MODE_L, &dspctl); 2211 }}, IntMultOp); 2212 0x5: dpsq_s_w_ph({{ 2213 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2214 ACDST, SIMD_FMT_PH, 2215 SIMD_FMT_W, NOSATURATE, 2216 MODE_L, &dspctl); 2217 }}, IntMultOp); 2218 0x6: mulsaq_s_w_ph({{ 2219 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw, 2220 ACDST, SIMD_FMT_PH, 2221 &dspctl); 2222 }}, IntMultOp); 2223 0x7: dpau_h_qbr({{ 2224 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2225 SIMD_FMT_QB, UNSIGNED, MODE_R); 2226 }}, IntMultOp); 2227 } 2228 } 2229 0x1: decode OP_LO { 2230 format DspHiLoOp { 2231 0x0: dpax_w_ph({{ 2232 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2233 SIMD_FMT_PH, SIGNED, MODE_X); 2234 }}, IntMultOp); 2235 0x1: dpsx_w_ph({{ 2236 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2237 SIMD_FMT_PH, SIGNED, MODE_X); 2238 }}, IntMultOp); 2239 0x3: dpsu_h_qbl({{ 2240 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2241 SIMD_FMT_QB, UNSIGNED, MODE_L); 2242 }}, IntMultOp); 2243 0x4: dpaq_sa_l_w({{ 2244 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2245 ACDST, SIMD_FMT_W, 2246 SIMD_FMT_L, SATURATE, 2247 MODE_L, &dspctl); 2248 }}, IntMultOp); 2249 0x5: dpsq_sa_l_w({{ 2250 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2251 ACDST, SIMD_FMT_W, 2252 SIMD_FMT_L, SATURATE, 2253 MODE_L, &dspctl); 2254 }}, IntMultOp); 2255 0x7: dpsu_h_qbr({{ 2256 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2257 SIMD_FMT_QB, UNSIGNED, MODE_R); 2258 }}, IntMultOp); 2259 } 2260 } 2261 0x2: decode OP_LO { 2262 format DspHiLoOp { 2263 0x0: maq_sa_w_phl({{ 2264 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2265 ACDST, SIMD_FMT_PH, 2266 MODE_L, SATURATE, &dspctl); 2267 }}, IntMultOp); 2268 0x2: maq_sa_w_phr({{ 2269 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2270 ACDST, SIMD_FMT_PH, 2271 MODE_R, SATURATE, &dspctl); 2272 }}, IntMultOp); 2273 0x4: maq_s_w_phl({{ 2274 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2275 ACDST, SIMD_FMT_PH, 2276 MODE_L, NOSATURATE, &dspctl); 2277 }}, IntMultOp); 2278 0x6: maq_s_w_phr({{ 2279 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2280 ACDST, SIMD_FMT_PH, 2281 MODE_R, NOSATURATE, &dspctl); 2282 }}, IntMultOp); 2283 } 2284 } 2285 0x3: decode OP_LO { 2286 format DspHiLoOp { 2287 0x0: dpaqx_s_w_ph({{ 2288 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2289 ACDST, SIMD_FMT_PH, 2290 SIMD_FMT_W, NOSATURATE, 2291 MODE_X, &dspctl); 2292 }}, IntMultOp); 2293 0x1: dpsqx_s_w_ph({{ 2294 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2295 ACDST, SIMD_FMT_PH, 2296 SIMD_FMT_W, NOSATURATE, 2297 MODE_X, &dspctl); 2298 }}, IntMultOp); 2299 0x2: dpaqx_sa_w_ph({{ 2300 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2301 ACDST, SIMD_FMT_PH, 2302 SIMD_FMT_W, SATURATE, 2303 MODE_X, &dspctl); 2304 }}, IntMultOp); 2305 0x3: dpsqx_sa_w_ph({{ 2306 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2307 ACDST, SIMD_FMT_PH, 2308 SIMD_FMT_W, SATURATE, 2309 MODE_X, &dspctl); 2310 }}, IntMultOp); 2311 } 2312 } 2313 } 2314 2315 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2316 0x1: decode OP_HI { 2317 0x0: decode OP_LO { 2318 format IntOp { 2319 0x0: append({{ 2320 Rt_uw = (Rt_uw << RD) | bits(Rs_uw, RD - 1, 0); 2321 }}); 2322 0x1: prepend({{ 2323 Rt_uw = (Rt_uw >> RD) | 2324 (bits(Rs_uw, RD - 1, 0) << (32 - RD)); 2325 }}); 2326 } 2327 } 2328 0x2: decode OP_LO { 2329 format IntOp { 2330 0x0: balign({{ 2331 Rt_uw = (Rt_uw << (8 * BP)) | 2332 (Rs_uw >> (8 * (4 - BP))); 2333 }}); 2334 } 2335 } 2336 } 2337 2338 } 2339 0x7: decode FUNCTION_LO { 2340 2341 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2342 //(DSP ASE MANUAL) 2343 0x0: decode OP_HI { 2344 0x0: decode OP_LO { 2345 format DspHiLoOp { 2346 0x0: extr_w({{ 2347 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2348 NOROUND, NOSATURATE, &dspctl); 2349 }}); 2350 0x1: extrv_w({{ 2351 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2352 NOROUND, NOSATURATE, &dspctl); 2353 }}); 2354 0x2: extp({{ 2355 Rt_uw = dspExtp(dspac, RS, &dspctl); 2356 }}); 2357 0x3: extpv({{ 2358 Rt_uw = dspExtp(dspac, Rs_uw, &dspctl); 2359 }}); 2360 0x4: extr_r_w({{ 2361 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2362 ROUND, NOSATURATE, &dspctl); 2363 }}); 2364 0x5: extrv_r_w({{ 2365 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2366 ROUND, NOSATURATE, &dspctl); 2367 }}); 2368 0x6: extr_rs_w({{ 2369 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2370 ROUND, SATURATE, &dspctl); 2371 }}); 2372 0x7: extrv_rs_w({{ 2373 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2374 ROUND, SATURATE, &dspctl); 2375 }}); 2376 } 2377 } 2378 0x1: decode OP_LO { 2379 format DspHiLoOp { 2380 0x2: extpdp({{ 2381 Rt_uw = dspExtpd(dspac, RS, &dspctl); 2382 }}); 2383 0x3: extpdpv({{ 2384 Rt_uw = dspExtpd(dspac, Rs_uw, &dspctl); 2385 }}); 2386 0x6: extr_s_h({{ 2387 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2388 NOROUND, SATURATE, &dspctl); 2389 }}); 2390 0x7: extrv_s_h({{ 2391 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, Rs_uw, 2392 NOROUND, SATURATE, &dspctl); 2393 }}); 2394 } 2395 } 2396 0x2: decode OP_LO { 2397 format DspIntOp { 2398 0x2: rddsp({{ 2399 Rd_uw = readDSPControl(&dspctl, RDDSPMASK); 2400 }}); 2401 0x3: wrdsp({{ 2402 writeDSPControl(&dspctl, Rs_uw, WRDSPMASK); 2403 }}); 2404 } 2405 } 2406 0x3: decode OP_LO { 2407 format DspHiLoOp { 2408 0x2: shilo({{ 2409 if (sext<6>(HILOSA) < 0) { 2410 dspac = (uint64_t)dspac << 2411 -sext<6>(HILOSA); 2412 } else { 2413 dspac = (uint64_t)dspac >> 2414 sext<6>(HILOSA); 2415 } 2416 }}); 2417 0x3: shilov({{ 2418 if (sext<6>(Rs_sw<5:0>) < 0) { 2419 dspac = (uint64_t)dspac << 2420 -sext<6>(Rs_sw<5:0>); 2421 } else { 2422 dspac = (uint64_t)dspac >> 2423 sext<6>(Rs_sw<5:0>); 2424 } 2425 }}); 2426 0x7: mthlip({{ 2427 dspac = dspac << 32; 2428 dspac |= Rs_uw; 2429 dspctl = insertBits(dspctl, 5, 0, 2430 dspctl<5:0> + 32); 2431 }}); 2432 } 2433 } 2434 } 2435 0x3: decode OP default FailUnimpl::rdhwr() { 2436 0x0: decode FullSystem { 2437 0: decode RD { 2438 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2439 } 2440 } 2441 } 2442 } 2443 } 2444 } 2445 2446 0x4: decode OPCODE_LO { 2447 format LoadMemory { 2448 0x0: lb({{ Rt_sw = Mem_sb; }}); 2449 0x1: lh({{ Rt_sw = Mem_sh; }}); 2450 0x3: lw({{ Rt_sw = Mem_sw; }}); 2451 0x4: lbu({{ Rt_uw = Mem_ub;}}); 2452 0x5: lhu({{ Rt_uw = Mem_uh; }}); 2453 } 2454 2455 format LoadUnalignedMemory { 2456 0x2: lwl({{ 2457 uint32_t mem_shift = 24 - (8 * byte_offset); 2458 Rt_uw = mem_word << mem_shift | (Rt_uw & mask(mem_shift)); 2459 }}); 2460 0x6: lwr({{ 2461 uint32_t mem_shift = 8 * byte_offset; 2462 Rt_uw = (Rt_uw & (mask(mem_shift) << (32 - mem_shift))) | 2463 (mem_word >> mem_shift); 2464 }}); 2465 } 2466 } 2467 2468 0x5: decode OPCODE_LO { 2469 format StoreMemory { 2470 0x0: sb({{ Mem_ub = Rt<7:0>; }}); 2471 0x1: sh({{ Mem_uh = Rt<15:0>; }}); 2472 0x3: sw({{ Mem_uw = Rt<31:0>; }}); 2473 } 2474 2475 format StoreUnalignedMemory { 2476 0x2: swl({{ 2477 uint32_t reg_shift = 24 - (8 * byte_offset); 2478 uint32_t mem_shift = 32 - reg_shift; 2479 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2480 (Rt_uw >> reg_shift); 2481 }}); 2482 0x6: swr({{ 2483 uint32_t reg_shift = 8 * byte_offset; 2484 mem_word = Rt_uw << reg_shift | 2485 (mem_word & (mask(reg_shift))); 2486 }}); 2487 } 2488 format CP0Control { 2489 0x7: cache({{ 2490 //Addr CacheEA = Rs_uw + OFFSET; 2491 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2492 }}); 2493 } 2494 } 2495 2496 0x6: decode OPCODE_LO { 2497 format LoadMemory { 2498 0x0: ll({{ Rt_uw = Mem_uw; }}, mem_flags=LLSC); 2499 0x1: lwc1({{ Ft_uw = Mem_uw; }}); 2500 0x5: ldc1({{ Ft_ud = Mem_ud; }}); 2501 } 2502 0x2: CP2Unimpl::lwc2(); 2503 0x6: CP2Unimpl::ldc2(); 2504 0x3: Prefetch::pref(); 2505 } 2506 2507 2508 0x7: decode OPCODE_LO { 2509 0x0: StoreCond::sc({{ Mem_uw = Rt_uw; }}, 2510 {{ uint64_t tmp = write_result; 2511 Rt_uw = (tmp == 0 || tmp == 1) ? tmp : Rt_uw; 2512 }}, mem_flags=LLSC, 2513 inst_flags = IsStoreConditional); 2514 format StoreMemory { 2515 0x1: swc1({{ Mem_uw = Ft_uw; }}); 2516 0x5: sdc1({{ Mem_ud = Ft_ud; }}); 2517 } 2518 0x2: CP2Unimpl::swc2(); 2519 0x6: CP2Unimpl::sdc2(); 2520 } 2521} 2522 2523
| 844 Ptr->insertAt(newEntry, Random, SP); 845 }}); 846 847 0x08: tlbp({{ 848 Config3Reg config3 = Config3; 849 PageGrainReg pageGrain = PageGrain; 850 EntryHiReg entryHi = EntryHi; 851 int tlbIndex; 852 Addr vpn; 853 if (pageGrain.esp == 1 && config3.sp ==1) { 854 vpn = EntryHi >> 11; 855 } else { 856 // Mask off lower 2 bits 857 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 858 } 859 tlbIndex = xc->tcBase()->getITBPtr()-> 860 probeEntry(vpn, entryHi.asid); 861 // Check TLB for entry matching EntryHi 862 if (tlbIndex != -1) { 863 Index = tlbIndex; 864 } else { 865 // else, set Index = 1 << 31 866 Index = (1 << 31); 867 } 868 }}); 869 } 870 format CP0Unimpl { 871 0x20: wait(); 872 } 873 default: CP0Unimpl::unknown(); 874 } 875 } 876 877 //Table A-13 MIPS32 COP1 Encoding of rs Field 878 0x1: decode RS_MSB { 879 0x0: decode RS_HI { 880 0x0: decode RS_LO { 881 format CP1Control { 882 0x0: mfc1 ({{ Rt_uw = Fs_uw; }}); 883 884 0x2: cfc1({{ 885 switch (FS) { 886 case 0: 887 Rt = FIR; 888 break; 889 case 25: 890 Rt = (FCSR & 0xFE000000) >> 24 | 891 (FCSR & 0x00800000) >> 23; 892 break; 893 case 26: 894 Rt = (FCSR & 0x0003F07C); 895 break; 896 case 28: 897 Rt = (FCSR & 0x00000F80) | 898 (FCSR & 0x01000000) >> 21 | 899 (FCSR & 0x00000003); 900 break; 901 case 31: 902 Rt = FCSR; 903 break; 904 default: 905 warn("FP Control Value (%d) Not Valid"); 906 } 907 }}); 908 909 0x3: mfhc1({{ Rt_uw = Fs_ud<63:32>; }}); 910 911 0x4: mtc1({{ Fs_uw = Rt_uw; }}); 912 913 0x6: ctc1({{ 914 switch (FS) { 915 case 25: 916 FCSR = (Rt_uw<7:1> << 25) | // move 31-25 917 (FCSR & 0x01000000) | // bit 24 918 (FCSR & 0x004FFFFF); // bit 22-0 919 break; 920 case 26: 921 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 922 Rt_uw<17:12> << 12 | // bit 17-12 923 (FCSR & 0x00000F80) << 7 | // bit 11-7 924 Rt_uw<6:2> << 2 | // bit 6-2 925 (FCSR & 0x00000002); // bit 1-0 926 break; 927 case 28: 928 FCSR = (FCSR & 0xFE000000) | // move 31-25 929 Rt_uw<2:2> << 24 | // bit 24 930 (FCSR & 0x00FFF000) << 23 | // bit 23-12 931 Rt_uw<11:7> << 7 | // bit 24 932 (FCSR & 0x000007E) | 933 Rt_uw<1:0>; // bit 22-0 934 break; 935 case 31: 936 FCSR = Rt_uw; 937 break; 938 939 default: 940 panic("FP Control Value (%d) " 941 "Not Available. Ignoring Access " 942 "to Floating Control Status " 943 "Register", FS); 944 } 945 }}); 946 947 0x7: mthc1({{ 948 uint64_t fs_hi = Rt_uw; 949 uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF; 950 Fs_ud = (fs_hi << 32) | fs_lo; 951 }}); 952 953 } 954 format CP1Unimpl { 955 0x1: dmfc1(); 956 0x5: dmtc1(); 957 } 958 } 959 960 0x1: decode RS_LO { 961 0x0: decode ND { 962 format Branch { 963 0x0: decode TF { 964 0x0: bc1f({{ 965 cond = getCondCode(FCSR, BRANCH_CC) == 0; 966 }}); 967 0x1: bc1t({{ 968 cond = getCondCode(FCSR, BRANCH_CC) == 1; 969 }}); 970 } 971 0x1: decode TF { 972 0x0: bc1fl({{ 973 cond = getCondCode(FCSR, BRANCH_CC) == 0; 974 }}, Likely); 975 0x1: bc1tl({{ 976 cond = getCondCode(FCSR, BRANCH_CC) == 1; 977 }}, Likely); 978 } 979 } 980 } 981 format CP1Unimpl { 982 0x1: bc1any2(); 983 0x2: bc1any4(); 984 default: unknown(); 985 } 986 } 987 } 988 989 0x1: decode RS_HI { 990 0x2: decode RS_LO { 991 //Table A-14 MIPS32 COP1 Encoding of Function Field When 992 //rs=S (( single-precision floating point)) 993 0x0: decode FUNCTION_HI { 994 0x0: decode FUNCTION_LO { 995 format FloatOp { 996 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }}); 997 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }}); 998 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }}); 999 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }}); 1000 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }}); 1001 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }}); 1002 0x7: neg_s({{ Fd_sf = -Fs_sf; }}); 1003 } 1004 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }}); 1005 } 1006 0x1: decode FUNCTION_LO { 1007 format FloatConvertOp { 1008 0x0: round_l_s({{ val = Fs_sf; }}, 1009 ToLong, Round); 1010 0x1: trunc_l_s({{ val = Fs_sf; }}, 1011 ToLong, Trunc); 1012 0x2: ceil_l_s({{ val = Fs_sf;}}, 1013 ToLong, Ceil); 1014 0x3: floor_l_s({{ val = Fs_sf; }}, 1015 ToLong, Floor); 1016 0x4: round_w_s({{ val = Fs_sf; }}, 1017 ToWord, Round); 1018 0x5: trunc_w_s({{ val = Fs_sf; }}, 1019 ToWord, Trunc); 1020 0x6: ceil_w_s({{ val = Fs_sf; }}, 1021 ToWord, Ceil); 1022 0x7: floor_w_s({{ val = Fs_sf; }}, 1023 ToWord, Floor); 1024 } 1025 } 1026 1027 0x2: decode FUNCTION_LO { 1028 0x1: decode MOVCF { 1029 format BasicOp { 1030 0x0: movf_s({{ 1031 Fd = (getCondCode(FCSR,CC) == 0) ? 1032 Fs : Fd; 1033 }}); 1034 0x1: movt_s({{ 1035 Fd = (getCondCode(FCSR,CC) == 1) ? 1036 Fs : Fd; 1037 }}); 1038 } 1039 } 1040 1041 format BasicOp { 1042 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1043 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1044 } 1045 1046 format FloatOp { 1047 0x5: recip_s({{ Fd = 1 / Fs; }}); 1048 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 1049 } 1050 format CP1Unimpl { 1051 default: unknown(); 1052 } 1053 } 1054 0x3: CP1Unimpl::unknown(); 1055 1056 0x4: decode FUNCTION_LO { 1057 format FloatConvertOp { 1058 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble); 1059 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord); 1060 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong); 1061 } 1062 1063 0x6: FloatOp::cvt_ps_s({{ 1064 Fd_ud = (uint64_t) Fs_uw << 32 | 1065 (uint64_t) Ft_uw; 1066 }}); 1067 format CP1Unimpl { 1068 default: unknown(); 1069 } 1070 } 1071 0x5: CP1Unimpl::unknown(); 1072 1073 0x6: decode FUNCTION_LO { 1074 format FloatCompareOp { 1075 0x0: c_f_s({{ cond = 0; }}, 1076 SinglePrecision, UnorderedFalse); 1077 0x1: c_un_s({{ cond = 0; }}, 1078 SinglePrecision, UnorderedTrue); 1079 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }}, 1080 UnorderedFalse); 1081 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }}, 1082 UnorderedTrue); 1083 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }}, 1084 UnorderedFalse); 1085 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }}, 1086 UnorderedTrue); 1087 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }}, 1088 UnorderedFalse); 1089 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }}, 1090 UnorderedTrue); 1091 } 1092 } 1093 1094 0x7: decode FUNCTION_LO { 1095 format FloatCompareOp { 1096 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1097 UnorderedFalse, QnanException); 1098 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1099 UnorderedTrue, QnanException); 1100 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }}, 1101 UnorderedFalse, QnanException); 1102 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }}, 1103 UnorderedTrue, QnanException); 1104 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }}, 1105 UnorderedFalse, QnanException); 1106 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }}, 1107 UnorderedTrue, QnanException); 1108 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }}, 1109 UnorderedFalse, QnanException); 1110 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }}, 1111 UnorderedTrue, QnanException); 1112 } 1113 } 1114 } 1115 1116 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1117 //rs=D 1118 0x1: decode FUNCTION_HI { 1119 0x0: decode FUNCTION_LO { 1120 format FloatOp { 1121 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }}); 1122 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }}); 1123 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }}); 1124 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }}); 1125 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }}); 1126 0x5: abs_d({{ Fd_df = fabs(Fs_df); }}); 1127 0x7: neg_d({{ Fd_df = -1 * Fs_df; }}); 1128 } 1129 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }}); 1130 } 1131 1132 0x1: decode FUNCTION_LO { 1133 format FloatConvertOp { 1134 0x0: round_l_d({{ val = Fs_df; }}, 1135 ToLong, Round); 1136 0x1: trunc_l_d({{ val = Fs_df; }}, 1137 ToLong, Trunc); 1138 0x2: ceil_l_d({{ val = Fs_df; }}, 1139 ToLong, Ceil); 1140 0x3: floor_l_d({{ val = Fs_df; }}, 1141 ToLong, Floor); 1142 0x4: round_w_d({{ val = Fs_df; }}, 1143 ToWord, Round); 1144 0x5: trunc_w_d({{ val = Fs_df; }}, 1145 ToWord, Trunc); 1146 0x6: ceil_w_d({{ val = Fs_df; }}, 1147 ToWord, Ceil); 1148 0x7: floor_w_d({{ val = Fs_df; }}, 1149 ToWord, Floor); 1150 } 1151 } 1152 1153 0x2: decode FUNCTION_LO { 1154 0x1: decode MOVCF { 1155 format BasicOp { 1156 0x0: movf_d({{ 1157 Fd_df = (getCondCode(FCSR,CC) == 0) ? 1158 Fs_df : Fd_df; 1159 }}); 1160 0x1: movt_d({{ 1161 Fd_df = (getCondCode(FCSR,CC) == 1) ? 1162 Fs_df : Fd_df; 1163 }}); 1164 } 1165 } 1166 1167 format BasicOp { 1168 0x2: movz_d({{ 1169 Fd_df = (Rt == 0) ? Fs_df : Fd_df; 1170 }}); 1171 0x3: movn_d({{ 1172 Fd_df = (Rt != 0) ? Fs_df : Fd_df; 1173 }}); 1174 } 1175 1176 format FloatOp { 1177 0x5: recip_d({{ Fd_df = 1 / Fs_df; }}); 1178 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }}); 1179 } 1180 format CP1Unimpl { 1181 default: unknown(); 1182 } 1183 1184 } 1185 0x4: decode FUNCTION_LO { 1186 format FloatConvertOp { 1187 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle); 1188 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord); 1189 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong); 1190 } 1191 default: CP1Unimpl::unknown(); 1192 } 1193 1194 0x6: decode FUNCTION_LO { 1195 format FloatCompareOp { 1196 0x0: c_f_d({{ cond = 0; }}, 1197 DoublePrecision, UnorderedFalse); 1198 0x1: c_un_d({{ cond = 0; }}, 1199 DoublePrecision, UnorderedTrue); 1200 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }}, 1201 UnorderedFalse); 1202 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }}, 1203 UnorderedTrue); 1204 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }}, 1205 UnorderedFalse); 1206 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }}, 1207 UnorderedTrue); 1208 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }}, 1209 UnorderedFalse); 1210 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }}, 1211 UnorderedTrue); 1212 } 1213 } 1214 1215 0x7: decode FUNCTION_LO { 1216 format FloatCompareOp { 1217 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1218 UnorderedFalse, QnanException); 1219 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1220 UnorderedTrue, QnanException); 1221 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }}, 1222 UnorderedFalse, QnanException); 1223 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }}, 1224 UnorderedTrue, QnanException); 1225 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }}, 1226 UnorderedFalse, QnanException); 1227 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }}, 1228 UnorderedTrue, QnanException); 1229 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }}, 1230 UnorderedFalse, QnanException); 1231 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }}, 1232 UnorderedTrue, QnanException); 1233 } 1234 } 1235 default: CP1Unimpl::unknown(); 1236 } 1237 0x2: CP1Unimpl::unknown(); 1238 0x3: CP1Unimpl::unknown(); 1239 0x7: CP1Unimpl::unknown(); 1240 1241 //Table A-16 MIPS32 COP1 Encoding of Function 1242 //Field When rs=W 1243 0x4: decode FUNCTION { 1244 format FloatConvertOp { 1245 0x20: cvt_s_w({{ val = Fs_uw; }}, ToSingle); 1246 0x21: cvt_d_w({{ val = Fs_uw; }}, ToDouble); 1247 0x26: CP1Unimpl::cvt_ps_w(); 1248 } 1249 default: CP1Unimpl::unknown(); 1250 } 1251 1252 //Table A-16 MIPS32 COP1 Encoding of Function Field 1253 //When rs=L1 1254 //Note: "1. Format type L is legal only if 64-bit 1255 //floating point operations are enabled." 1256 0x5: decode FUNCTION_HI { 1257 format FloatConvertOp { 1258 0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle); 1259 0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble); 1260 0x26: CP1Unimpl::cvt_ps_l(); 1261 } 1262 default: CP1Unimpl::unknown(); 1263 } 1264 1265 //Table A-17 MIPS64 COP1 Encoding of Function Field 1266 //When rs=PS1 1267 //Note: "1. Format type PS is legal only if 64-bit 1268 //floating point operations are enabled. " 1269 0x6: decode FUNCTION_HI { 1270 0x0: decode FUNCTION_LO { 1271 format Float64Op { 1272 0x0: add_ps({{ 1273 Fd1_sf = Fs1_sf + Ft2_sf; 1274 Fd2_sf = Fs2_sf + Ft2_sf; 1275 }}); 1276 0x1: sub_ps({{ 1277 Fd1_sf = Fs1_sf - Ft2_sf; 1278 Fd2_sf = Fs2_sf - Ft2_sf; 1279 }}); 1280 0x2: mul_ps({{ 1281 Fd1_sf = Fs1_sf * Ft2_sf; 1282 Fd2_sf = Fs2_sf * Ft2_sf; 1283 }}); 1284 0x5: abs_ps({{ 1285 Fd1_sf = fabs(Fs1_sf); 1286 Fd2_sf = fabs(Fs2_sf); 1287 }}); 1288 0x6: mov_ps({{ 1289 Fd1_sf = Fs1_sf; 1290 Fd2_sf = Fs2_sf; 1291 }}); 1292 0x7: neg_ps({{ 1293 Fd1_sf = -(Fs1_sf); 1294 Fd2_sf = -(Fs2_sf); 1295 }}); 1296 default: CP1Unimpl::unknown(); 1297 } 1298 } 1299 0x1: CP1Unimpl::unknown(); 1300 0x2: decode FUNCTION_LO { 1301 0x1: decode MOVCF { 1302 format Float64Op { 1303 0x0: movf_ps({{ 1304 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1305 Fs1 : Fd1; 1306 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1307 Fs2 : Fd2; 1308 }}); 1309 0x1: movt_ps({{ 1310 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1311 Fs1 : Fd1; 1312 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1313 Fs2 : Fd2; 1314 }}); 1315 } 1316 } 1317 1318 format Float64Op { 1319 0x2: movz_ps({{ 1320 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1321 Fs1 : Fd1; 1322 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1323 Fs2 : Fd2; 1324 }}); 1325 0x3: movn_ps({{ 1326 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1327 Fs1 : Fd1; 1328 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1329 Fs2 : Fd2; 1330 }}); 1331 } 1332 default: CP1Unimpl::unknown(); 1333 } 1334 0x3: CP1Unimpl::unknown(); 1335 0x4: decode FUNCTION_LO { 1336 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }}); 1337 default: CP1Unimpl::unknown(); 1338 } 1339 1340 0x5: decode FUNCTION_LO { 1341 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }}); 1342 format Float64Op { 1343 0x4: pll({{ 1344 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw; 1345 }}); 1346 0x5: plu({{ 1347 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw; 1348 }}); 1349 0x6: pul({{ 1350 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw; 1351 }}); 1352 0x7: puu({{ 1353 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw; 1354 }}); 1355 } 1356 default: CP1Unimpl::unknown(); 1357 } 1358 1359 0x6: decode FUNCTION_LO { 1360 format FloatPSCompareOp { 1361 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1362 UnorderedFalse); 1363 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1364 UnorderedTrue); 1365 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1366 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1367 UnorderedFalse); 1368 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1369 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1370 UnorderedTrue); 1371 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1372 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1373 UnorderedFalse); 1374 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }}, 1375 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1376 UnorderedTrue); 1377 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }}, 1378 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1379 UnorderedFalse); 1380 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1381 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1382 UnorderedTrue); 1383 } 1384 } 1385 1386 0x7: decode FUNCTION_LO { 1387 format FloatPSCompareOp { 1388 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1389 UnorderedFalse, QnanException); 1390 0x1: c_ngle_ps({{ cond1 = 0; }}, 1391 {{ cond2 = 0; }}, 1392 UnorderedTrue, QnanException); 1393 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1394 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1395 UnorderedFalse, QnanException); 1396 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1397 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1398 UnorderedTrue, QnanException); 1399 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1400 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1401 UnorderedFalse, QnanException); 1402 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1403 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1404 UnorderedTrue, QnanException); 1405 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1406 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1407 UnorderedFalse, QnanException); 1408 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1409 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1410 UnorderedTrue, QnanException); 1411 } 1412 } 1413 } 1414 } 1415 default: CP1Unimpl::unknown(); 1416 } 1417 } 1418 1419 //Table A-19 MIPS32 COP2 Encoding of rs Field 1420 0x2: decode RS_MSB { 1421 format CP2Unimpl { 1422 0x0: decode RS_HI { 1423 0x0: decode RS_LO { 1424 0x0: mfc2(); 1425 0x2: cfc2(); 1426 0x3: mfhc2(); 1427 0x4: mtc2(); 1428 0x6: ctc2(); 1429 0x7: mftc2(); 1430 default: unknown(); 1431 } 1432 1433 0x1: decode ND { 1434 0x0: decode TF { 1435 0x0: bc2f(); 1436 0x1: bc2t(); 1437 default: unknown(); 1438 } 1439 1440 0x1: decode TF { 1441 0x0: bc2fl(); 1442 0x1: bc2tl(); 1443 default: unknown(); 1444 } 1445 default: unknown(); 1446 1447 } 1448 default: unknown(); 1449 } 1450 default: unknown(); 1451 } 1452 } 1453 1454 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1455 //Note: "COP1X instructions are legal only if 64-bit floating point 1456 //operations are enabled." 1457 0x3: decode FUNCTION_HI { 1458 0x0: decode FUNCTION_LO { 1459 format LoadIndexedMemory { 1460 0x0: lwxc1({{ Fd_uw = Mem_uw; }}); 1461 0x1: ldxc1({{ Fd_ud = Mem_ud; }}); 1462 0x5: luxc1({{ Fd_ud = Mem_ud; }}, 1463 {{ EA = (Rs + Rt) & ~7; }}); 1464 } 1465 } 1466 1467 0x1: decode FUNCTION_LO { 1468 format StoreIndexedMemory { 1469 0x0: swxc1({{ Mem_uw = Fs_uw; }}); 1470 0x1: sdxc1({{ Mem_ud = Fs_ud; }}); 1471 0x5: suxc1({{ Mem_ud = Fs_ud; }}, 1472 {{ EA = (Rs + Rt) & ~7; }}); 1473 } 1474 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1475 } 1476 1477 0x3: decode FUNCTION_LO { 1478 0x6: Float64Op::alnv_ps({{ 1479 if (Rs<2:0> == 0) { 1480 Fd_ud = Fs_ud; 1481 } else if (Rs<2:0> == 4) { 1482 if (GuestByteOrder == BigEndianByteOrder) 1483 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; 1484 else 1485 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; 1486 } else { 1487 Fd_ud = Fd_ud; 1488 } 1489 }}); 1490 } 1491 1492 format FloatAccOp { 1493 0x4: decode FUNCTION_LO { 1494 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }}); 1495 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }}); 1496 0x6: madd_ps({{ 1497 Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df; 1498 Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df; 1499 }}); 1500 } 1501 1502 0x5: decode FUNCTION_LO { 1503 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }}); 1504 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }}); 1505 0x6: msub_ps({{ 1506 Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df; 1507 Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df; 1508 }}); 1509 } 1510 1511 0x6: decode FUNCTION_LO { 1512 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }}); 1513 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }}); 1514 0x6: nmadd_ps({{ 1515 Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df); 1516 Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df); 1517 }}); 1518 } 1519 1520 0x7: decode FUNCTION_LO { 1521 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }}); 1522 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }}); 1523 0x6: nmsub_ps({{ 1524 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df); 1525 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df); 1526 }}); 1527 } 1528 } 1529 } 1530 1531 format Branch { 1532 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely); 1533 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely); 1534 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely); 1535 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely); 1536 } 1537 } 1538 1539 0x3: decode OPCODE_LO { 1540 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1541 0x4: decode FUNCTION_HI { 1542 0x0: decode FUNCTION_LO { 1543 0x2: IntOp::mul({{ 1544 int64_t temp1 = Rs_sd * Rt_sd; 1545 Rd_sw = temp1<31:0>; 1546 }}, IntMultOp); 1547 1548 format HiLoRdSelValOp { 1549 0x0: madd({{ 1550 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1551 (Rs_sd * Rt_sd); 1552 }}, IntMultOp); 1553 0x1: maddu({{ 1554 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1555 (Rs_ud * Rt_ud); 1556 }}, IntMultOp); 1557 0x4: msub({{ 1558 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1559 (Rs_sd * Rt_sd); 1560 }}, IntMultOp); 1561 0x5: msubu({{ 1562 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1563 (Rs_ud * Rt_ud); 1564 }}, IntMultOp); 1565 } 1566 } 1567 1568 0x4: decode FUNCTION_LO { 1569 format BasicOp { 1570 0x0: clz({{ 1571 int cnt = 32; 1572 for (int idx = 31; idx >= 0; idx--) { 1573 if (Rs<idx:idx> == 1) { 1574 cnt = 31 - idx; 1575 break; 1576 } 1577 } 1578 Rd_uw = cnt; 1579 }}); 1580 0x1: clo({{ 1581 int cnt = 32; 1582 for (int idx = 31; idx >= 0; idx--) { 1583 if (Rs<idx:idx> == 0) { 1584 cnt = 31 - idx; 1585 break; 1586 } 1587 } 1588 Rd_uw = cnt; 1589 }}); 1590 } 1591 } 1592 1593 0x7: decode FUNCTION_LO { 1594 0x7: FailUnimpl::sdbbp(); 1595 } 1596 } 1597 1598 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1599 //of the Architecture 1600 0x7: decode FUNCTION_HI { 1601 0x0: decode FUNCTION_LO { 1602 format BasicOp { 1603 0x0: ext({{ Rt_uw = bits(Rs_uw, MSB+LSB, LSB); }}); 1604 0x4: ins({{ 1605 Rt_uw = bits(Rt_uw, 31, MSB+1) << (MSB+1) | 1606 bits(Rs_uw, MSB-LSB, 0) << LSB | 1607 bits(Rt_uw, LSB-1, 0); 1608 }}); 1609 } 1610 } 1611 1612 0x1: decode FUNCTION_LO { 1613 format MT_Control { 1614 0x0: fork({{ 1615 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1616 }}, UserMode); 1617 0x1: yield({{ 1618 Rd_sw = yieldThread(xc->tcBase(), fault, Rs_sw, 1619 YQMask); 1620 }}, UserMode); 1621 } 1622 1623 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1624 0x2: decode OP_HI { 1625 0x0: decode OP_LO { 1626 format LoadIndexedMemory { 1627 0x0: lwx({{ Rd_sw = Mem_sw; }}); 1628 0x4: lhx({{ Rd_sw = Mem_sh; }}); 1629 0x6: lbux({{ Rd_uw = Mem_ub; }}); 1630 } 1631 } 1632 } 1633 0x4: DspIntOp::insv({{ 1634 int pos = dspctl<5:0>; 1635 int size = dspctl<12:7> - 1; 1636 Rt_uw = insertBits(Rt_uw, pos+size, 1637 pos, Rs_uw<size:0>); 1638 }}); 1639 } 1640 1641 0x2: decode FUNCTION_LO { 1642 1643 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1644 //(DSP ASE MANUAL) 1645 0x0: decode OP_HI { 1646 0x0: decode OP_LO { 1647 format DspIntOp { 1648 0x0: addu_qb({{ 1649 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1650 NOSATURATE, UNSIGNED, &dspctl); 1651 }}); 1652 0x1: subu_qb({{ 1653 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1654 NOSATURATE, UNSIGNED, &dspctl); 1655 }}); 1656 0x4: addu_s_qb({{ 1657 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1658 SATURATE, UNSIGNED, &dspctl); 1659 }}); 1660 0x5: subu_s_qb({{ 1661 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1662 SATURATE, UNSIGNED, &dspctl); 1663 }}); 1664 0x6: muleu_s_ph_qbl({{ 1665 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1666 MODE_L, &dspctl); 1667 }}, IntMultOp); 1668 0x7: muleu_s_ph_qbr({{ 1669 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1670 MODE_R, &dspctl); 1671 }}, IntMultOp); 1672 } 1673 } 1674 0x1: decode OP_LO { 1675 format DspIntOp { 1676 0x0: addu_ph({{ 1677 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1678 NOSATURATE, UNSIGNED, &dspctl); 1679 }}); 1680 0x1: subu_ph({{ 1681 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1682 NOSATURATE, UNSIGNED, &dspctl); 1683 }}); 1684 0x2: addq_ph({{ 1685 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1686 NOSATURATE, SIGNED, &dspctl); 1687 }}); 1688 0x3: subq_ph({{ 1689 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1690 NOSATURATE, SIGNED, &dspctl); 1691 }}); 1692 0x4: addu_s_ph({{ 1693 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1694 SATURATE, UNSIGNED, &dspctl); 1695 }}); 1696 0x5: subu_s_ph({{ 1697 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1698 SATURATE, UNSIGNED, &dspctl); 1699 }}); 1700 0x6: addq_s_ph({{ 1701 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1702 SATURATE, SIGNED, &dspctl); 1703 }}); 1704 0x7: subq_s_ph({{ 1705 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1706 SATURATE, SIGNED, &dspctl); 1707 }}); 1708 } 1709 } 1710 0x2: decode OP_LO { 1711 format DspIntOp { 1712 0x0: addsc({{ 1713 int64_t dresult; 1714 dresult = Rs_ud + Rt_ud; 1715 Rd_sw = dresult<31:0>; 1716 dspctl = insertBits(dspctl, 13, 13, 1717 dresult<32:32>); 1718 }}); 1719 0x1: addwc({{ 1720 int64_t dresult; 1721 dresult = Rs_sd + Rt_sd + dspctl<13:13>; 1722 Rd_sw = dresult<31:0>; 1723 if (dresult<32:32> != dresult<31:31>) 1724 dspctl = insertBits(dspctl, 20, 20, 1); 1725 }}); 1726 0x2: modsub({{ 1727 Rd_sw = (Rs_sw == 0) ? Rt_sw<23:8> : 1728 Rs_sw - Rt_sw<7:0>; 1729 }}); 1730 0x4: raddu_w_qb({{ 1731 Rd_uw = Rs_uw<31:24> + Rs_uw<23:16> + 1732 Rs_uw<15:8> + Rs_uw<7:0>; 1733 }}); 1734 0x6: addq_s_w({{ 1735 Rd_sw = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W, 1736 SATURATE, SIGNED, &dspctl); 1737 }}); 1738 0x7: subq_s_w({{ 1739 Rd_sw = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W, 1740 SATURATE, SIGNED, &dspctl); 1741 }}); 1742 } 1743 } 1744 0x3: decode OP_LO { 1745 format DspIntOp { 1746 0x4: muleq_s_w_phl({{ 1747 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1748 MODE_L, &dspctl); 1749 }}, IntMultOp); 1750 0x5: muleq_s_w_phr({{ 1751 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1752 MODE_R, &dspctl); 1753 }}, IntMultOp); 1754 0x6: mulq_s_ph({{ 1755 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1756 SATURATE, NOROUND, &dspctl); 1757 }}, IntMultOp); 1758 0x7: mulq_rs_ph({{ 1759 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1760 SATURATE, ROUND, &dspctl); 1761 }}, IntMultOp); 1762 } 1763 } 1764 } 1765 1766 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1767 //(DSP ASE MANUAL) 1768 0x1: decode OP_HI { 1769 0x0: decode OP_LO { 1770 format DspIntOp { 1771 0x0: cmpu_eq_qb({{ 1772 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1773 UNSIGNED, CMP_EQ, &dspctl); 1774 }}); 1775 0x1: cmpu_lt_qb({{ 1776 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1777 UNSIGNED, CMP_LT, &dspctl); 1778 }}); 1779 0x2: cmpu_le_qb({{ 1780 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1781 UNSIGNED, CMP_LE, &dspctl); 1782 }}); 1783 0x3: pick_qb({{ 1784 Rd_uw = dspPick(Rs_uw, Rt_uw, 1785 SIMD_FMT_QB, &dspctl); 1786 }}); 1787 0x4: cmpgu_eq_qb({{ 1788 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1789 UNSIGNED, CMP_EQ ); 1790 }}); 1791 0x5: cmpgu_lt_qb({{ 1792 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1793 UNSIGNED, CMP_LT); 1794 }}); 1795 0x6: cmpgu_le_qb({{ 1796 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1797 UNSIGNED, CMP_LE); 1798 }}); 1799 } 1800 } 1801 0x1: decode OP_LO { 1802 format DspIntOp { 1803 0x0: cmp_eq_ph({{ 1804 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1805 SIGNED, CMP_EQ, &dspctl); 1806 }}); 1807 0x1: cmp_lt_ph({{ 1808 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1809 SIGNED, CMP_LT, &dspctl); 1810 }}); 1811 0x2: cmp_le_ph({{ 1812 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1813 SIGNED, CMP_LE, &dspctl); 1814 }}); 1815 0x3: pick_ph({{ 1816 Rd_uw = dspPick(Rs_uw, Rt_uw, 1817 SIMD_FMT_PH, &dspctl); 1818 }}); 1819 0x4: precrq_qb_ph({{ 1820 Rd_uw = Rs_uw<31:24> << 24 | 1821 Rs_uw<15:8> << 16 | 1822 Rt_uw<31:24> << 8 | 1823 Rt_uw<15:8>; 1824 }}); 1825 0x5: precr_qb_ph({{ 1826 Rd_uw = Rs_uw<23:16> << 24 | 1827 Rs_uw<7:0> << 16 | 1828 Rt_uw<23:16> << 8 | 1829 Rt_uw<7:0>; 1830 }}); 1831 0x6: packrl_ph({{ 1832 Rd_uw = dspPack(Rs_uw, Rt_uw, SIMD_FMT_PH); 1833 }}); 1834 0x7: precrqu_s_qb_ph({{ 1835 Rd_uw = dspPrecrqu(Rs_uw, Rt_uw, &dspctl); 1836 }}); 1837 } 1838 } 1839 0x2: decode OP_LO { 1840 format DspIntOp { 1841 0x4: precrq_ph_w({{ 1842 Rd_uw = Rs_uw<31:16> << 16 | Rt_uw<31:16>; 1843 }}); 1844 0x5: precrq_rs_ph_w({{ 1845 Rd_uw = dspPrecrq(Rs_uw, Rt_uw, 1846 SIMD_FMT_W, &dspctl); 1847 }}); 1848 } 1849 } 1850 0x3: decode OP_LO { 1851 format DspIntOp { 1852 0x0: cmpgdu_eq_qb({{ 1853 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1854 UNSIGNED, CMP_EQ, &dspctl); 1855 }}); 1856 0x1: cmpgdu_lt_qb({{ 1857 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1858 UNSIGNED, CMP_LT, &dspctl); 1859 }}); 1860 0x2: cmpgdu_le_qb({{ 1861 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1862 UNSIGNED, CMP_LE, &dspctl); 1863 }}); 1864 0x6: precr_sra_ph_w({{ 1865 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1866 SIMD_FMT_W, NOROUND); 1867 }}); 1868 0x7: precr_sra_r_ph_w({{ 1869 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1870 SIMD_FMT_W, ROUND); 1871 }}); 1872 } 1873 } 1874 } 1875 1876 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1877 //(DSP ASE MANUAL) 1878 0x2: decode OP_HI { 1879 0x0: decode OP_LO { 1880 format DspIntOp { 1881 0x1: absq_s_qb({{ 1882 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl); 1883 }}); 1884 0x2: repl_qb({{ 1885 Rd_uw = RS_RT<7:0> << 24 | 1886 RS_RT<7:0> << 16 | 1887 RS_RT<7:0> << 8 | 1888 RS_RT<7:0>; 1889 }}); 1890 0x3: replv_qb({{ 1891 Rd_sw = Rt_uw<7:0> << 24 | 1892 Rt_uw<7:0> << 16 | 1893 Rt_uw<7:0> << 8 | 1894 Rt_uw<7:0>; 1895 }}); 1896 0x4: precequ_ph_qbl({{ 1897 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1898 SIMD_FMT_PH, SIGNED, MODE_L); 1899 }}); 1900 0x5: precequ_ph_qbr({{ 1901 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1902 SIMD_FMT_PH, SIGNED, MODE_R); 1903 }}); 1904 0x6: precequ_ph_qbla({{ 1905 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1906 SIMD_FMT_PH, SIGNED, MODE_LA); 1907 }}); 1908 0x7: precequ_ph_qbra({{ 1909 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1910 SIMD_FMT_PH, SIGNED, MODE_RA); 1911 }}); 1912 } 1913 } 1914 0x1: decode OP_LO { 1915 format DspIntOp { 1916 0x1: absq_s_ph({{ 1917 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl); 1918 }}); 1919 0x2: repl_ph({{ 1920 Rd_uw = (sext<10>(RS_RT))<15:0> << 16 | 1921 (sext<10>(RS_RT))<15:0>; 1922 }}); 1923 0x3: replv_ph({{ 1924 Rd_uw = Rt_uw<15:0> << 16 | 1925 Rt_uw<15:0>; 1926 }}); 1927 0x4: preceq_w_phl({{ 1928 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1929 SIMD_FMT_W, SIGNED, MODE_L); 1930 }}); 1931 0x5: preceq_w_phr({{ 1932 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1933 SIMD_FMT_W, SIGNED, MODE_R); 1934 }}); 1935 } 1936 } 1937 0x2: decode OP_LO { 1938 format DspIntOp { 1939 0x1: absq_s_w({{ 1940 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl); 1941 }}); 1942 } 1943 } 1944 0x3: decode OP_LO { 1945 0x3: IntOp::bitrev({{ 1946 Rd_uw = bitrev( Rt_uw<15:0> ); 1947 }}); 1948 format DspIntOp { 1949 0x4: preceu_ph_qbl({{ 1950 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1951 UNSIGNED, SIMD_FMT_PH, 1952 UNSIGNED, MODE_L); 1953 }}); 1954 0x5: preceu_ph_qbr({{ 1955 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1956 UNSIGNED, SIMD_FMT_PH, 1957 UNSIGNED, MODE_R ); 1958 }}); 1959 0x6: preceu_ph_qbla({{ 1960 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1961 UNSIGNED, SIMD_FMT_PH, 1962 UNSIGNED, MODE_LA ); 1963 }}); 1964 0x7: preceu_ph_qbra({{ 1965 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1966 UNSIGNED, SIMD_FMT_PH, 1967 UNSIGNED, MODE_RA); 1968 }}); 1969 } 1970 } 1971 } 1972 1973 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 1974 //(DSP ASE MANUAL) 1975 0x3: decode OP_HI { 1976 0x0: decode OP_LO { 1977 format DspIntOp { 1978 0x0: shll_qb({{ 1979 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_QB, 1980 NOSATURATE, UNSIGNED, &dspctl); 1981 }}); 1982 0x1: shrl_qb({{ 1983 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_QB, 1984 UNSIGNED); 1985 }}); 1986 0x2: shllv_qb({{ 1987 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB, 1988 NOSATURATE, UNSIGNED, &dspctl); 1989 }}); 1990 0x3: shrlv_qb({{ 1991 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB, 1992 UNSIGNED); 1993 }}); 1994 0x4: shra_qb({{ 1995 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 1996 NOROUND, SIGNED, &dspctl); 1997 }}); 1998 0x5: shra_r_qb({{ 1999 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2000 ROUND, SIGNED, &dspctl); 2001 }}); 2002 0x6: shrav_qb({{ 2003 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2004 NOROUND, SIGNED, &dspctl); 2005 }}); 2006 0x7: shrav_r_qb({{ 2007 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2008 ROUND, SIGNED, &dspctl); 2009 }}); 2010 } 2011 } 2012 0x1: decode OP_LO { 2013 format DspIntOp { 2014 0x0: shll_ph({{ 2015 Rd_uw = dspShll(Rt_uw, RS, SIMD_FMT_PH, 2016 NOSATURATE, SIGNED, &dspctl); 2017 }}); 2018 0x1: shra_ph({{ 2019 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2020 NOROUND, SIGNED, &dspctl); 2021 }}); 2022 0x2: shllv_ph({{ 2023 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2024 NOSATURATE, SIGNED, &dspctl); 2025 }}); 2026 0x3: shrav_ph({{ 2027 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2028 NOROUND, SIGNED, &dspctl); 2029 }}); 2030 0x4: shll_s_ph({{ 2031 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_PH, 2032 SATURATE, SIGNED, &dspctl); 2033 }}); 2034 0x5: shra_r_ph({{ 2035 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2036 ROUND, SIGNED, &dspctl); 2037 }}); 2038 0x6: shllv_s_ph({{ 2039 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2040 SATURATE, SIGNED, &dspctl); 2041 }}); 2042 0x7: shrav_r_ph({{ 2043 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2044 ROUND, SIGNED, &dspctl); 2045 }}); 2046 } 2047 } 2048 0x2: decode OP_LO { 2049 format DspIntOp { 2050 0x4: shll_s_w({{ 2051 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_W, 2052 SATURATE, SIGNED, &dspctl); 2053 }}); 2054 0x5: shra_r_w({{ 2055 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_W, 2056 ROUND, SIGNED, &dspctl); 2057 }}); 2058 0x6: shllv_s_w({{ 2059 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W, 2060 SATURATE, SIGNED, &dspctl); 2061 }}); 2062 0x7: shrav_r_w({{ 2063 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W, 2064 ROUND, SIGNED, &dspctl); 2065 }}); 2066 } 2067 } 2068 0x3: decode OP_LO { 2069 format DspIntOp { 2070 0x1: shrl_ph({{ 2071 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_PH, 2072 UNSIGNED); 2073 }}); 2074 0x3: shrlv_ph({{ 2075 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH, 2076 UNSIGNED); 2077 }}); 2078 } 2079 } 2080 } 2081 } 2082 2083 0x3: decode FUNCTION_LO { 2084 2085 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2086 //(DSP ASE Rev2 Manual) 2087 0x0: decode OP_HI { 2088 0x0: decode OP_LO { 2089 format DspIntOp { 2090 0x0: adduh_qb({{ 2091 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2092 NOROUND, UNSIGNED); 2093 }}); 2094 0x1: subuh_qb({{ 2095 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2096 NOROUND, UNSIGNED); 2097 }}); 2098 0x2: adduh_r_qb({{ 2099 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2100 ROUND, UNSIGNED); 2101 }}); 2102 0x3: subuh_r_qb({{ 2103 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2104 ROUND, UNSIGNED); 2105 }}); 2106 } 2107 } 2108 0x1: decode OP_LO { 2109 format DspIntOp { 2110 0x0: addqh_ph({{ 2111 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2112 NOROUND, SIGNED); 2113 }}); 2114 0x1: subqh_ph({{ 2115 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2116 NOROUND, SIGNED); 2117 }}); 2118 0x2: addqh_r_ph({{ 2119 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2120 ROUND, SIGNED); 2121 }}); 2122 0x3: subqh_r_ph({{ 2123 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2124 ROUND, SIGNED); 2125 }}); 2126 0x4: mul_ph({{ 2127 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2128 NOSATURATE, &dspctl); 2129 }}, IntMultOp); 2130 0x6: mul_s_ph({{ 2131 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2132 SATURATE, &dspctl); 2133 }}, IntMultOp); 2134 } 2135 } 2136 0x2: decode OP_LO { 2137 format DspIntOp { 2138 0x0: addqh_w({{ 2139 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2140 NOROUND, SIGNED); 2141 }}); 2142 0x1: subqh_w({{ 2143 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2144 NOROUND, SIGNED); 2145 }}); 2146 0x2: addqh_r_w({{ 2147 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2148 ROUND, SIGNED); 2149 }}); 2150 0x3: subqh_r_w({{ 2151 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2152 ROUND, SIGNED); 2153 }}); 2154 0x6: mulq_s_w({{ 2155 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2156 SATURATE, NOROUND, &dspctl); 2157 }}, IntMultOp); 2158 0x7: mulq_rs_w({{ 2159 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2160 SATURATE, ROUND, &dspctl); 2161 }}, IntMultOp); 2162 } 2163 } 2164 } 2165 } 2166 2167 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2168 0x4: decode SA { 2169 format BasicOp { 2170 0x02: wsbh({{ 2171 Rd_uw = Rt_uw<23:16> << 24 | 2172 Rt_uw<31:24> << 16 | 2173 Rt_uw<7:0> << 8 | 2174 Rt_uw<15:8>; 2175 }}); 2176 0x10: seb({{ Rd_sw = Rt_sb; }}); 2177 0x18: seh({{ Rd_sw = Rt_sh; }}); 2178 } 2179 } 2180 2181 0x6: decode FUNCTION_LO { 2182 2183 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2184 //(DSP ASE MANUAL) 2185 0x0: decode OP_HI { 2186 0x0: decode OP_LO { 2187 format DspHiLoOp { 2188 0x0: dpa_w_ph({{ 2189 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2190 SIMD_FMT_PH, SIGNED, MODE_L); 2191 }}, IntMultOp); 2192 0x1: dps_w_ph({{ 2193 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2194 SIMD_FMT_PH, SIGNED, MODE_L); 2195 }}, IntMultOp); 2196 0x2: mulsa_w_ph({{ 2197 dspac = dspMulsa(dspac, Rs_sw, Rt_sw, 2198 ACDST, SIMD_FMT_PH ); 2199 }}, IntMultOp); 2200 0x3: dpau_h_qbl({{ 2201 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2202 SIMD_FMT_QB, UNSIGNED, MODE_L); 2203 }}, IntMultOp); 2204 0x4: dpaq_s_w_ph({{ 2205 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2206 ACDST, SIMD_FMT_PH, 2207 SIMD_FMT_W, NOSATURATE, 2208 MODE_L, &dspctl); 2209 }}, IntMultOp); 2210 0x5: dpsq_s_w_ph({{ 2211 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2212 ACDST, SIMD_FMT_PH, 2213 SIMD_FMT_W, NOSATURATE, 2214 MODE_L, &dspctl); 2215 }}, IntMultOp); 2216 0x6: mulsaq_s_w_ph({{ 2217 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw, 2218 ACDST, SIMD_FMT_PH, 2219 &dspctl); 2220 }}, IntMultOp); 2221 0x7: dpau_h_qbr({{ 2222 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2223 SIMD_FMT_QB, UNSIGNED, MODE_R); 2224 }}, IntMultOp); 2225 } 2226 } 2227 0x1: decode OP_LO { 2228 format DspHiLoOp { 2229 0x0: dpax_w_ph({{ 2230 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2231 SIMD_FMT_PH, SIGNED, MODE_X); 2232 }}, IntMultOp); 2233 0x1: dpsx_w_ph({{ 2234 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2235 SIMD_FMT_PH, SIGNED, MODE_X); 2236 }}, IntMultOp); 2237 0x3: dpsu_h_qbl({{ 2238 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2239 SIMD_FMT_QB, UNSIGNED, MODE_L); 2240 }}, IntMultOp); 2241 0x4: dpaq_sa_l_w({{ 2242 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2243 ACDST, SIMD_FMT_W, 2244 SIMD_FMT_L, SATURATE, 2245 MODE_L, &dspctl); 2246 }}, IntMultOp); 2247 0x5: dpsq_sa_l_w({{ 2248 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2249 ACDST, SIMD_FMT_W, 2250 SIMD_FMT_L, SATURATE, 2251 MODE_L, &dspctl); 2252 }}, IntMultOp); 2253 0x7: dpsu_h_qbr({{ 2254 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2255 SIMD_FMT_QB, UNSIGNED, MODE_R); 2256 }}, IntMultOp); 2257 } 2258 } 2259 0x2: decode OP_LO { 2260 format DspHiLoOp { 2261 0x0: maq_sa_w_phl({{ 2262 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2263 ACDST, SIMD_FMT_PH, 2264 MODE_L, SATURATE, &dspctl); 2265 }}, IntMultOp); 2266 0x2: maq_sa_w_phr({{ 2267 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2268 ACDST, SIMD_FMT_PH, 2269 MODE_R, SATURATE, &dspctl); 2270 }}, IntMultOp); 2271 0x4: maq_s_w_phl({{ 2272 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2273 ACDST, SIMD_FMT_PH, 2274 MODE_L, NOSATURATE, &dspctl); 2275 }}, IntMultOp); 2276 0x6: maq_s_w_phr({{ 2277 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2278 ACDST, SIMD_FMT_PH, 2279 MODE_R, NOSATURATE, &dspctl); 2280 }}, IntMultOp); 2281 } 2282 } 2283 0x3: decode OP_LO { 2284 format DspHiLoOp { 2285 0x0: dpaqx_s_w_ph({{ 2286 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2287 ACDST, SIMD_FMT_PH, 2288 SIMD_FMT_W, NOSATURATE, 2289 MODE_X, &dspctl); 2290 }}, IntMultOp); 2291 0x1: dpsqx_s_w_ph({{ 2292 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2293 ACDST, SIMD_FMT_PH, 2294 SIMD_FMT_W, NOSATURATE, 2295 MODE_X, &dspctl); 2296 }}, IntMultOp); 2297 0x2: dpaqx_sa_w_ph({{ 2298 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2299 ACDST, SIMD_FMT_PH, 2300 SIMD_FMT_W, SATURATE, 2301 MODE_X, &dspctl); 2302 }}, IntMultOp); 2303 0x3: dpsqx_sa_w_ph({{ 2304 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2305 ACDST, SIMD_FMT_PH, 2306 SIMD_FMT_W, SATURATE, 2307 MODE_X, &dspctl); 2308 }}, IntMultOp); 2309 } 2310 } 2311 } 2312 2313 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2314 0x1: decode OP_HI { 2315 0x0: decode OP_LO { 2316 format IntOp { 2317 0x0: append({{ 2318 Rt_uw = (Rt_uw << RD) | bits(Rs_uw, RD - 1, 0); 2319 }}); 2320 0x1: prepend({{ 2321 Rt_uw = (Rt_uw >> RD) | 2322 (bits(Rs_uw, RD - 1, 0) << (32 - RD)); 2323 }}); 2324 } 2325 } 2326 0x2: decode OP_LO { 2327 format IntOp { 2328 0x0: balign({{ 2329 Rt_uw = (Rt_uw << (8 * BP)) | 2330 (Rs_uw >> (8 * (4 - BP))); 2331 }}); 2332 } 2333 } 2334 } 2335 2336 } 2337 0x7: decode FUNCTION_LO { 2338 2339 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2340 //(DSP ASE MANUAL) 2341 0x0: decode OP_HI { 2342 0x0: decode OP_LO { 2343 format DspHiLoOp { 2344 0x0: extr_w({{ 2345 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2346 NOROUND, NOSATURATE, &dspctl); 2347 }}); 2348 0x1: extrv_w({{ 2349 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2350 NOROUND, NOSATURATE, &dspctl); 2351 }}); 2352 0x2: extp({{ 2353 Rt_uw = dspExtp(dspac, RS, &dspctl); 2354 }}); 2355 0x3: extpv({{ 2356 Rt_uw = dspExtp(dspac, Rs_uw, &dspctl); 2357 }}); 2358 0x4: extr_r_w({{ 2359 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2360 ROUND, NOSATURATE, &dspctl); 2361 }}); 2362 0x5: extrv_r_w({{ 2363 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2364 ROUND, NOSATURATE, &dspctl); 2365 }}); 2366 0x6: extr_rs_w({{ 2367 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2368 ROUND, SATURATE, &dspctl); 2369 }}); 2370 0x7: extrv_rs_w({{ 2371 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2372 ROUND, SATURATE, &dspctl); 2373 }}); 2374 } 2375 } 2376 0x1: decode OP_LO { 2377 format DspHiLoOp { 2378 0x2: extpdp({{ 2379 Rt_uw = dspExtpd(dspac, RS, &dspctl); 2380 }}); 2381 0x3: extpdpv({{ 2382 Rt_uw = dspExtpd(dspac, Rs_uw, &dspctl); 2383 }}); 2384 0x6: extr_s_h({{ 2385 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2386 NOROUND, SATURATE, &dspctl); 2387 }}); 2388 0x7: extrv_s_h({{ 2389 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, Rs_uw, 2390 NOROUND, SATURATE, &dspctl); 2391 }}); 2392 } 2393 } 2394 0x2: decode OP_LO { 2395 format DspIntOp { 2396 0x2: rddsp({{ 2397 Rd_uw = readDSPControl(&dspctl, RDDSPMASK); 2398 }}); 2399 0x3: wrdsp({{ 2400 writeDSPControl(&dspctl, Rs_uw, WRDSPMASK); 2401 }}); 2402 } 2403 } 2404 0x3: decode OP_LO { 2405 format DspHiLoOp { 2406 0x2: shilo({{ 2407 if (sext<6>(HILOSA) < 0) { 2408 dspac = (uint64_t)dspac << 2409 -sext<6>(HILOSA); 2410 } else { 2411 dspac = (uint64_t)dspac >> 2412 sext<6>(HILOSA); 2413 } 2414 }}); 2415 0x3: shilov({{ 2416 if (sext<6>(Rs_sw<5:0>) < 0) { 2417 dspac = (uint64_t)dspac << 2418 -sext<6>(Rs_sw<5:0>); 2419 } else { 2420 dspac = (uint64_t)dspac >> 2421 sext<6>(Rs_sw<5:0>); 2422 } 2423 }}); 2424 0x7: mthlip({{ 2425 dspac = dspac << 32; 2426 dspac |= Rs_uw; 2427 dspctl = insertBits(dspctl, 5, 0, 2428 dspctl<5:0> + 32); 2429 }}); 2430 } 2431 } 2432 } 2433 0x3: decode OP default FailUnimpl::rdhwr() { 2434 0x0: decode FullSystem { 2435 0: decode RD { 2436 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2437 } 2438 } 2439 } 2440 } 2441 } 2442 } 2443 2444 0x4: decode OPCODE_LO { 2445 format LoadMemory { 2446 0x0: lb({{ Rt_sw = Mem_sb; }}); 2447 0x1: lh({{ Rt_sw = Mem_sh; }}); 2448 0x3: lw({{ Rt_sw = Mem_sw; }}); 2449 0x4: lbu({{ Rt_uw = Mem_ub;}}); 2450 0x5: lhu({{ Rt_uw = Mem_uh; }}); 2451 } 2452 2453 format LoadUnalignedMemory { 2454 0x2: lwl({{ 2455 uint32_t mem_shift = 24 - (8 * byte_offset); 2456 Rt_uw = mem_word << mem_shift | (Rt_uw & mask(mem_shift)); 2457 }}); 2458 0x6: lwr({{ 2459 uint32_t mem_shift = 8 * byte_offset; 2460 Rt_uw = (Rt_uw & (mask(mem_shift) << (32 - mem_shift))) | 2461 (mem_word >> mem_shift); 2462 }}); 2463 } 2464 } 2465 2466 0x5: decode OPCODE_LO { 2467 format StoreMemory { 2468 0x0: sb({{ Mem_ub = Rt<7:0>; }}); 2469 0x1: sh({{ Mem_uh = Rt<15:0>; }}); 2470 0x3: sw({{ Mem_uw = Rt<31:0>; }}); 2471 } 2472 2473 format StoreUnalignedMemory { 2474 0x2: swl({{ 2475 uint32_t reg_shift = 24 - (8 * byte_offset); 2476 uint32_t mem_shift = 32 - reg_shift; 2477 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2478 (Rt_uw >> reg_shift); 2479 }}); 2480 0x6: swr({{ 2481 uint32_t reg_shift = 8 * byte_offset; 2482 mem_word = Rt_uw << reg_shift | 2483 (mem_word & (mask(reg_shift))); 2484 }}); 2485 } 2486 format CP0Control { 2487 0x7: cache({{ 2488 //Addr CacheEA = Rs_uw + OFFSET; 2489 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2490 }}); 2491 } 2492 } 2493 2494 0x6: decode OPCODE_LO { 2495 format LoadMemory { 2496 0x0: ll({{ Rt_uw = Mem_uw; }}, mem_flags=LLSC); 2497 0x1: lwc1({{ Ft_uw = Mem_uw; }}); 2498 0x5: ldc1({{ Ft_ud = Mem_ud; }}); 2499 } 2500 0x2: CP2Unimpl::lwc2(); 2501 0x6: CP2Unimpl::ldc2(); 2502 0x3: Prefetch::pref(); 2503 } 2504 2505 2506 0x7: decode OPCODE_LO { 2507 0x0: StoreCond::sc({{ Mem_uw = Rt_uw; }}, 2508 {{ uint64_t tmp = write_result; 2509 Rt_uw = (tmp == 0 || tmp == 1) ? tmp : Rt_uw; 2510 }}, mem_flags=LLSC, 2511 inst_flags = IsStoreConditional); 2512 format StoreMemory { 2513 0x1: swc1({{ Mem_uw = Ft_uw; }}); 2514 0x5: sdc1({{ Mem_ud = Ft_ud; }}); 2515 } 2516 0x2: CP2Unimpl::swc2(); 2517 0x6: CP2Unimpl::sdc2(); 2518 } 2519} 2520 2521
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