746 Debug = debug; 747 }}, IsReturn, IsSerializing, IsERET); 748 } 749 format CP0TLB { 750 0x01: tlbr({{ 751 MipsISA::PTE *PTEntry = 752 xc->tcBase()->getITBPtr()-> 753 getEntry(Index & 0x7FFFFFFF); 754 if (PTEntry == NULL) { 755 fatal("Invalid PTE Entry received on " 756 "a TLBR instruction\n"); 757 } 758 /* Setup PageMask */ 759 // If 1KB pages are not enabled, a read of PageMask 760 // must return 0b00 in bits 12, 11 761 PageMask = (PTEntry->Mask << 11); 762 /* Setup EntryHi */ 763 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 764 /* Setup Entry Lo0 */ 765 EntryLo0 = ((PTEntry->PFN0 << 6) | 766 (PTEntry->C0 << 3) | 767 (PTEntry->D0 << 2) | 768 (PTEntry->V0 << 1) | 769 PTEntry->G); 770 /* Setup Entry Lo1 */ 771 EntryLo1 = ((PTEntry->PFN1 << 6) | 772 (PTEntry->C1 << 3) | 773 (PTEntry->D1 << 2) | 774 (PTEntry->V1 << 1) | 775 PTEntry->G); 776 }}); // Need to hook up to TLB 777 778 0x02: tlbwi({{ 779 //Create PTE 780 MipsISA::PTE newEntry; 781 //Write PTE 782 newEntry.Mask = (Addr)(PageMask >> 11); 783 newEntry.VPN = (Addr)(EntryHi >> 11); 784 /* PageGrain _ ESP Config3 _ SP */ 785 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 786 // If 1KB pages are *NOT* enabled, lowest bits of 787 // the mask are 0b11 for TLB writes 788 newEntry.Mask |= 0x3; 789 // Reset bits 0 and 1 if 1KB pages are not enabled 790 newEntry.VPN &= 0xFFFFFFFC; 791 } 792 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 793 794 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 795 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 796 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 797 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 798 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 799 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 800 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 801 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 802 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 803 /* Now, compute the AddrShiftAmount and OffsetMask - 804 TLB optimizations */ 805 /* Addr Shift Amount for 1KB or larger pages */ 806 if ((newEntry.Mask & 0xFFFF) == 3) { 807 newEntry.AddrShiftAmount = 12; 808 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 809 newEntry.AddrShiftAmount = 10; 810 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 811 newEntry.AddrShiftAmount = 14; 812 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 813 newEntry.AddrShiftAmount = 16; 814 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 815 newEntry.AddrShiftAmount = 18; 816 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 817 newEntry.AddrShiftAmount = 20; 818 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 819 newEntry.AddrShiftAmount = 22; 820 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 821 newEntry.AddrShiftAmount = 24; 822 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 823 newEntry.AddrShiftAmount = 26; 824 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 825 newEntry.AddrShiftAmount = 28; 826 } else { 827 fatal("Invalid Mask Pattern Detected!\n"); 828 } 829 newEntry.OffsetMask = 830 (1 << newEntry.AddrShiftAmount) - 1; 831 832 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 833 Config3Reg config3 = Config3; 834 PageGrainReg pageGrain = PageGrain; 835 int SP = 0; 836 if (bits(config3, config3.sp) == 1 && 837 bits(pageGrain, pageGrain.esp) == 1) { 838 SP = 1; 839 } 840 IndexReg index = Index; 841 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 842 }}); 843 0x06: tlbwr({{ 844 //Create PTE 845 MipsISA::PTE newEntry; 846 //Write PTE 847 newEntry.Mask = (Addr)(PageMask >> 11); 848 newEntry.VPN = (Addr)(EntryHi >> 11); 849 /* PageGrain _ ESP Config3 _ SP */ 850 if (bits(PageGrain, 28) == 0 || 851 bits(Config3, 4) == 0) { 852 // If 1KB pages are *NOT* enabled, lowest bits of 853 // the mask are 0b11 for TLB writes 854 newEntry.Mask |= 0x3; 855 // Reset bits 0 and 1 if 1KB pages are not enabled 856 newEntry.VPN &= 0xFFFFFFFC; 857 } 858 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 859 860 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 861 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 862 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 863 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 864 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 865 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 866 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 867 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 868 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 869 /* Now, compute the AddrShiftAmount and OffsetMask - 870 TLB optimizations */ 871 /* Addr Shift Amount for 1KB or larger pages */ 872 if ((newEntry.Mask & 0xFFFF) == 3){ 873 newEntry.AddrShiftAmount = 12; 874 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 875 newEntry.AddrShiftAmount = 10; 876 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 877 newEntry.AddrShiftAmount = 14; 878 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 879 newEntry.AddrShiftAmount = 16; 880 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 881 newEntry.AddrShiftAmount = 18; 882 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 883 newEntry.AddrShiftAmount = 20; 884 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 885 newEntry.AddrShiftAmount = 22; 886 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 887 newEntry.AddrShiftAmount = 24; 888 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 889 newEntry.AddrShiftAmount = 26; 890 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 891 newEntry.AddrShiftAmount = 28; 892 } else { 893 fatal("Invalid Mask Pattern Detected!\n"); 894 } 895 newEntry.OffsetMask = 896 (1 << newEntry.AddrShiftAmount) - 1; 897 898 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 899 Config3Reg config3 = Config3; 900 PageGrainReg pageGrain = PageGrain; 901 int SP = 0; 902 if (bits(config3, config3.sp) == 1 && 903 bits(pageGrain, pageGrain.esp) == 1) { 904 SP = 1; 905 } 906 IndexReg index = Index; 907 Ptr->insertAt(newEntry, Random, SP); 908 }}); 909 910 0x08: tlbp({{ 911 Config3Reg config3 = Config3; 912 PageGrainReg pageGrain = PageGrain; 913 EntryHiReg entryHi = EntryHi; 914 int tlbIndex; 915 Addr vpn; 916 if (pageGrain.esp == 1 && config3.sp ==1) { 917 vpn = EntryHi >> 11; 918 } else { 919 // Mask off lower 2 bits 920 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 921 } 922 tlbIndex = xc->tcBase()->getITBPtr()-> 923 probeEntry(vpn, entryHi.asid); 924 // Check TLB for entry matching EntryHi 925 if (tlbIndex != -1) { 926 Index = tlbIndex; 927 } else { 928 // else, set Index = 1 << 31 929 Index = (1 << 31); 930 } 931 }}); 932 } 933 format CP0Unimpl { 934 0x20: wait(); 935 } 936 default: CP0Unimpl::unknown(); 937 } 938 } 939 940 //Table A-13 MIPS32 COP1 Encoding of rs Field 941 0x1: decode RS_MSB { 942 0x0: decode RS_HI { 943 0x0: decode RS_LO { 944 format CP1Control { 945 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 946 947 0x2: cfc1({{ 948 switch (FS) { 949 case 0: 950 Rt = FIR; 951 break; 952 case 25: 953 Rt = (FCSR & 0xFE000000) >> 24 | 954 (FCSR & 0x00800000) >> 23; 955 break; 956 case 26: 957 Rt = (FCSR & 0x0003F07C); 958 break; 959 case 28: 960 Rt = (FCSR & 0x00000F80) | 961 (FCSR & 0x01000000) >> 21 | 962 (FCSR & 0x00000003); 963 break; 964 case 31: 965 Rt = FCSR; 966 break; 967 default: 968 warn("FP Control Value (%d) Not Valid"); 969 } 970 }}); 971 972 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>; }}); 973 974 0x4: mtc1({{ Fs.uw = Rt.uw; }}); 975 976 0x6: ctc1({{ 977 switch (FS) { 978 case 25: 979 FCSR = (Rt.uw<7:1> << 25) | // move 31-25 980 (FCSR & 0x01000000) | // bit 24 981 (FCSR & 0x004FFFFF); // bit 22-0 982 break; 983 case 26: 984 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 985 Rt.uw<17:12> << 12 | // bit 17-12 986 (FCSR & 0x00000F80) << 7 | // bit 11-7 987 Rt.uw<6:2> << 2 | // bit 6-2 988 (FCSR & 0x00000002); // bit 1-0 989 break; 990 case 28: 991 FCSR = (FCSR & 0xFE000000) | // move 31-25 992 Rt.uw<2:2> << 24 | // bit 24 993 (FCSR & 0x00FFF000) << 23 | // bit 23-12 994 Rt.uw<11:7> << 7 | // bit 24 995 (FCSR & 0x000007E) | 996 Rt.uw<1:0>; // bit 22-0 997 break; 998 case 31: 999 FCSR = Rt.uw; 1000 break; 1001 1002 default: 1003 panic("FP Control Value (%d) " 1004 "Not Available. Ignoring Access " 1005 "to Floating Control Status " 1006 "Register", FS); 1007 } 1008 }}); 1009 1010 0x7: mthc1({{ 1011 uint64_t fs_hi = Rt.uw; 1012 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 1013 Fs.ud = (fs_hi << 32) | fs_lo; 1014 }}); 1015 1016 } 1017 format CP1Unimpl { 1018 0x1: dmfc1(); 1019 0x5: dmtc1(); 1020 } 1021 } 1022 1023 0x1: decode RS_LO { 1024 0x0: decode ND { 1025 format Branch { 1026 0x0: decode TF { 1027 0x0: bc1f({{ 1028 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1029 }}); 1030 0x1: bc1t({{ 1031 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1032 }}); 1033 } 1034 0x1: decode TF { 1035 0x0: bc1fl({{ 1036 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1037 }}, Likely); 1038 0x1: bc1tl({{ 1039 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1040 }}, Likely); 1041 } 1042 } 1043 } 1044 format CP1Unimpl { 1045 0x1: bc1any2(); 1046 0x2: bc1any4(); 1047 default: unknown(); 1048 } 1049 } 1050 } 1051 1052 0x1: decode RS_HI { 1053 0x2: decode RS_LO { 1054 //Table A-14 MIPS32 COP1 Encoding of Function Field When 1055 //rs=S (( single-precision floating point)) 1056 0x0: decode FUNCTION_HI { 1057 0x0: decode FUNCTION_LO { 1058 format FloatOp { 1059 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf; }}); 1060 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf; }}); 1061 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf; }}); 1062 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf; }}); 1063 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf); }}); 1064 0x5: abs_s({{ Fd.sf = fabs(Fs.sf); }}); 1065 0x7: neg_s({{ Fd.sf = -Fs.sf; }}); 1066 } 1067 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf; }}); 1068 } 1069 0x1: decode FUNCTION_LO { 1070 format FloatConvertOp { 1071 0x0: round_l_s({{ val = Fs.sf; }}, 1072 ToLong, Round); 1073 0x1: trunc_l_s({{ val = Fs.sf; }}, 1074 ToLong, Trunc); 1075 0x2: ceil_l_s({{ val = Fs.sf;}}, 1076 ToLong, Ceil); 1077 0x3: floor_l_s({{ val = Fs.sf; }}, 1078 ToLong, Floor); 1079 0x4: round_w_s({{ val = Fs.sf; }}, 1080 ToWord, Round); 1081 0x5: trunc_w_s({{ val = Fs.sf; }}, 1082 ToWord, Trunc); 1083 0x6: ceil_w_s({{ val = Fs.sf; }}, 1084 ToWord, Ceil); 1085 0x7: floor_w_s({{ val = Fs.sf; }}, 1086 ToWord, Floor); 1087 } 1088 } 1089 1090 0x2: decode FUNCTION_LO { 1091 0x1: decode MOVCF { 1092 format BasicOp { 1093 0x0: movf_s({{ 1094 Fd = (getCondCode(FCSR,CC) == 0) ? 1095 Fs : Fd; 1096 }}); 1097 0x1: movt_s({{ 1098 Fd = (getCondCode(FCSR,CC) == 1) ? 1099 Fs : Fd; 1100 }}); 1101 } 1102 } 1103 1104 format BasicOp { 1105 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1106 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1107 } 1108 1109 format FloatOp { 1110 0x5: recip_s({{ Fd = 1 / Fs; }}); 1111 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 1112 } 1113 format CP1Unimpl { 1114 default: unknown(); 1115 } 1116 } 1117 0x3: CP1Unimpl::unknown(); 1118 1119 0x4: decode FUNCTION_LO { 1120 format FloatConvertOp { 1121 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 1122 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 1123 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 1124 } 1125 1126 0x6: FloatOp::cvt_ps_s({{ 1127 Fd.ud = (uint64_t) Fs.uw << 32 | 1128 (uint64_t) Ft.uw; 1129 }}); 1130 format CP1Unimpl { 1131 default: unknown(); 1132 } 1133 } 1134 0x5: CP1Unimpl::unknown(); 1135 1136 0x6: decode FUNCTION_LO { 1137 format FloatCompareOp { 1138 0x0: c_f_s({{ cond = 0; }}, 1139 SinglePrecision, UnorderedFalse); 1140 0x1: c_un_s({{ cond = 0; }}, 1141 SinglePrecision, UnorderedTrue); 1142 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 1143 UnorderedFalse); 1144 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 1145 UnorderedTrue); 1146 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 1147 UnorderedFalse); 1148 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 1149 UnorderedTrue); 1150 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 1151 UnorderedFalse); 1152 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 1153 UnorderedTrue); 1154 } 1155 } 1156 1157 0x7: decode FUNCTION_LO { 1158 format FloatCompareOp { 1159 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1160 UnorderedFalse, QnanException); 1161 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1162 UnorderedTrue, QnanException); 1163 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf); }}, 1164 UnorderedFalse, QnanException); 1165 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 1166 UnorderedTrue, QnanException); 1167 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 1168 UnorderedFalse, QnanException); 1169 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 1170 UnorderedTrue, QnanException); 1171 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 1172 UnorderedFalse, QnanException); 1173 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 1174 UnorderedTrue, QnanException); 1175 } 1176 } 1177 } 1178 1179 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1180 //rs=D 1181 0x1: decode FUNCTION_HI { 1182 0x0: decode FUNCTION_LO { 1183 format FloatOp { 1184 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 1185 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 1186 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 1187 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 1188 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 1189 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 1190 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 1191 } 1192 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 1193 } 1194 1195 0x1: decode FUNCTION_LO { 1196 format FloatConvertOp { 1197 0x0: round_l_d({{ val = Fs.df; }}, 1198 ToLong, Round); 1199 0x1: trunc_l_d({{ val = Fs.df; }}, 1200 ToLong, Trunc); 1201 0x2: ceil_l_d({{ val = Fs.df; }}, 1202 ToLong, Ceil); 1203 0x3: floor_l_d({{ val = Fs.df; }}, 1204 ToLong, Floor); 1205 0x4: round_w_d({{ val = Fs.df; }}, 1206 ToWord, Round); 1207 0x5: trunc_w_d({{ val = Fs.df; }}, 1208 ToWord, Trunc); 1209 0x6: ceil_w_d({{ val = Fs.df; }}, 1210 ToWord, Ceil); 1211 0x7: floor_w_d({{ val = Fs.df; }}, 1212 ToWord, Floor); 1213 } 1214 } 1215 1216 0x2: decode FUNCTION_LO { 1217 0x1: decode MOVCF { 1218 format BasicOp { 1219 0x0: movf_d({{ 1220 Fd.df = (getCondCode(FCSR,CC) == 0) ? 1221 Fs.df : Fd.df; 1222 }}); 1223 0x1: movt_d({{ 1224 Fd.df = (getCondCode(FCSR,CC) == 1) ? 1225 Fs.df : Fd.df; 1226 }}); 1227 } 1228 } 1229 1230 format BasicOp { 1231 0x2: movz_d({{ 1232 Fd.df = (Rt == 0) ? Fs.df : Fd.df; 1233 }}); 1234 0x3: movn_d({{ 1235 Fd.df = (Rt != 0) ? Fs.df : Fd.df; 1236 }}); 1237 } 1238 1239 format FloatOp { 1240 0x5: recip_d({{ Fd.df = 1 / Fs.df; }}); 1241 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df); }}); 1242 } 1243 format CP1Unimpl { 1244 default: unknown(); 1245 } 1246 1247 } 1248 0x4: decode FUNCTION_LO { 1249 format FloatConvertOp { 1250 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 1251 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 1252 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 1253 } 1254 default: CP1Unimpl::unknown(); 1255 } 1256 1257 0x6: decode FUNCTION_LO { 1258 format FloatCompareOp { 1259 0x0: c_f_d({{ cond = 0; }}, 1260 DoublePrecision, UnorderedFalse); 1261 0x1: c_un_d({{ cond = 0; }}, 1262 DoublePrecision, UnorderedTrue); 1263 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 1264 UnorderedFalse); 1265 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 1266 UnorderedTrue); 1267 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 1268 UnorderedFalse); 1269 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 1270 UnorderedTrue); 1271 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 1272 UnorderedFalse); 1273 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 1274 UnorderedTrue); 1275 } 1276 } 1277 1278 0x7: decode FUNCTION_LO { 1279 format FloatCompareOp { 1280 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1281 UnorderedFalse, QnanException); 1282 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1283 UnorderedTrue, QnanException); 1284 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 1285 UnorderedFalse, QnanException); 1286 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 1287 UnorderedTrue, QnanException); 1288 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 1289 UnorderedFalse, QnanException); 1290 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 1291 UnorderedTrue, QnanException); 1292 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 1293 UnorderedFalse, QnanException); 1294 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 1295 UnorderedTrue, QnanException); 1296 } 1297 } 1298 default: CP1Unimpl::unknown(); 1299 } 1300 0x2: CP1Unimpl::unknown(); 1301 0x3: CP1Unimpl::unknown(); 1302 0x7: CP1Unimpl::unknown(); 1303 1304 //Table A-16 MIPS32 COP1 Encoding of Function 1305 //Field When rs=W 1306 0x4: decode FUNCTION { 1307 format FloatConvertOp { 1308 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 1309 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 1310 0x26: CP1Unimpl::cvt_ps_w(); 1311 } 1312 default: CP1Unimpl::unknown(); 1313 } 1314 1315 //Table A-16 MIPS32 COP1 Encoding of Function Field 1316 //When rs=L1 1317 //Note: "1. Format type L is legal only if 64-bit 1318 //floating point operations are enabled." 1319 0x5: decode FUNCTION_HI { 1320 format FloatConvertOp { 1321 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 1322 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 1323 0x26: CP1Unimpl::cvt_ps_l(); 1324 } 1325 default: CP1Unimpl::unknown(); 1326 } 1327 1328 //Table A-17 MIPS64 COP1 Encoding of Function Field 1329 //When rs=PS1 1330 //Note: "1. Format type PS is legal only if 64-bit 1331 //floating point operations are enabled. " 1332 0x6: decode FUNCTION_HI { 1333 0x0: decode FUNCTION_LO { 1334 format Float64Op { 1335 0x0: add_ps({{ 1336 Fd1.sf = Fs1.sf + Ft2.sf; 1337 Fd2.sf = Fs2.sf + Ft2.sf; 1338 }}); 1339 0x1: sub_ps({{ 1340 Fd1.sf = Fs1.sf - Ft2.sf; 1341 Fd2.sf = Fs2.sf - Ft2.sf; 1342 }}); 1343 0x2: mul_ps({{ 1344 Fd1.sf = Fs1.sf * Ft2.sf; 1345 Fd2.sf = Fs2.sf * Ft2.sf; 1346 }}); 1347 0x5: abs_ps({{ 1348 Fd1.sf = fabs(Fs1.sf); 1349 Fd2.sf = fabs(Fs2.sf); 1350 }}); 1351 0x6: mov_ps({{ 1352 Fd1.sf = Fs1.sf; 1353 Fd2.sf = Fs2.sf; 1354 }}); 1355 0x7: neg_ps({{ 1356 Fd1.sf = -(Fs1.sf); 1357 Fd2.sf = -(Fs2.sf); 1358 }}); 1359 default: CP1Unimpl::unknown(); 1360 } 1361 } 1362 0x1: CP1Unimpl::unknown(); 1363 0x2: decode FUNCTION_LO { 1364 0x1: decode MOVCF { 1365 format Float64Op { 1366 0x0: movf_ps({{ 1367 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1368 Fs1 : Fd1; 1369 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1370 Fs2 : Fd2; 1371 }}); 1372 0x1: movt_ps({{ 1373 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1374 Fs1 : Fd1; 1375 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1376 Fs2 : Fd2; 1377 }}); 1378 } 1379 } 1380 1381 format Float64Op { 1382 0x2: movz_ps({{ 1383 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1384 Fs1 : Fd1; 1385 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1386 Fs2 : Fd2; 1387 }}); 1388 0x3: movn_ps({{ 1389 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1390 Fs1 : Fd1; 1391 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1392 Fs2 : Fd2; 1393 }}); 1394 } 1395 default: CP1Unimpl::unknown(); 1396 } 1397 0x3: CP1Unimpl::unknown(); 1398 0x4: decode FUNCTION_LO { 1399 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 1400 default: CP1Unimpl::unknown(); 1401 } 1402 1403 0x5: decode FUNCTION_LO { 1404 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 1405 format Float64Op { 1406 0x4: pll({{ 1407 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft1.uw; 1408 }}); 1409 0x5: plu({{ 1410 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft2.uw; 1411 }}); 1412 0x6: pul({{ 1413 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft1.uw; 1414 }}); 1415 0x7: puu({{ 1416 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft2.uw; 1417 }}); 1418 } 1419 default: CP1Unimpl::unknown(); 1420 } 1421 1422 0x6: decode FUNCTION_LO { 1423 format FloatPSCompareOp { 1424 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1425 UnorderedFalse); 1426 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1427 UnorderedTrue); 1428 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1429 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1430 UnorderedFalse); 1431 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1432 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1433 UnorderedTrue); 1434 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1435 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1436 UnorderedFalse); 1437 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 1438 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1439 UnorderedTrue); 1440 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 1441 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1442 UnorderedFalse); 1443 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1444 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1445 UnorderedTrue); 1446 } 1447 } 1448 1449 0x7: decode FUNCTION_LO { 1450 format FloatPSCompareOp { 1451 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1452 UnorderedFalse, QnanException); 1453 0x1: c_ngle_ps({{ cond1 = 0; }}, 1454 {{ cond2 = 0; }}, 1455 UnorderedTrue, QnanException); 1456 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1457 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1458 UnorderedFalse, QnanException); 1459 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1460 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1461 UnorderedTrue, QnanException); 1462 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1463 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1464 UnorderedFalse, QnanException); 1465 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1466 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1467 UnorderedTrue, QnanException); 1468 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1469 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1470 UnorderedFalse, QnanException); 1471 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1472 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1473 UnorderedTrue, QnanException); 1474 } 1475 } 1476 } 1477 } 1478 default: CP1Unimpl::unknown(); 1479 } 1480 } 1481 1482 //Table A-19 MIPS32 COP2 Encoding of rs Field 1483 0x2: decode RS_MSB { 1484 format CP2Unimpl { 1485 0x0: decode RS_HI { 1486 0x0: decode RS_LO { 1487 0x0: mfc2(); 1488 0x2: cfc2(); 1489 0x3: mfhc2(); 1490 0x4: mtc2(); 1491 0x6: ctc2(); 1492 0x7: mftc2(); 1493 default: unknown(); 1494 } 1495 1496 0x1: decode ND { 1497 0x0: decode TF { 1498 0x0: bc2f(); 1499 0x1: bc2t(); 1500 default: unknown(); 1501 } 1502 1503 0x1: decode TF { 1504 0x0: bc2fl(); 1505 0x1: bc2tl(); 1506 default: unknown(); 1507 } 1508 default: unknown(); 1509 1510 } 1511 default: unknown(); 1512 } 1513 default: unknown(); 1514 } 1515 } 1516 1517 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1518 //Note: "COP1X instructions are legal only if 64-bit floating point 1519 //operations are enabled." 1520 0x3: decode FUNCTION_HI { 1521 0x0: decode FUNCTION_LO { 1522 format LoadIndexedMemory { 1523 0x0: lwxc1({{ Fd.uw = Mem.uw; }}); 1524 0x1: ldxc1({{ Fd.ud = Mem.ud; }}); 1525 0x5: luxc1({{ Fd.ud = Mem.ud; }}, 1526 {{ EA = (Rs + Rt) & ~7; }}); 1527 } 1528 } 1529 1530 0x1: decode FUNCTION_LO { 1531 format StoreIndexedMemory { 1532 0x0: swxc1({{ Mem.uw = Fs.uw; }}); 1533 0x1: sdxc1({{ Mem.ud = Fs.ud; }}); 1534 0x5: suxc1({{ Mem.ud = Fs.ud; }}, 1535 {{ EA = (Rs + Rt) & ~7; }}); 1536 } 1537 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1538 } 1539 1540 0x3: decode FUNCTION_LO { 1541 0x6: Float64Op::alnv_ps({{ 1542 if (Rs<2:0> == 0) { 1543 Fd.ud = Fs.ud; 1544 } else if (Rs<2:0> == 4) { 1545#if BYTE_ORDER == BIG_ENDIAN 1546 Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>; 1547#elif BYTE_ORDER == LITTLE_ENDIAN 1548 Fd.ud = Ft.ud<31:0> << 32 | Fs.ud<63:32>; 1549#endif 1550 } else { 1551 Fd.ud = Fd.ud; 1552 } 1553 }}); 1554 } 1555 1556 format FloatAccOp { 1557 0x4: decode FUNCTION_LO { 1558 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 1559 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 1560 0x6: madd_ps({{ 1561 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 1562 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 1563 }}); 1564 } 1565 1566 0x5: decode FUNCTION_LO { 1567 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 1568 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 1569 0x6: msub_ps({{ 1570 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 1571 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 1572 }}); 1573 } 1574 1575 0x6: decode FUNCTION_LO { 1576 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1577 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 1578 0x6: nmadd_ps({{ 1579 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 1580 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 1581 }}); 1582 } 1583 1584 0x7: decode FUNCTION_LO { 1585 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1586 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 1587 0x6: nmsub_ps({{ 1588 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 1589 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 1590 }}); 1591 } 1592 } 1593 } 1594 1595 format Branch { 1596 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 1597 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 1598 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 1599 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 1600 } 1601 } 1602 1603 0x3: decode OPCODE_LO { 1604 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1605 0x4: decode FUNCTION_HI { 1606 0x0: decode FUNCTION_LO { 1607 0x2: IntOp::mul({{ 1608 int64_t temp1 = Rs.sd * Rt.sd; 1609 Rd.sw = temp1<31:0>; 1610 }}, IntMultOp); 1611 1612 format HiLoRdSelValOp { 1613 0x0: madd({{ 1614 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1615 (Rs.sd * Rt.sd); 1616 }}, IntMultOp); 1617 0x1: maddu({{ 1618 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1619 (Rs.ud * Rt.ud); 1620 }}, IntMultOp); 1621 0x4: msub({{ 1622 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1623 (Rs.sd * Rt.sd); 1624 }}, IntMultOp); 1625 0x5: msubu({{ 1626 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1627 (Rs.ud * Rt.ud); 1628 }}, IntMultOp); 1629 } 1630 } 1631 1632 0x4: decode FUNCTION_LO { 1633 format BasicOp { 1634 0x0: clz({{ 1635 int cnt = 32; 1636 for (int idx = 31; idx >= 0; idx--) { 1637 if (Rs<idx:idx> == 1) { 1638 cnt = 31 - idx; 1639 break; 1640 } 1641 } 1642 Rd.uw = cnt; 1643 }}); 1644 0x1: clo({{ 1645 int cnt = 32; 1646 for (int idx = 31; idx >= 0; idx--) { 1647 if (Rs<idx:idx> == 0) { 1648 cnt = 31 - idx; 1649 break; 1650 } 1651 } 1652 Rd.uw = cnt; 1653 }}); 1654 } 1655 } 1656 1657 0x7: decode FUNCTION_LO { 1658 0x7: FailUnimpl::sdbbp(); 1659 } 1660 } 1661 1662 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1663 //of the Architecture 1664 0x7: decode FUNCTION_HI { 1665 0x0: decode FUNCTION_LO { 1666 format BasicOp { 1667 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 1668 0x4: ins({{ 1669 Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1670 bits(Rs.uw, MSB-LSB, 0) << LSB | 1671 bits(Rt.uw, LSB-1, 0); 1672 }}); 1673 } 1674 } 1675 1676 0x1: decode FUNCTION_LO { 1677 format MT_Control { 1678 0x0: fork({{ 1679 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1680 }}, UserMode); 1681 0x1: yield({{ 1682 Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, 1683 YQMask); 1684 }}, UserMode); 1685 } 1686 1687 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1688 0x2: decode OP_HI { 1689 0x0: decode OP_LO { 1690 format LoadIndexedMemory { 1691 0x0: lwx({{ Rd.sw = Mem.sw; }}); 1692 0x4: lhx({{ Rd.sw = Mem.sh; }}); 1693 0x6: lbux({{ Rd.uw = Mem.ub; }}); 1694 } 1695 } 1696 } 1697 0x4: DspIntOp::insv({{ 1698 int pos = dspctl<5:0>; 1699 int size = dspctl<12:7> - 1; 1700 Rt.uw = insertBits(Rt.uw, pos+size, 1701 pos, Rs.uw<size:0>); 1702 }}); 1703 } 1704 1705 0x2: decode FUNCTION_LO { 1706 1707 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1708 //(DSP ASE MANUAL) 1709 0x0: decode OP_HI { 1710 0x0: decode OP_LO { 1711 format DspIntOp { 1712 0x0: addu_qb({{ 1713 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1714 NOSATURATE, UNSIGNED, &dspctl); 1715 }}); 1716 0x1: subu_qb({{ 1717 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1718 NOSATURATE, UNSIGNED, &dspctl); 1719 }}); 1720 0x4: addu_s_qb({{ 1721 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1722 SATURATE, UNSIGNED, &dspctl); 1723 }}); 1724 0x5: subu_s_qb({{ 1725 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1726 SATURATE, UNSIGNED, &dspctl); 1727 }}); 1728 0x6: muleu_s_ph_qbl({{ 1729 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1730 MODE_L, &dspctl); 1731 }}, IntMultOp); 1732 0x7: muleu_s_ph_qbr({{ 1733 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1734 MODE_R, &dspctl); 1735 }}, IntMultOp); 1736 } 1737 } 1738 0x1: decode OP_LO { 1739 format DspIntOp { 1740 0x0: addu_ph({{ 1741 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1742 NOSATURATE, UNSIGNED, &dspctl); 1743 }}); 1744 0x1: subu_ph({{ 1745 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1746 NOSATURATE, UNSIGNED, &dspctl); 1747 }}); 1748 0x2: addq_ph({{ 1749 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1750 NOSATURATE, SIGNED, &dspctl); 1751 }}); 1752 0x3: subq_ph({{ 1753 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1754 NOSATURATE, SIGNED, &dspctl); 1755 }}); 1756 0x4: addu_s_ph({{ 1757 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1758 SATURATE, UNSIGNED, &dspctl); 1759 }}); 1760 0x5: subu_s_ph({{ 1761 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1762 SATURATE, UNSIGNED, &dspctl); 1763 }}); 1764 0x6: addq_s_ph({{ 1765 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1766 SATURATE, SIGNED, &dspctl); 1767 }}); 1768 0x7: subq_s_ph({{ 1769 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1770 SATURATE, SIGNED, &dspctl); 1771 }}); 1772 } 1773 } 1774 0x2: decode OP_LO { 1775 format DspIntOp { 1776 0x0: addsc({{ 1777 int64_t dresult; 1778 dresult = Rs.ud + Rt.ud; 1779 Rd.sw = dresult<31:0>; 1780 dspctl = insertBits(dspctl, 13, 13, 1781 dresult<32:32>); 1782 }}); 1783 0x1: addwc({{ 1784 int64_t dresult; 1785 dresult = Rs.sd + Rt.sd + dspctl<13:13>; 1786 Rd.sw = dresult<31:0>; 1787 if (dresult<32:32> != dresult<31:31>) 1788 dspctl = insertBits(dspctl, 20, 20, 1); 1789 }}); 1790 0x2: modsub({{ 1791 Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : 1792 Rs.sw - Rt.sw<7:0>; 1793 }}); 1794 0x4: raddu_w_qb({{ 1795 Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 1796 Rs.uw<15:8> + Rs.uw<7:0>; 1797 }}); 1798 0x6: addq_s_w({{ 1799 Rd.sw = dspAdd(Rs.sw, Rt.sw, SIMD_FMT_W, 1800 SATURATE, SIGNED, &dspctl); 1801 }}); 1802 0x7: subq_s_w({{ 1803 Rd.sw = dspSub(Rs.sw, Rt.sw, SIMD_FMT_W, 1804 SATURATE, SIGNED, &dspctl); 1805 }}); 1806 } 1807 } 1808 0x3: decode OP_LO { 1809 format DspIntOp { 1810 0x4: muleq_s_w_phl({{ 1811 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1812 MODE_L, &dspctl); 1813 }}, IntMultOp); 1814 0x5: muleq_s_w_phr({{ 1815 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1816 MODE_R, &dspctl); 1817 }}, IntMultOp); 1818 0x6: mulq_s_ph({{ 1819 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1820 SATURATE, NOROUND, &dspctl); 1821 }}, IntMultOp); 1822 0x7: mulq_rs_ph({{ 1823 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1824 SATURATE, ROUND, &dspctl); 1825 }}, IntMultOp); 1826 } 1827 } 1828 } 1829 1830 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1831 //(DSP ASE MANUAL) 1832 0x1: decode OP_HI { 1833 0x0: decode OP_LO { 1834 format DspIntOp { 1835 0x0: cmpu_eq_qb({{ 1836 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1837 UNSIGNED, CMP_EQ, &dspctl); 1838 }}); 1839 0x1: cmpu_lt_qb({{ 1840 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1841 UNSIGNED, CMP_LT, &dspctl); 1842 }}); 1843 0x2: cmpu_le_qb({{ 1844 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1845 UNSIGNED, CMP_LE, &dspctl); 1846 }}); 1847 0x3: pick_qb({{ 1848 Rd.uw = dspPick(Rs.uw, Rt.uw, 1849 SIMD_FMT_QB, &dspctl); 1850 }}); 1851 0x4: cmpgu_eq_qb({{ 1852 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1853 UNSIGNED, CMP_EQ ); 1854 }}); 1855 0x5: cmpgu_lt_qb({{ 1856 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1857 UNSIGNED, CMP_LT); 1858 }}); 1859 0x6: cmpgu_le_qb({{ 1860 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1861 UNSIGNED, CMP_LE); 1862 }}); 1863 } 1864 } 1865 0x1: decode OP_LO { 1866 format DspIntOp { 1867 0x0: cmp_eq_ph({{ 1868 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1869 SIGNED, CMP_EQ, &dspctl); 1870 }}); 1871 0x1: cmp_lt_ph({{ 1872 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1873 SIGNED, CMP_LT, &dspctl); 1874 }}); 1875 0x2: cmp_le_ph({{ 1876 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1877 SIGNED, CMP_LE, &dspctl); 1878 }}); 1879 0x3: pick_ph({{ 1880 Rd.uw = dspPick(Rs.uw, Rt.uw, 1881 SIMD_FMT_PH, &dspctl); 1882 }}); 1883 0x4: precrq_qb_ph({{ 1884 Rd.uw = Rs.uw<31:24> << 24 | 1885 Rs.uw<15:8> << 16 | 1886 Rt.uw<31:24> << 8 | 1887 Rt.uw<15:8>; 1888 }}); 1889 0x5: precr_qb_ph({{ 1890 Rd.uw = Rs.uw<23:16> << 24 | 1891 Rs.uw<7:0> << 16 | 1892 Rt.uw<23:16> << 8 | 1893 Rt.uw<7:0>; 1894 }}); 1895 0x6: packrl_ph({{ 1896 Rd.uw = dspPack(Rs.uw, Rt.uw, SIMD_FMT_PH); 1897 }}); 1898 0x7: precrqu_s_qb_ph({{ 1899 Rd.uw = dspPrecrqu(Rs.uw, Rt.uw, &dspctl); 1900 }}); 1901 } 1902 } 1903 0x2: decode OP_LO { 1904 format DspIntOp { 1905 0x4: precrq_ph_w({{ 1906 Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; 1907 }}); 1908 0x5: precrq_rs_ph_w({{ 1909 Rd.uw = dspPrecrq(Rs.uw, Rt.uw, 1910 SIMD_FMT_W, &dspctl); 1911 }}); 1912 } 1913 } 1914 0x3: decode OP_LO { 1915 format DspIntOp { 1916 0x0: cmpgdu_eq_qb({{ 1917 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1918 UNSIGNED, CMP_EQ, &dspctl); 1919 }}); 1920 0x1: cmpgdu_lt_qb({{ 1921 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1922 UNSIGNED, CMP_LT, &dspctl); 1923 }}); 1924 0x2: cmpgdu_le_qb({{ 1925 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1926 UNSIGNED, CMP_LE, &dspctl); 1927 }}); 1928 0x6: precr_sra_ph_w({{ 1929 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1930 SIMD_FMT_W, NOROUND); 1931 }}); 1932 0x7: precr_sra_r_ph_w({{ 1933 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1934 SIMD_FMT_W, ROUND); 1935 }}); 1936 } 1937 } 1938 } 1939 1940 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1941 //(DSP ASE MANUAL) 1942 0x2: decode OP_HI { 1943 0x0: decode OP_LO { 1944 format DspIntOp { 1945 0x1: absq_s_qb({{ 1946 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_QB, &dspctl); 1947 }}); 1948 0x2: repl_qb({{ 1949 Rd.uw = RS_RT<7:0> << 24 | 1950 RS_RT<7:0> << 16 | 1951 RS_RT<7:0> << 8 | 1952 RS_RT<7:0>; 1953 }}); 1954 0x3: replv_qb({{ 1955 Rd.sw = Rt.uw<7:0> << 24 | 1956 Rt.uw<7:0> << 16 | 1957 Rt.uw<7:0> << 8 | 1958 Rt.uw<7:0>; 1959 }}); 1960 0x4: precequ_ph_qbl({{ 1961 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1962 SIMD_FMT_PH, SIGNED, MODE_L); 1963 }}); 1964 0x5: precequ_ph_qbr({{ 1965 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1966 SIMD_FMT_PH, SIGNED, MODE_R); 1967 }}); 1968 0x6: precequ_ph_qbla({{ 1969 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1970 SIMD_FMT_PH, SIGNED, MODE_LA); 1971 }}); 1972 0x7: precequ_ph_qbra({{ 1973 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1974 SIMD_FMT_PH, SIGNED, MODE_RA); 1975 }}); 1976 } 1977 } 1978 0x1: decode OP_LO { 1979 format DspIntOp { 1980 0x1: absq_s_ph({{ 1981 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_PH, &dspctl); 1982 }}); 1983 0x2: repl_ph({{ 1984 Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 1985 (sext<10>(RS_RT))<15:0>; 1986 }}); 1987 0x3: replv_ph({{ 1988 Rd.uw = Rt.uw<15:0> << 16 | 1989 Rt.uw<15:0>; 1990 }}); 1991 0x4: preceq_w_phl({{ 1992 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1993 SIMD_FMT_W, SIGNED, MODE_L); 1994 }}); 1995 0x5: preceq_w_phr({{ 1996 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1997 SIMD_FMT_W, SIGNED, MODE_R); 1998 }}); 1999 } 2000 } 2001 0x2: decode OP_LO { 2002 format DspIntOp { 2003 0x1: absq_s_w({{ 2004 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_W, &dspctl); 2005 }}); 2006 } 2007 } 2008 0x3: decode OP_LO { 2009 0x3: IntOp::bitrev({{ 2010 Rd.uw = bitrev( Rt.uw<15:0> ); 2011 }}); 2012 format DspIntOp { 2013 0x4: preceu_ph_qbl({{ 2014 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2015 UNSIGNED, SIMD_FMT_PH, 2016 UNSIGNED, MODE_L); 2017 }}); 2018 0x5: preceu_ph_qbr({{ 2019 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2020 UNSIGNED, SIMD_FMT_PH, 2021 UNSIGNED, MODE_R ); 2022 }}); 2023 0x6: preceu_ph_qbla({{ 2024 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2025 UNSIGNED, SIMD_FMT_PH, 2026 UNSIGNED, MODE_LA ); 2027 }}); 2028 0x7: preceu_ph_qbra({{ 2029 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2030 UNSIGNED, SIMD_FMT_PH, 2031 UNSIGNED, MODE_RA); 2032 }}); 2033 } 2034 } 2035 } 2036 2037 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 2038 //(DSP ASE MANUAL) 2039 0x3: decode OP_HI { 2040 0x0: decode OP_LO { 2041 format DspIntOp { 2042 0x0: shll_qb({{ 2043 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_QB, 2044 NOSATURATE, UNSIGNED, &dspctl); 2045 }}); 2046 0x1: shrl_qb({{ 2047 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_QB, 2048 UNSIGNED); 2049 }}); 2050 0x2: shllv_qb({{ 2051 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_QB, 2052 NOSATURATE, UNSIGNED, &dspctl); 2053 }}); 2054 0x3: shrlv_qb({{ 2055 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_QB, 2056 UNSIGNED); 2057 }}); 2058 0x4: shra_qb({{ 2059 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2060 NOROUND, SIGNED, &dspctl); 2061 }}); 2062 0x5: shra_r_qb({{ 2063 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2064 ROUND, SIGNED, &dspctl); 2065 }}); 2066 0x6: shrav_qb({{ 2067 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2068 NOROUND, SIGNED, &dspctl); 2069 }}); 2070 0x7: shrav_r_qb({{ 2071 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2072 ROUND, SIGNED, &dspctl); 2073 }}); 2074 } 2075 } 2076 0x1: decode OP_LO { 2077 format DspIntOp { 2078 0x0: shll_ph({{ 2079 Rd.uw = dspShll(Rt.uw, RS, SIMD_FMT_PH, 2080 NOSATURATE, SIGNED, &dspctl); 2081 }}); 2082 0x1: shra_ph({{ 2083 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2084 NOROUND, SIGNED, &dspctl); 2085 }}); 2086 0x2: shllv_ph({{ 2087 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2088 NOSATURATE, SIGNED, &dspctl); 2089 }}); 2090 0x3: shrav_ph({{ 2091 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2092 NOROUND, SIGNED, &dspctl); 2093 }}); 2094 0x4: shll_s_ph({{ 2095 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_PH, 2096 SATURATE, SIGNED, &dspctl); 2097 }}); 2098 0x5: shra_r_ph({{ 2099 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2100 ROUND, SIGNED, &dspctl); 2101 }}); 2102 0x6: shllv_s_ph({{ 2103 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2104 SATURATE, SIGNED, &dspctl); 2105 }}); 2106 0x7: shrav_r_ph({{ 2107 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2108 ROUND, SIGNED, &dspctl); 2109 }}); 2110 } 2111 } 2112 0x2: decode OP_LO { 2113 format DspIntOp { 2114 0x4: shll_s_w({{ 2115 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_W, 2116 SATURATE, SIGNED, &dspctl); 2117 }}); 2118 0x5: shra_r_w({{ 2119 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_W, 2120 ROUND, SIGNED, &dspctl); 2121 }}); 2122 0x6: shllv_s_w({{ 2123 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_W, 2124 SATURATE, SIGNED, &dspctl); 2125 }}); 2126 0x7: shrav_r_w({{ 2127 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_W, 2128 ROUND, SIGNED, &dspctl); 2129 }}); 2130 } 2131 } 2132 0x3: decode OP_LO { 2133 format DspIntOp { 2134 0x1: shrl_ph({{ 2135 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_PH, 2136 UNSIGNED); 2137 }}); 2138 0x3: shrlv_ph({{ 2139 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_PH, 2140 UNSIGNED); 2141 }}); 2142 } 2143 } 2144 } 2145 } 2146 2147 0x3: decode FUNCTION_LO { 2148 2149 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2150 //(DSP ASE Rev2 Manual) 2151 0x0: decode OP_HI { 2152 0x0: decode OP_LO { 2153 format DspIntOp { 2154 0x0: adduh_qb({{ 2155 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2156 NOROUND, UNSIGNED); 2157 }}); 2158 0x1: subuh_qb({{ 2159 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2160 NOROUND, UNSIGNED); 2161 }}); 2162 0x2: adduh_r_qb({{ 2163 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2164 ROUND, UNSIGNED); 2165 }}); 2166 0x3: subuh_r_qb({{ 2167 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2168 ROUND, UNSIGNED); 2169 }}); 2170 } 2171 } 2172 0x1: decode OP_LO { 2173 format DspIntOp { 2174 0x0: addqh_ph({{ 2175 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2176 NOROUND, SIGNED); 2177 }}); 2178 0x1: subqh_ph({{ 2179 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2180 NOROUND, SIGNED); 2181 }}); 2182 0x2: addqh_r_ph({{ 2183 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2184 ROUND, SIGNED); 2185 }}); 2186 0x3: subqh_r_ph({{ 2187 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2188 ROUND, SIGNED); 2189 }}); 2190 0x4: mul_ph({{ 2191 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2192 NOSATURATE, &dspctl); 2193 }}, IntMultOp); 2194 0x6: mul_s_ph({{ 2195 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2196 SATURATE, &dspctl); 2197 }}, IntMultOp); 2198 } 2199 } 2200 0x2: decode OP_LO { 2201 format DspIntOp { 2202 0x0: addqh_w({{ 2203 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2204 NOROUND, SIGNED); 2205 }}); 2206 0x1: subqh_w({{ 2207 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2208 NOROUND, SIGNED); 2209 }}); 2210 0x2: addqh_r_w({{ 2211 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2212 ROUND, SIGNED); 2213 }}); 2214 0x3: subqh_r_w({{ 2215 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2216 ROUND, SIGNED); 2217 }}); 2218 0x6: mulq_s_w({{ 2219 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2220 SATURATE, NOROUND, &dspctl); 2221 }}, IntMultOp); 2222 0x7: mulq_rs_w({{ 2223 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2224 SATURATE, ROUND, &dspctl); 2225 }}, IntMultOp); 2226 } 2227 } 2228 } 2229 } 2230 2231 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2232 0x4: decode SA { 2233 format BasicOp { 2234 0x02: wsbh({{ 2235 Rd.uw = Rt.uw<23:16> << 24 | 2236 Rt.uw<31:24> << 16 | 2237 Rt.uw<7:0> << 8 | 2238 Rt.uw<15:8>; 2239 }}); 2240 0x10: seb({{ Rd.sw = Rt.sb; }}); 2241 0x18: seh({{ Rd.sw = Rt.sh; }}); 2242 } 2243 } 2244 2245 0x6: decode FUNCTION_LO { 2246 2247 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2248 //(DSP ASE MANUAL) 2249 0x0: decode OP_HI { 2250 0x0: decode OP_LO { 2251 format DspHiLoOp { 2252 0x0: dpa_w_ph({{ 2253 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2254 SIMD_FMT_PH, SIGNED, MODE_L); 2255 }}, IntMultOp); 2256 0x1: dps_w_ph({{ 2257 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2258 SIMD_FMT_PH, SIGNED, MODE_L); 2259 }}, IntMultOp); 2260 0x2: mulsa_w_ph({{ 2261 dspac = dspMulsa(dspac, Rs.sw, Rt.sw, 2262 ACDST, SIMD_FMT_PH ); 2263 }}, IntMultOp); 2264 0x3: dpau_h_qbl({{ 2265 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2266 SIMD_FMT_QB, UNSIGNED, MODE_L); 2267 }}, IntMultOp); 2268 0x4: dpaq_s_w_ph({{ 2269 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2270 ACDST, SIMD_FMT_PH, 2271 SIMD_FMT_W, NOSATURATE, 2272 MODE_L, &dspctl); 2273 }}, IntMultOp); 2274 0x5: dpsq_s_w_ph({{ 2275 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2276 ACDST, SIMD_FMT_PH, 2277 SIMD_FMT_W, NOSATURATE, 2278 MODE_L, &dspctl); 2279 }}, IntMultOp); 2280 0x6: mulsaq_s_w_ph({{ 2281 dspac = dspMulsaq(dspac, Rs.sw, Rt.sw, 2282 ACDST, SIMD_FMT_PH, 2283 &dspctl); 2284 }}, IntMultOp); 2285 0x7: dpau_h_qbr({{ 2286 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2287 SIMD_FMT_QB, UNSIGNED, MODE_R); 2288 }}, IntMultOp); 2289 } 2290 } 2291 0x1: decode OP_LO { 2292 format DspHiLoOp { 2293 0x0: dpax_w_ph({{ 2294 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2295 SIMD_FMT_PH, SIGNED, MODE_X); 2296 }}, IntMultOp); 2297 0x1: dpsx_w_ph({{ 2298 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2299 SIMD_FMT_PH, SIGNED, MODE_X); 2300 }}, IntMultOp); 2301 0x3: dpsu_h_qbl({{ 2302 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2303 SIMD_FMT_QB, UNSIGNED, MODE_L); 2304 }}, IntMultOp); 2305 0x4: dpaq_sa_l_w({{ 2306 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2307 ACDST, SIMD_FMT_W, 2308 SIMD_FMT_L, SATURATE, 2309 MODE_L, &dspctl); 2310 }}, IntMultOp); 2311 0x5: dpsq_sa_l_w({{ 2312 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2313 ACDST, SIMD_FMT_W, 2314 SIMD_FMT_L, SATURATE, 2315 MODE_L, &dspctl); 2316 }}, IntMultOp); 2317 0x7: dpsu_h_qbr({{ 2318 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2319 SIMD_FMT_QB, UNSIGNED, MODE_R); 2320 }}, IntMultOp); 2321 } 2322 } 2323 0x2: decode OP_LO { 2324 format DspHiLoOp { 2325 0x0: maq_sa_w_phl({{ 2326 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2327 ACDST, SIMD_FMT_PH, 2328 MODE_L, SATURATE, &dspctl); 2329 }}, IntMultOp); 2330 0x2: maq_sa_w_phr({{ 2331 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2332 ACDST, SIMD_FMT_PH, 2333 MODE_R, SATURATE, &dspctl); 2334 }}, IntMultOp); 2335 0x4: maq_s_w_phl({{ 2336 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2337 ACDST, SIMD_FMT_PH, 2338 MODE_L, NOSATURATE, &dspctl); 2339 }}, IntMultOp); 2340 0x6: maq_s_w_phr({{ 2341 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2342 ACDST, SIMD_FMT_PH, 2343 MODE_R, NOSATURATE, &dspctl); 2344 }}, IntMultOp); 2345 } 2346 } 2347 0x3: decode OP_LO { 2348 format DspHiLoOp { 2349 0x0: dpaqx_s_w_ph({{ 2350 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2351 ACDST, SIMD_FMT_PH, 2352 SIMD_FMT_W, NOSATURATE, 2353 MODE_X, &dspctl); 2354 }}, IntMultOp); 2355 0x1: dpsqx_s_w_ph({{ 2356 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2357 ACDST, SIMD_FMT_PH, 2358 SIMD_FMT_W, NOSATURATE, 2359 MODE_X, &dspctl); 2360 }}, IntMultOp); 2361 0x2: dpaqx_sa_w_ph({{ 2362 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2363 ACDST, SIMD_FMT_PH, 2364 SIMD_FMT_W, SATURATE, 2365 MODE_X, &dspctl); 2366 }}, IntMultOp); 2367 0x3: dpsqx_sa_w_ph({{ 2368 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2369 ACDST, SIMD_FMT_PH, 2370 SIMD_FMT_W, SATURATE, 2371 MODE_X, &dspctl); 2372 }}, IntMultOp); 2373 } 2374 } 2375 } 2376 2377 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2378 0x1: decode OP_HI { 2379 0x0: decode OP_LO { 2380 format IntOp { 2381 0x0: append({{ 2382 Rt.uw = (Rt.uw << RD) | bits(Rs.uw, RD - 1, 0); 2383 }}); 2384 0x1: prepend({{ 2385 Rt.uw = (Rt.uw >> RD) | 2386 (bits(Rs.uw, RD - 1, 0) << (32 - RD)); 2387 }}); 2388 } 2389 } 2390 0x2: decode OP_LO { 2391 format IntOp { 2392 0x0: balign({{ 2393 Rt.uw = (Rt.uw << (8 * BP)) | 2394 (Rs.uw >> (8 * (4 - BP))); 2395 }}); 2396 } 2397 } 2398 } 2399 2400 } 2401 0x7: decode FUNCTION_LO { 2402 2403 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2404 //(DSP ASE MANUAL) 2405 0x0: decode OP_HI { 2406 0x0: decode OP_LO { 2407 format DspHiLoOp { 2408 0x0: extr_w({{ 2409 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2410 NOROUND, NOSATURATE, &dspctl); 2411 }}); 2412 0x1: extrv_w({{ 2413 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2414 NOROUND, NOSATURATE, &dspctl); 2415 }}); 2416 0x2: extp({{ 2417 Rt.uw = dspExtp(dspac, RS, &dspctl); 2418 }}); 2419 0x3: extpv({{ 2420 Rt.uw = dspExtp(dspac, Rs.uw, &dspctl); 2421 }}); 2422 0x4: extr_r_w({{ 2423 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2424 ROUND, NOSATURATE, &dspctl); 2425 }}); 2426 0x5: extrv_r_w({{ 2427 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2428 ROUND, NOSATURATE, &dspctl); 2429 }}); 2430 0x6: extr_rs_w({{ 2431 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2432 ROUND, SATURATE, &dspctl); 2433 }}); 2434 0x7: extrv_rs_w({{ 2435 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2436 ROUND, SATURATE, &dspctl); 2437 }}); 2438 } 2439 } 2440 0x1: decode OP_LO { 2441 format DspHiLoOp { 2442 0x2: extpdp({{ 2443 Rt.uw = dspExtpd(dspac, RS, &dspctl); 2444 }}); 2445 0x3: extpdpv({{ 2446 Rt.uw = dspExtpd(dspac, Rs.uw, &dspctl); 2447 }}); 2448 0x6: extr_s_h({{ 2449 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2450 NOROUND, SATURATE, &dspctl); 2451 }}); 2452 0x7: extrv_s_h({{ 2453 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, Rs.uw, 2454 NOROUND, SATURATE, &dspctl); 2455 }}); 2456 } 2457 } 2458 0x2: decode OP_LO { 2459 format DspIntOp { 2460 0x2: rddsp({{ 2461 Rd.uw = readDSPControl(&dspctl, RDDSPMASK); 2462 }}); 2463 0x3: wrdsp({{ 2464 writeDSPControl(&dspctl, Rs.uw, WRDSPMASK); 2465 }}); 2466 } 2467 } 2468 0x3: decode OP_LO { 2469 format DspHiLoOp { 2470 0x2: shilo({{ 2471 if (sext<6>(HILOSA) < 0) { 2472 dspac = (uint64_t)dspac << 2473 -sext<6>(HILOSA); 2474 } else { 2475 dspac = (uint64_t)dspac >> 2476 sext<6>(HILOSA); 2477 } 2478 }}); 2479 0x3: shilov({{ 2480 if (sext<6>(Rs.sw<5:0>) < 0) { 2481 dspac = (uint64_t)dspac << 2482 -sext<6>(Rs.sw<5:0>); 2483 } else { 2484 dspac = (uint64_t)dspac >> 2485 sext<6>(Rs.sw<5:0>); 2486 } 2487 }}); 2488 0x7: mthlip({{ 2489 dspac = dspac << 32; 2490 dspac |= Rs.uw; 2491 dspctl = insertBits(dspctl, 5, 0, 2492 dspctl<5:0> + 32); 2493 }}); 2494 } 2495 } 2496 } 2497 0x3: decode OP { 2498#if FULL_SYSTEM 2499 0x0: FailUnimpl::rdhwr(); 2500#else 2501 0x0: decode RD { 2502 29: BasicOp::rdhwr({{ Rt = TpValue; }}); 2503 } 2504#endif 2505 } 2506 } 2507 } 2508 } 2509 2510 0x4: decode OPCODE_LO { 2511 format LoadMemory { 2512 0x0: lb({{ Rt.sw = Mem.sb; }}); 2513 0x1: lh({{ Rt.sw = Mem.sh; }}); 2514 0x3: lw({{ Rt.sw = Mem.sw; }}); 2515 0x4: lbu({{ Rt.uw = Mem.ub;}}); 2516 0x5: lhu({{ Rt.uw = Mem.uh; }}); 2517 } 2518 2519 format LoadUnalignedMemory { 2520 0x2: lwl({{ 2521 uint32_t mem_shift = 24 - (8 * byte_offset); 2522 Rt.uw = mem_word << mem_shift | (Rt.uw & mask(mem_shift)); 2523 }}); 2524 0x6: lwr({{ 2525 uint32_t mem_shift = 8 * byte_offset; 2526 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | 2527 (mem_word >> mem_shift); 2528 }}); 2529 } 2530 } 2531 2532 0x5: decode OPCODE_LO { 2533 format StoreMemory { 2534 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 2535 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 2536 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 2537 } 2538 2539 format StoreUnalignedMemory { 2540 0x2: swl({{ 2541 uint32_t reg_shift = 24 - (8 * byte_offset); 2542 uint32_t mem_shift = 32 - reg_shift; 2543 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2544 (Rt.uw >> reg_shift); 2545 }}); 2546 0x6: swr({{ 2547 uint32_t reg_shift = 8 * byte_offset; 2548 mem_word = Rt.uw << reg_shift | 2549 (mem_word & (mask(reg_shift))); 2550 }}); 2551 } 2552 format CP0Control { 2553 0x7: cache({{ 2554 //Addr CacheEA = Rs.uw + OFFSET; 2555 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2556 }}); 2557 } 2558 } 2559 2560 0x6: decode OPCODE_LO { 2561 format LoadMemory { 2562 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC); 2563 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 2564 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 2565 } 2566 0x2: CP2Unimpl::lwc2(); 2567 0x6: CP2Unimpl::ldc2(); 2568 0x3: Prefetch::pref(); 2569 } 2570 2571 2572 0x7: decode OPCODE_LO { 2573 0x0: StoreCond::sc({{ Mem.uw = Rt.uw; }}, 2574 {{ uint64_t tmp = write_result; 2575 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 2576 }}, mem_flags=LLSC, 2577 inst_flags = IsStoreConditional); 2578 format StoreMemory { 2579 0x1: swc1({{ Mem.uw = Ft.uw; }}); 2580 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 2581 } 2582 0x2: CP2Unimpl::swc2(); 2583 0x6: CP2Unimpl::sdc2(); 2584 } 2585} 2586 2587
| 734 Debug = debug; 735 }}, IsReturn, IsSerializing, IsERET); 736 } 737 format CP0TLB { 738 0x01: tlbr({{ 739 MipsISA::PTE *PTEntry = 740 xc->tcBase()->getITBPtr()-> 741 getEntry(Index & 0x7FFFFFFF); 742 if (PTEntry == NULL) { 743 fatal("Invalid PTE Entry received on " 744 "a TLBR instruction\n"); 745 } 746 /* Setup PageMask */ 747 // If 1KB pages are not enabled, a read of PageMask 748 // must return 0b00 in bits 12, 11 749 PageMask = (PTEntry->Mask << 11); 750 /* Setup EntryHi */ 751 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 752 /* Setup Entry Lo0 */ 753 EntryLo0 = ((PTEntry->PFN0 << 6) | 754 (PTEntry->C0 << 3) | 755 (PTEntry->D0 << 2) | 756 (PTEntry->V0 << 1) | 757 PTEntry->G); 758 /* Setup Entry Lo1 */ 759 EntryLo1 = ((PTEntry->PFN1 << 6) | 760 (PTEntry->C1 << 3) | 761 (PTEntry->D1 << 2) | 762 (PTEntry->V1 << 1) | 763 PTEntry->G); 764 }}); // Need to hook up to TLB 765 766 0x02: tlbwi({{ 767 //Create PTE 768 MipsISA::PTE newEntry; 769 //Write PTE 770 newEntry.Mask = (Addr)(PageMask >> 11); 771 newEntry.VPN = (Addr)(EntryHi >> 11); 772 /* PageGrain _ ESP Config3 _ SP */ 773 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 774 // If 1KB pages are *NOT* enabled, lowest bits of 775 // the mask are 0b11 for TLB writes 776 newEntry.Mask |= 0x3; 777 // Reset bits 0 and 1 if 1KB pages are not enabled 778 newEntry.VPN &= 0xFFFFFFFC; 779 } 780 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 781 782 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 783 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 784 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 785 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 786 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 787 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 788 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 789 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 790 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 791 /* Now, compute the AddrShiftAmount and OffsetMask - 792 TLB optimizations */ 793 /* Addr Shift Amount for 1KB or larger pages */ 794 if ((newEntry.Mask & 0xFFFF) == 3) { 795 newEntry.AddrShiftAmount = 12; 796 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 797 newEntry.AddrShiftAmount = 10; 798 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 799 newEntry.AddrShiftAmount = 14; 800 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 801 newEntry.AddrShiftAmount = 16; 802 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 803 newEntry.AddrShiftAmount = 18; 804 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 805 newEntry.AddrShiftAmount = 20; 806 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 807 newEntry.AddrShiftAmount = 22; 808 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 809 newEntry.AddrShiftAmount = 24; 810 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 811 newEntry.AddrShiftAmount = 26; 812 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 813 newEntry.AddrShiftAmount = 28; 814 } else { 815 fatal("Invalid Mask Pattern Detected!\n"); 816 } 817 newEntry.OffsetMask = 818 (1 << newEntry.AddrShiftAmount) - 1; 819 820 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 821 Config3Reg config3 = Config3; 822 PageGrainReg pageGrain = PageGrain; 823 int SP = 0; 824 if (bits(config3, config3.sp) == 1 && 825 bits(pageGrain, pageGrain.esp) == 1) { 826 SP = 1; 827 } 828 IndexReg index = Index; 829 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 830 }}); 831 0x06: tlbwr({{ 832 //Create PTE 833 MipsISA::PTE newEntry; 834 //Write PTE 835 newEntry.Mask = (Addr)(PageMask >> 11); 836 newEntry.VPN = (Addr)(EntryHi >> 11); 837 /* PageGrain _ ESP Config3 _ SP */ 838 if (bits(PageGrain, 28) == 0 || 839 bits(Config3, 4) == 0) { 840 // If 1KB pages are *NOT* enabled, lowest bits of 841 // the mask are 0b11 for TLB writes 842 newEntry.Mask |= 0x3; 843 // Reset bits 0 and 1 if 1KB pages are not enabled 844 newEntry.VPN &= 0xFFFFFFFC; 845 } 846 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 847 848 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 849 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 850 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 851 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 852 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 853 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 854 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 855 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 856 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 857 /* Now, compute the AddrShiftAmount and OffsetMask - 858 TLB optimizations */ 859 /* Addr Shift Amount for 1KB or larger pages */ 860 if ((newEntry.Mask & 0xFFFF) == 3){ 861 newEntry.AddrShiftAmount = 12; 862 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 863 newEntry.AddrShiftAmount = 10; 864 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 865 newEntry.AddrShiftAmount = 14; 866 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 867 newEntry.AddrShiftAmount = 16; 868 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 869 newEntry.AddrShiftAmount = 18; 870 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 871 newEntry.AddrShiftAmount = 20; 872 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 873 newEntry.AddrShiftAmount = 22; 874 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 875 newEntry.AddrShiftAmount = 24; 876 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 877 newEntry.AddrShiftAmount = 26; 878 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 879 newEntry.AddrShiftAmount = 28; 880 } else { 881 fatal("Invalid Mask Pattern Detected!\n"); 882 } 883 newEntry.OffsetMask = 884 (1 << newEntry.AddrShiftAmount) - 1; 885 886 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 887 Config3Reg config3 = Config3; 888 PageGrainReg pageGrain = PageGrain; 889 int SP = 0; 890 if (bits(config3, config3.sp) == 1 && 891 bits(pageGrain, pageGrain.esp) == 1) { 892 SP = 1; 893 } 894 IndexReg index = Index; 895 Ptr->insertAt(newEntry, Random, SP); 896 }}); 897 898 0x08: tlbp({{ 899 Config3Reg config3 = Config3; 900 PageGrainReg pageGrain = PageGrain; 901 EntryHiReg entryHi = EntryHi; 902 int tlbIndex; 903 Addr vpn; 904 if (pageGrain.esp == 1 && config3.sp ==1) { 905 vpn = EntryHi >> 11; 906 } else { 907 // Mask off lower 2 bits 908 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 909 } 910 tlbIndex = xc->tcBase()->getITBPtr()-> 911 probeEntry(vpn, entryHi.asid); 912 // Check TLB for entry matching EntryHi 913 if (tlbIndex != -1) { 914 Index = tlbIndex; 915 } else { 916 // else, set Index = 1 << 31 917 Index = (1 << 31); 918 } 919 }}); 920 } 921 format CP0Unimpl { 922 0x20: wait(); 923 } 924 default: CP0Unimpl::unknown(); 925 } 926 } 927 928 //Table A-13 MIPS32 COP1 Encoding of rs Field 929 0x1: decode RS_MSB { 930 0x0: decode RS_HI { 931 0x0: decode RS_LO { 932 format CP1Control { 933 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 934 935 0x2: cfc1({{ 936 switch (FS) { 937 case 0: 938 Rt = FIR; 939 break; 940 case 25: 941 Rt = (FCSR & 0xFE000000) >> 24 | 942 (FCSR & 0x00800000) >> 23; 943 break; 944 case 26: 945 Rt = (FCSR & 0x0003F07C); 946 break; 947 case 28: 948 Rt = (FCSR & 0x00000F80) | 949 (FCSR & 0x01000000) >> 21 | 950 (FCSR & 0x00000003); 951 break; 952 case 31: 953 Rt = FCSR; 954 break; 955 default: 956 warn("FP Control Value (%d) Not Valid"); 957 } 958 }}); 959 960 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>; }}); 961 962 0x4: mtc1({{ Fs.uw = Rt.uw; }}); 963 964 0x6: ctc1({{ 965 switch (FS) { 966 case 25: 967 FCSR = (Rt.uw<7:1> << 25) | // move 31-25 968 (FCSR & 0x01000000) | // bit 24 969 (FCSR & 0x004FFFFF); // bit 22-0 970 break; 971 case 26: 972 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 973 Rt.uw<17:12> << 12 | // bit 17-12 974 (FCSR & 0x00000F80) << 7 | // bit 11-7 975 Rt.uw<6:2> << 2 | // bit 6-2 976 (FCSR & 0x00000002); // bit 1-0 977 break; 978 case 28: 979 FCSR = (FCSR & 0xFE000000) | // move 31-25 980 Rt.uw<2:2> << 24 | // bit 24 981 (FCSR & 0x00FFF000) << 23 | // bit 23-12 982 Rt.uw<11:7> << 7 | // bit 24 983 (FCSR & 0x000007E) | 984 Rt.uw<1:0>; // bit 22-0 985 break; 986 case 31: 987 FCSR = Rt.uw; 988 break; 989 990 default: 991 panic("FP Control Value (%d) " 992 "Not Available. Ignoring Access " 993 "to Floating Control Status " 994 "Register", FS); 995 } 996 }}); 997 998 0x7: mthc1({{ 999 uint64_t fs_hi = Rt.uw; 1000 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 1001 Fs.ud = (fs_hi << 32) | fs_lo; 1002 }}); 1003 1004 } 1005 format CP1Unimpl { 1006 0x1: dmfc1(); 1007 0x5: dmtc1(); 1008 } 1009 } 1010 1011 0x1: decode RS_LO { 1012 0x0: decode ND { 1013 format Branch { 1014 0x0: decode TF { 1015 0x0: bc1f({{ 1016 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1017 }}); 1018 0x1: bc1t({{ 1019 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1020 }}); 1021 } 1022 0x1: decode TF { 1023 0x0: bc1fl({{ 1024 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1025 }}, Likely); 1026 0x1: bc1tl({{ 1027 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1028 }}, Likely); 1029 } 1030 } 1031 } 1032 format CP1Unimpl { 1033 0x1: bc1any2(); 1034 0x2: bc1any4(); 1035 default: unknown(); 1036 } 1037 } 1038 } 1039 1040 0x1: decode RS_HI { 1041 0x2: decode RS_LO { 1042 //Table A-14 MIPS32 COP1 Encoding of Function Field When 1043 //rs=S (( single-precision floating point)) 1044 0x0: decode FUNCTION_HI { 1045 0x0: decode FUNCTION_LO { 1046 format FloatOp { 1047 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf; }}); 1048 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf; }}); 1049 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf; }}); 1050 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf; }}); 1051 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf); }}); 1052 0x5: abs_s({{ Fd.sf = fabs(Fs.sf); }}); 1053 0x7: neg_s({{ Fd.sf = -Fs.sf; }}); 1054 } 1055 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf; }}); 1056 } 1057 0x1: decode FUNCTION_LO { 1058 format FloatConvertOp { 1059 0x0: round_l_s({{ val = Fs.sf; }}, 1060 ToLong, Round); 1061 0x1: trunc_l_s({{ val = Fs.sf; }}, 1062 ToLong, Trunc); 1063 0x2: ceil_l_s({{ val = Fs.sf;}}, 1064 ToLong, Ceil); 1065 0x3: floor_l_s({{ val = Fs.sf; }}, 1066 ToLong, Floor); 1067 0x4: round_w_s({{ val = Fs.sf; }}, 1068 ToWord, Round); 1069 0x5: trunc_w_s({{ val = Fs.sf; }}, 1070 ToWord, Trunc); 1071 0x6: ceil_w_s({{ val = Fs.sf; }}, 1072 ToWord, Ceil); 1073 0x7: floor_w_s({{ val = Fs.sf; }}, 1074 ToWord, Floor); 1075 } 1076 } 1077 1078 0x2: decode FUNCTION_LO { 1079 0x1: decode MOVCF { 1080 format BasicOp { 1081 0x0: movf_s({{ 1082 Fd = (getCondCode(FCSR,CC) == 0) ? 1083 Fs : Fd; 1084 }}); 1085 0x1: movt_s({{ 1086 Fd = (getCondCode(FCSR,CC) == 1) ? 1087 Fs : Fd; 1088 }}); 1089 } 1090 } 1091 1092 format BasicOp { 1093 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1094 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1095 } 1096 1097 format FloatOp { 1098 0x5: recip_s({{ Fd = 1 / Fs; }}); 1099 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 1100 } 1101 format CP1Unimpl { 1102 default: unknown(); 1103 } 1104 } 1105 0x3: CP1Unimpl::unknown(); 1106 1107 0x4: decode FUNCTION_LO { 1108 format FloatConvertOp { 1109 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 1110 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 1111 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 1112 } 1113 1114 0x6: FloatOp::cvt_ps_s({{ 1115 Fd.ud = (uint64_t) Fs.uw << 32 | 1116 (uint64_t) Ft.uw; 1117 }}); 1118 format CP1Unimpl { 1119 default: unknown(); 1120 } 1121 } 1122 0x5: CP1Unimpl::unknown(); 1123 1124 0x6: decode FUNCTION_LO { 1125 format FloatCompareOp { 1126 0x0: c_f_s({{ cond = 0; }}, 1127 SinglePrecision, UnorderedFalse); 1128 0x1: c_un_s({{ cond = 0; }}, 1129 SinglePrecision, UnorderedTrue); 1130 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 1131 UnorderedFalse); 1132 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 1133 UnorderedTrue); 1134 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 1135 UnorderedFalse); 1136 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 1137 UnorderedTrue); 1138 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 1139 UnorderedFalse); 1140 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 1141 UnorderedTrue); 1142 } 1143 } 1144 1145 0x7: decode FUNCTION_LO { 1146 format FloatCompareOp { 1147 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1148 UnorderedFalse, QnanException); 1149 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1150 UnorderedTrue, QnanException); 1151 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf); }}, 1152 UnorderedFalse, QnanException); 1153 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 1154 UnorderedTrue, QnanException); 1155 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 1156 UnorderedFalse, QnanException); 1157 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 1158 UnorderedTrue, QnanException); 1159 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 1160 UnorderedFalse, QnanException); 1161 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 1162 UnorderedTrue, QnanException); 1163 } 1164 } 1165 } 1166 1167 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1168 //rs=D 1169 0x1: decode FUNCTION_HI { 1170 0x0: decode FUNCTION_LO { 1171 format FloatOp { 1172 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 1173 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 1174 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 1175 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 1176 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 1177 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 1178 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 1179 } 1180 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 1181 } 1182 1183 0x1: decode FUNCTION_LO { 1184 format FloatConvertOp { 1185 0x0: round_l_d({{ val = Fs.df; }}, 1186 ToLong, Round); 1187 0x1: trunc_l_d({{ val = Fs.df; }}, 1188 ToLong, Trunc); 1189 0x2: ceil_l_d({{ val = Fs.df; }}, 1190 ToLong, Ceil); 1191 0x3: floor_l_d({{ val = Fs.df; }}, 1192 ToLong, Floor); 1193 0x4: round_w_d({{ val = Fs.df; }}, 1194 ToWord, Round); 1195 0x5: trunc_w_d({{ val = Fs.df; }}, 1196 ToWord, Trunc); 1197 0x6: ceil_w_d({{ val = Fs.df; }}, 1198 ToWord, Ceil); 1199 0x7: floor_w_d({{ val = Fs.df; }}, 1200 ToWord, Floor); 1201 } 1202 } 1203 1204 0x2: decode FUNCTION_LO { 1205 0x1: decode MOVCF { 1206 format BasicOp { 1207 0x0: movf_d({{ 1208 Fd.df = (getCondCode(FCSR,CC) == 0) ? 1209 Fs.df : Fd.df; 1210 }}); 1211 0x1: movt_d({{ 1212 Fd.df = (getCondCode(FCSR,CC) == 1) ? 1213 Fs.df : Fd.df; 1214 }}); 1215 } 1216 } 1217 1218 format BasicOp { 1219 0x2: movz_d({{ 1220 Fd.df = (Rt == 0) ? Fs.df : Fd.df; 1221 }}); 1222 0x3: movn_d({{ 1223 Fd.df = (Rt != 0) ? Fs.df : Fd.df; 1224 }}); 1225 } 1226 1227 format FloatOp { 1228 0x5: recip_d({{ Fd.df = 1 / Fs.df; }}); 1229 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df); }}); 1230 } 1231 format CP1Unimpl { 1232 default: unknown(); 1233 } 1234 1235 } 1236 0x4: decode FUNCTION_LO { 1237 format FloatConvertOp { 1238 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 1239 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 1240 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 1241 } 1242 default: CP1Unimpl::unknown(); 1243 } 1244 1245 0x6: decode FUNCTION_LO { 1246 format FloatCompareOp { 1247 0x0: c_f_d({{ cond = 0; }}, 1248 DoublePrecision, UnorderedFalse); 1249 0x1: c_un_d({{ cond = 0; }}, 1250 DoublePrecision, UnorderedTrue); 1251 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 1252 UnorderedFalse); 1253 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 1254 UnorderedTrue); 1255 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 1256 UnorderedFalse); 1257 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 1258 UnorderedTrue); 1259 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 1260 UnorderedFalse); 1261 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 1262 UnorderedTrue); 1263 } 1264 } 1265 1266 0x7: decode FUNCTION_LO { 1267 format FloatCompareOp { 1268 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1269 UnorderedFalse, QnanException); 1270 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1271 UnorderedTrue, QnanException); 1272 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 1273 UnorderedFalse, QnanException); 1274 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 1275 UnorderedTrue, QnanException); 1276 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 1277 UnorderedFalse, QnanException); 1278 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 1279 UnorderedTrue, QnanException); 1280 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 1281 UnorderedFalse, QnanException); 1282 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 1283 UnorderedTrue, QnanException); 1284 } 1285 } 1286 default: CP1Unimpl::unknown(); 1287 } 1288 0x2: CP1Unimpl::unknown(); 1289 0x3: CP1Unimpl::unknown(); 1290 0x7: CP1Unimpl::unknown(); 1291 1292 //Table A-16 MIPS32 COP1 Encoding of Function 1293 //Field When rs=W 1294 0x4: decode FUNCTION { 1295 format FloatConvertOp { 1296 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 1297 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 1298 0x26: CP1Unimpl::cvt_ps_w(); 1299 } 1300 default: CP1Unimpl::unknown(); 1301 } 1302 1303 //Table A-16 MIPS32 COP1 Encoding of Function Field 1304 //When rs=L1 1305 //Note: "1. Format type L is legal only if 64-bit 1306 //floating point operations are enabled." 1307 0x5: decode FUNCTION_HI { 1308 format FloatConvertOp { 1309 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 1310 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 1311 0x26: CP1Unimpl::cvt_ps_l(); 1312 } 1313 default: CP1Unimpl::unknown(); 1314 } 1315 1316 //Table A-17 MIPS64 COP1 Encoding of Function Field 1317 //When rs=PS1 1318 //Note: "1. Format type PS is legal only if 64-bit 1319 //floating point operations are enabled. " 1320 0x6: decode FUNCTION_HI { 1321 0x0: decode FUNCTION_LO { 1322 format Float64Op { 1323 0x0: add_ps({{ 1324 Fd1.sf = Fs1.sf + Ft2.sf; 1325 Fd2.sf = Fs2.sf + Ft2.sf; 1326 }}); 1327 0x1: sub_ps({{ 1328 Fd1.sf = Fs1.sf - Ft2.sf; 1329 Fd2.sf = Fs2.sf - Ft2.sf; 1330 }}); 1331 0x2: mul_ps({{ 1332 Fd1.sf = Fs1.sf * Ft2.sf; 1333 Fd2.sf = Fs2.sf * Ft2.sf; 1334 }}); 1335 0x5: abs_ps({{ 1336 Fd1.sf = fabs(Fs1.sf); 1337 Fd2.sf = fabs(Fs2.sf); 1338 }}); 1339 0x6: mov_ps({{ 1340 Fd1.sf = Fs1.sf; 1341 Fd2.sf = Fs2.sf; 1342 }}); 1343 0x7: neg_ps({{ 1344 Fd1.sf = -(Fs1.sf); 1345 Fd2.sf = -(Fs2.sf); 1346 }}); 1347 default: CP1Unimpl::unknown(); 1348 } 1349 } 1350 0x1: CP1Unimpl::unknown(); 1351 0x2: decode FUNCTION_LO { 1352 0x1: decode MOVCF { 1353 format Float64Op { 1354 0x0: movf_ps({{ 1355 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1356 Fs1 : Fd1; 1357 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1358 Fs2 : Fd2; 1359 }}); 1360 0x1: movt_ps({{ 1361 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1362 Fs1 : Fd1; 1363 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1364 Fs2 : Fd2; 1365 }}); 1366 } 1367 } 1368 1369 format Float64Op { 1370 0x2: movz_ps({{ 1371 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1372 Fs1 : Fd1; 1373 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1374 Fs2 : Fd2; 1375 }}); 1376 0x3: movn_ps({{ 1377 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1378 Fs1 : Fd1; 1379 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1380 Fs2 : Fd2; 1381 }}); 1382 } 1383 default: CP1Unimpl::unknown(); 1384 } 1385 0x3: CP1Unimpl::unknown(); 1386 0x4: decode FUNCTION_LO { 1387 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 1388 default: CP1Unimpl::unknown(); 1389 } 1390 1391 0x5: decode FUNCTION_LO { 1392 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 1393 format Float64Op { 1394 0x4: pll({{ 1395 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft1.uw; 1396 }}); 1397 0x5: plu({{ 1398 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft2.uw; 1399 }}); 1400 0x6: pul({{ 1401 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft1.uw; 1402 }}); 1403 0x7: puu({{ 1404 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft2.uw; 1405 }}); 1406 } 1407 default: CP1Unimpl::unknown(); 1408 } 1409 1410 0x6: decode FUNCTION_LO { 1411 format FloatPSCompareOp { 1412 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1413 UnorderedFalse); 1414 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1415 UnorderedTrue); 1416 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1417 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1418 UnorderedFalse); 1419 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1420 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1421 UnorderedTrue); 1422 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1423 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1424 UnorderedFalse); 1425 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 1426 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1427 UnorderedTrue); 1428 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 1429 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1430 UnorderedFalse); 1431 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1432 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1433 UnorderedTrue); 1434 } 1435 } 1436 1437 0x7: decode FUNCTION_LO { 1438 format FloatPSCompareOp { 1439 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1440 UnorderedFalse, QnanException); 1441 0x1: c_ngle_ps({{ cond1 = 0; }}, 1442 {{ cond2 = 0; }}, 1443 UnorderedTrue, QnanException); 1444 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1445 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1446 UnorderedFalse, QnanException); 1447 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1448 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1449 UnorderedTrue, QnanException); 1450 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1451 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1452 UnorderedFalse, QnanException); 1453 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1454 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1455 UnorderedTrue, QnanException); 1456 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1457 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1458 UnorderedFalse, QnanException); 1459 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1460 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1461 UnorderedTrue, QnanException); 1462 } 1463 } 1464 } 1465 } 1466 default: CP1Unimpl::unknown(); 1467 } 1468 } 1469 1470 //Table A-19 MIPS32 COP2 Encoding of rs Field 1471 0x2: decode RS_MSB { 1472 format CP2Unimpl { 1473 0x0: decode RS_HI { 1474 0x0: decode RS_LO { 1475 0x0: mfc2(); 1476 0x2: cfc2(); 1477 0x3: mfhc2(); 1478 0x4: mtc2(); 1479 0x6: ctc2(); 1480 0x7: mftc2(); 1481 default: unknown(); 1482 } 1483 1484 0x1: decode ND { 1485 0x0: decode TF { 1486 0x0: bc2f(); 1487 0x1: bc2t(); 1488 default: unknown(); 1489 } 1490 1491 0x1: decode TF { 1492 0x0: bc2fl(); 1493 0x1: bc2tl(); 1494 default: unknown(); 1495 } 1496 default: unknown(); 1497 1498 } 1499 default: unknown(); 1500 } 1501 default: unknown(); 1502 } 1503 } 1504 1505 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1506 //Note: "COP1X instructions are legal only if 64-bit floating point 1507 //operations are enabled." 1508 0x3: decode FUNCTION_HI { 1509 0x0: decode FUNCTION_LO { 1510 format LoadIndexedMemory { 1511 0x0: lwxc1({{ Fd.uw = Mem.uw; }}); 1512 0x1: ldxc1({{ Fd.ud = Mem.ud; }}); 1513 0x5: luxc1({{ Fd.ud = Mem.ud; }}, 1514 {{ EA = (Rs + Rt) & ~7; }}); 1515 } 1516 } 1517 1518 0x1: decode FUNCTION_LO { 1519 format StoreIndexedMemory { 1520 0x0: swxc1({{ Mem.uw = Fs.uw; }}); 1521 0x1: sdxc1({{ Mem.ud = Fs.ud; }}); 1522 0x5: suxc1({{ Mem.ud = Fs.ud; }}, 1523 {{ EA = (Rs + Rt) & ~7; }}); 1524 } 1525 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1526 } 1527 1528 0x3: decode FUNCTION_LO { 1529 0x6: Float64Op::alnv_ps({{ 1530 if (Rs<2:0> == 0) { 1531 Fd.ud = Fs.ud; 1532 } else if (Rs<2:0> == 4) { 1533#if BYTE_ORDER == BIG_ENDIAN 1534 Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>; 1535#elif BYTE_ORDER == LITTLE_ENDIAN 1536 Fd.ud = Ft.ud<31:0> << 32 | Fs.ud<63:32>; 1537#endif 1538 } else { 1539 Fd.ud = Fd.ud; 1540 } 1541 }}); 1542 } 1543 1544 format FloatAccOp { 1545 0x4: decode FUNCTION_LO { 1546 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 1547 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 1548 0x6: madd_ps({{ 1549 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 1550 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 1551 }}); 1552 } 1553 1554 0x5: decode FUNCTION_LO { 1555 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 1556 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 1557 0x6: msub_ps({{ 1558 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 1559 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 1560 }}); 1561 } 1562 1563 0x6: decode FUNCTION_LO { 1564 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1565 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 1566 0x6: nmadd_ps({{ 1567 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 1568 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 1569 }}); 1570 } 1571 1572 0x7: decode FUNCTION_LO { 1573 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1574 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 1575 0x6: nmsub_ps({{ 1576 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 1577 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 1578 }}); 1579 } 1580 } 1581 } 1582 1583 format Branch { 1584 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 1585 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 1586 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 1587 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 1588 } 1589 } 1590 1591 0x3: decode OPCODE_LO { 1592 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1593 0x4: decode FUNCTION_HI { 1594 0x0: decode FUNCTION_LO { 1595 0x2: IntOp::mul({{ 1596 int64_t temp1 = Rs.sd * Rt.sd; 1597 Rd.sw = temp1<31:0>; 1598 }}, IntMultOp); 1599 1600 format HiLoRdSelValOp { 1601 0x0: madd({{ 1602 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1603 (Rs.sd * Rt.sd); 1604 }}, IntMultOp); 1605 0x1: maddu({{ 1606 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1607 (Rs.ud * Rt.ud); 1608 }}, IntMultOp); 1609 0x4: msub({{ 1610 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1611 (Rs.sd * Rt.sd); 1612 }}, IntMultOp); 1613 0x5: msubu({{ 1614 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1615 (Rs.ud * Rt.ud); 1616 }}, IntMultOp); 1617 } 1618 } 1619 1620 0x4: decode FUNCTION_LO { 1621 format BasicOp { 1622 0x0: clz({{ 1623 int cnt = 32; 1624 for (int idx = 31; idx >= 0; idx--) { 1625 if (Rs<idx:idx> == 1) { 1626 cnt = 31 - idx; 1627 break; 1628 } 1629 } 1630 Rd.uw = cnt; 1631 }}); 1632 0x1: clo({{ 1633 int cnt = 32; 1634 for (int idx = 31; idx >= 0; idx--) { 1635 if (Rs<idx:idx> == 0) { 1636 cnt = 31 - idx; 1637 break; 1638 } 1639 } 1640 Rd.uw = cnt; 1641 }}); 1642 } 1643 } 1644 1645 0x7: decode FUNCTION_LO { 1646 0x7: FailUnimpl::sdbbp(); 1647 } 1648 } 1649 1650 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1651 //of the Architecture 1652 0x7: decode FUNCTION_HI { 1653 0x0: decode FUNCTION_LO { 1654 format BasicOp { 1655 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 1656 0x4: ins({{ 1657 Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1658 bits(Rs.uw, MSB-LSB, 0) << LSB | 1659 bits(Rt.uw, LSB-1, 0); 1660 }}); 1661 } 1662 } 1663 1664 0x1: decode FUNCTION_LO { 1665 format MT_Control { 1666 0x0: fork({{ 1667 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1668 }}, UserMode); 1669 0x1: yield({{ 1670 Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, 1671 YQMask); 1672 }}, UserMode); 1673 } 1674 1675 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1676 0x2: decode OP_HI { 1677 0x0: decode OP_LO { 1678 format LoadIndexedMemory { 1679 0x0: lwx({{ Rd.sw = Mem.sw; }}); 1680 0x4: lhx({{ Rd.sw = Mem.sh; }}); 1681 0x6: lbux({{ Rd.uw = Mem.ub; }}); 1682 } 1683 } 1684 } 1685 0x4: DspIntOp::insv({{ 1686 int pos = dspctl<5:0>; 1687 int size = dspctl<12:7> - 1; 1688 Rt.uw = insertBits(Rt.uw, pos+size, 1689 pos, Rs.uw<size:0>); 1690 }}); 1691 } 1692 1693 0x2: decode FUNCTION_LO { 1694 1695 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1696 //(DSP ASE MANUAL) 1697 0x0: decode OP_HI { 1698 0x0: decode OP_LO { 1699 format DspIntOp { 1700 0x0: addu_qb({{ 1701 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1702 NOSATURATE, UNSIGNED, &dspctl); 1703 }}); 1704 0x1: subu_qb({{ 1705 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1706 NOSATURATE, UNSIGNED, &dspctl); 1707 }}); 1708 0x4: addu_s_qb({{ 1709 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1710 SATURATE, UNSIGNED, &dspctl); 1711 }}); 1712 0x5: subu_s_qb({{ 1713 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1714 SATURATE, UNSIGNED, &dspctl); 1715 }}); 1716 0x6: muleu_s_ph_qbl({{ 1717 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1718 MODE_L, &dspctl); 1719 }}, IntMultOp); 1720 0x7: muleu_s_ph_qbr({{ 1721 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1722 MODE_R, &dspctl); 1723 }}, IntMultOp); 1724 } 1725 } 1726 0x1: decode OP_LO { 1727 format DspIntOp { 1728 0x0: addu_ph({{ 1729 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1730 NOSATURATE, UNSIGNED, &dspctl); 1731 }}); 1732 0x1: subu_ph({{ 1733 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1734 NOSATURATE, UNSIGNED, &dspctl); 1735 }}); 1736 0x2: addq_ph({{ 1737 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1738 NOSATURATE, SIGNED, &dspctl); 1739 }}); 1740 0x3: subq_ph({{ 1741 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1742 NOSATURATE, SIGNED, &dspctl); 1743 }}); 1744 0x4: addu_s_ph({{ 1745 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1746 SATURATE, UNSIGNED, &dspctl); 1747 }}); 1748 0x5: subu_s_ph({{ 1749 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1750 SATURATE, UNSIGNED, &dspctl); 1751 }}); 1752 0x6: addq_s_ph({{ 1753 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1754 SATURATE, SIGNED, &dspctl); 1755 }}); 1756 0x7: subq_s_ph({{ 1757 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1758 SATURATE, SIGNED, &dspctl); 1759 }}); 1760 } 1761 } 1762 0x2: decode OP_LO { 1763 format DspIntOp { 1764 0x0: addsc({{ 1765 int64_t dresult; 1766 dresult = Rs.ud + Rt.ud; 1767 Rd.sw = dresult<31:0>; 1768 dspctl = insertBits(dspctl, 13, 13, 1769 dresult<32:32>); 1770 }}); 1771 0x1: addwc({{ 1772 int64_t dresult; 1773 dresult = Rs.sd + Rt.sd + dspctl<13:13>; 1774 Rd.sw = dresult<31:0>; 1775 if (dresult<32:32> != dresult<31:31>) 1776 dspctl = insertBits(dspctl, 20, 20, 1); 1777 }}); 1778 0x2: modsub({{ 1779 Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : 1780 Rs.sw - Rt.sw<7:0>; 1781 }}); 1782 0x4: raddu_w_qb({{ 1783 Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 1784 Rs.uw<15:8> + Rs.uw<7:0>; 1785 }}); 1786 0x6: addq_s_w({{ 1787 Rd.sw = dspAdd(Rs.sw, Rt.sw, SIMD_FMT_W, 1788 SATURATE, SIGNED, &dspctl); 1789 }}); 1790 0x7: subq_s_w({{ 1791 Rd.sw = dspSub(Rs.sw, Rt.sw, SIMD_FMT_W, 1792 SATURATE, SIGNED, &dspctl); 1793 }}); 1794 } 1795 } 1796 0x3: decode OP_LO { 1797 format DspIntOp { 1798 0x4: muleq_s_w_phl({{ 1799 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1800 MODE_L, &dspctl); 1801 }}, IntMultOp); 1802 0x5: muleq_s_w_phr({{ 1803 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1804 MODE_R, &dspctl); 1805 }}, IntMultOp); 1806 0x6: mulq_s_ph({{ 1807 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1808 SATURATE, NOROUND, &dspctl); 1809 }}, IntMultOp); 1810 0x7: mulq_rs_ph({{ 1811 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1812 SATURATE, ROUND, &dspctl); 1813 }}, IntMultOp); 1814 } 1815 } 1816 } 1817 1818 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1819 //(DSP ASE MANUAL) 1820 0x1: decode OP_HI { 1821 0x0: decode OP_LO { 1822 format DspIntOp { 1823 0x0: cmpu_eq_qb({{ 1824 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1825 UNSIGNED, CMP_EQ, &dspctl); 1826 }}); 1827 0x1: cmpu_lt_qb({{ 1828 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1829 UNSIGNED, CMP_LT, &dspctl); 1830 }}); 1831 0x2: cmpu_le_qb({{ 1832 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1833 UNSIGNED, CMP_LE, &dspctl); 1834 }}); 1835 0x3: pick_qb({{ 1836 Rd.uw = dspPick(Rs.uw, Rt.uw, 1837 SIMD_FMT_QB, &dspctl); 1838 }}); 1839 0x4: cmpgu_eq_qb({{ 1840 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1841 UNSIGNED, CMP_EQ ); 1842 }}); 1843 0x5: cmpgu_lt_qb({{ 1844 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1845 UNSIGNED, CMP_LT); 1846 }}); 1847 0x6: cmpgu_le_qb({{ 1848 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1849 UNSIGNED, CMP_LE); 1850 }}); 1851 } 1852 } 1853 0x1: decode OP_LO { 1854 format DspIntOp { 1855 0x0: cmp_eq_ph({{ 1856 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1857 SIGNED, CMP_EQ, &dspctl); 1858 }}); 1859 0x1: cmp_lt_ph({{ 1860 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1861 SIGNED, CMP_LT, &dspctl); 1862 }}); 1863 0x2: cmp_le_ph({{ 1864 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1865 SIGNED, CMP_LE, &dspctl); 1866 }}); 1867 0x3: pick_ph({{ 1868 Rd.uw = dspPick(Rs.uw, Rt.uw, 1869 SIMD_FMT_PH, &dspctl); 1870 }}); 1871 0x4: precrq_qb_ph({{ 1872 Rd.uw = Rs.uw<31:24> << 24 | 1873 Rs.uw<15:8> << 16 | 1874 Rt.uw<31:24> << 8 | 1875 Rt.uw<15:8>; 1876 }}); 1877 0x5: precr_qb_ph({{ 1878 Rd.uw = Rs.uw<23:16> << 24 | 1879 Rs.uw<7:0> << 16 | 1880 Rt.uw<23:16> << 8 | 1881 Rt.uw<7:0>; 1882 }}); 1883 0x6: packrl_ph({{ 1884 Rd.uw = dspPack(Rs.uw, Rt.uw, SIMD_FMT_PH); 1885 }}); 1886 0x7: precrqu_s_qb_ph({{ 1887 Rd.uw = dspPrecrqu(Rs.uw, Rt.uw, &dspctl); 1888 }}); 1889 } 1890 } 1891 0x2: decode OP_LO { 1892 format DspIntOp { 1893 0x4: precrq_ph_w({{ 1894 Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; 1895 }}); 1896 0x5: precrq_rs_ph_w({{ 1897 Rd.uw = dspPrecrq(Rs.uw, Rt.uw, 1898 SIMD_FMT_W, &dspctl); 1899 }}); 1900 } 1901 } 1902 0x3: decode OP_LO { 1903 format DspIntOp { 1904 0x0: cmpgdu_eq_qb({{ 1905 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1906 UNSIGNED, CMP_EQ, &dspctl); 1907 }}); 1908 0x1: cmpgdu_lt_qb({{ 1909 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1910 UNSIGNED, CMP_LT, &dspctl); 1911 }}); 1912 0x2: cmpgdu_le_qb({{ 1913 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1914 UNSIGNED, CMP_LE, &dspctl); 1915 }}); 1916 0x6: precr_sra_ph_w({{ 1917 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1918 SIMD_FMT_W, NOROUND); 1919 }}); 1920 0x7: precr_sra_r_ph_w({{ 1921 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1922 SIMD_FMT_W, ROUND); 1923 }}); 1924 } 1925 } 1926 } 1927 1928 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1929 //(DSP ASE MANUAL) 1930 0x2: decode OP_HI { 1931 0x0: decode OP_LO { 1932 format DspIntOp { 1933 0x1: absq_s_qb({{ 1934 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_QB, &dspctl); 1935 }}); 1936 0x2: repl_qb({{ 1937 Rd.uw = RS_RT<7:0> << 24 | 1938 RS_RT<7:0> << 16 | 1939 RS_RT<7:0> << 8 | 1940 RS_RT<7:0>; 1941 }}); 1942 0x3: replv_qb({{ 1943 Rd.sw = Rt.uw<7:0> << 24 | 1944 Rt.uw<7:0> << 16 | 1945 Rt.uw<7:0> << 8 | 1946 Rt.uw<7:0>; 1947 }}); 1948 0x4: precequ_ph_qbl({{ 1949 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1950 SIMD_FMT_PH, SIGNED, MODE_L); 1951 }}); 1952 0x5: precequ_ph_qbr({{ 1953 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1954 SIMD_FMT_PH, SIGNED, MODE_R); 1955 }}); 1956 0x6: precequ_ph_qbla({{ 1957 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1958 SIMD_FMT_PH, SIGNED, MODE_LA); 1959 }}); 1960 0x7: precequ_ph_qbra({{ 1961 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1962 SIMD_FMT_PH, SIGNED, MODE_RA); 1963 }}); 1964 } 1965 } 1966 0x1: decode OP_LO { 1967 format DspIntOp { 1968 0x1: absq_s_ph({{ 1969 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_PH, &dspctl); 1970 }}); 1971 0x2: repl_ph({{ 1972 Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 1973 (sext<10>(RS_RT))<15:0>; 1974 }}); 1975 0x3: replv_ph({{ 1976 Rd.uw = Rt.uw<15:0> << 16 | 1977 Rt.uw<15:0>; 1978 }}); 1979 0x4: preceq_w_phl({{ 1980 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1981 SIMD_FMT_W, SIGNED, MODE_L); 1982 }}); 1983 0x5: preceq_w_phr({{ 1984 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1985 SIMD_FMT_W, SIGNED, MODE_R); 1986 }}); 1987 } 1988 } 1989 0x2: decode OP_LO { 1990 format DspIntOp { 1991 0x1: absq_s_w({{ 1992 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_W, &dspctl); 1993 }}); 1994 } 1995 } 1996 0x3: decode OP_LO { 1997 0x3: IntOp::bitrev({{ 1998 Rd.uw = bitrev( Rt.uw<15:0> ); 1999 }}); 2000 format DspIntOp { 2001 0x4: preceu_ph_qbl({{ 2002 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2003 UNSIGNED, SIMD_FMT_PH, 2004 UNSIGNED, MODE_L); 2005 }}); 2006 0x5: preceu_ph_qbr({{ 2007 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2008 UNSIGNED, SIMD_FMT_PH, 2009 UNSIGNED, MODE_R ); 2010 }}); 2011 0x6: preceu_ph_qbla({{ 2012 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2013 UNSIGNED, SIMD_FMT_PH, 2014 UNSIGNED, MODE_LA ); 2015 }}); 2016 0x7: preceu_ph_qbra({{ 2017 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2018 UNSIGNED, SIMD_FMT_PH, 2019 UNSIGNED, MODE_RA); 2020 }}); 2021 } 2022 } 2023 } 2024 2025 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 2026 //(DSP ASE MANUAL) 2027 0x3: decode OP_HI { 2028 0x0: decode OP_LO { 2029 format DspIntOp { 2030 0x0: shll_qb({{ 2031 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_QB, 2032 NOSATURATE, UNSIGNED, &dspctl); 2033 }}); 2034 0x1: shrl_qb({{ 2035 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_QB, 2036 UNSIGNED); 2037 }}); 2038 0x2: shllv_qb({{ 2039 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_QB, 2040 NOSATURATE, UNSIGNED, &dspctl); 2041 }}); 2042 0x3: shrlv_qb({{ 2043 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_QB, 2044 UNSIGNED); 2045 }}); 2046 0x4: shra_qb({{ 2047 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2048 NOROUND, SIGNED, &dspctl); 2049 }}); 2050 0x5: shra_r_qb({{ 2051 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2052 ROUND, SIGNED, &dspctl); 2053 }}); 2054 0x6: shrav_qb({{ 2055 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2056 NOROUND, SIGNED, &dspctl); 2057 }}); 2058 0x7: shrav_r_qb({{ 2059 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2060 ROUND, SIGNED, &dspctl); 2061 }}); 2062 } 2063 } 2064 0x1: decode OP_LO { 2065 format DspIntOp { 2066 0x0: shll_ph({{ 2067 Rd.uw = dspShll(Rt.uw, RS, SIMD_FMT_PH, 2068 NOSATURATE, SIGNED, &dspctl); 2069 }}); 2070 0x1: shra_ph({{ 2071 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2072 NOROUND, SIGNED, &dspctl); 2073 }}); 2074 0x2: shllv_ph({{ 2075 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2076 NOSATURATE, SIGNED, &dspctl); 2077 }}); 2078 0x3: shrav_ph({{ 2079 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2080 NOROUND, SIGNED, &dspctl); 2081 }}); 2082 0x4: shll_s_ph({{ 2083 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_PH, 2084 SATURATE, SIGNED, &dspctl); 2085 }}); 2086 0x5: shra_r_ph({{ 2087 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2088 ROUND, SIGNED, &dspctl); 2089 }}); 2090 0x6: shllv_s_ph({{ 2091 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2092 SATURATE, SIGNED, &dspctl); 2093 }}); 2094 0x7: shrav_r_ph({{ 2095 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2096 ROUND, SIGNED, &dspctl); 2097 }}); 2098 } 2099 } 2100 0x2: decode OP_LO { 2101 format DspIntOp { 2102 0x4: shll_s_w({{ 2103 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_W, 2104 SATURATE, SIGNED, &dspctl); 2105 }}); 2106 0x5: shra_r_w({{ 2107 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_W, 2108 ROUND, SIGNED, &dspctl); 2109 }}); 2110 0x6: shllv_s_w({{ 2111 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_W, 2112 SATURATE, SIGNED, &dspctl); 2113 }}); 2114 0x7: shrav_r_w({{ 2115 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_W, 2116 ROUND, SIGNED, &dspctl); 2117 }}); 2118 } 2119 } 2120 0x3: decode OP_LO { 2121 format DspIntOp { 2122 0x1: shrl_ph({{ 2123 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_PH, 2124 UNSIGNED); 2125 }}); 2126 0x3: shrlv_ph({{ 2127 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_PH, 2128 UNSIGNED); 2129 }}); 2130 } 2131 } 2132 } 2133 } 2134 2135 0x3: decode FUNCTION_LO { 2136 2137 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2138 //(DSP ASE Rev2 Manual) 2139 0x0: decode OP_HI { 2140 0x0: decode OP_LO { 2141 format DspIntOp { 2142 0x0: adduh_qb({{ 2143 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2144 NOROUND, UNSIGNED); 2145 }}); 2146 0x1: subuh_qb({{ 2147 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2148 NOROUND, UNSIGNED); 2149 }}); 2150 0x2: adduh_r_qb({{ 2151 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2152 ROUND, UNSIGNED); 2153 }}); 2154 0x3: subuh_r_qb({{ 2155 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2156 ROUND, UNSIGNED); 2157 }}); 2158 } 2159 } 2160 0x1: decode OP_LO { 2161 format DspIntOp { 2162 0x0: addqh_ph({{ 2163 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2164 NOROUND, SIGNED); 2165 }}); 2166 0x1: subqh_ph({{ 2167 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2168 NOROUND, SIGNED); 2169 }}); 2170 0x2: addqh_r_ph({{ 2171 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2172 ROUND, SIGNED); 2173 }}); 2174 0x3: subqh_r_ph({{ 2175 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2176 ROUND, SIGNED); 2177 }}); 2178 0x4: mul_ph({{ 2179 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2180 NOSATURATE, &dspctl); 2181 }}, IntMultOp); 2182 0x6: mul_s_ph({{ 2183 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2184 SATURATE, &dspctl); 2185 }}, IntMultOp); 2186 } 2187 } 2188 0x2: decode OP_LO { 2189 format DspIntOp { 2190 0x0: addqh_w({{ 2191 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2192 NOROUND, SIGNED); 2193 }}); 2194 0x1: subqh_w({{ 2195 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2196 NOROUND, SIGNED); 2197 }}); 2198 0x2: addqh_r_w({{ 2199 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2200 ROUND, SIGNED); 2201 }}); 2202 0x3: subqh_r_w({{ 2203 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2204 ROUND, SIGNED); 2205 }}); 2206 0x6: mulq_s_w({{ 2207 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2208 SATURATE, NOROUND, &dspctl); 2209 }}, IntMultOp); 2210 0x7: mulq_rs_w({{ 2211 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2212 SATURATE, ROUND, &dspctl); 2213 }}, IntMultOp); 2214 } 2215 } 2216 } 2217 } 2218 2219 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2220 0x4: decode SA { 2221 format BasicOp { 2222 0x02: wsbh({{ 2223 Rd.uw = Rt.uw<23:16> << 24 | 2224 Rt.uw<31:24> << 16 | 2225 Rt.uw<7:0> << 8 | 2226 Rt.uw<15:8>; 2227 }}); 2228 0x10: seb({{ Rd.sw = Rt.sb; }}); 2229 0x18: seh({{ Rd.sw = Rt.sh; }}); 2230 } 2231 } 2232 2233 0x6: decode FUNCTION_LO { 2234 2235 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2236 //(DSP ASE MANUAL) 2237 0x0: decode OP_HI { 2238 0x0: decode OP_LO { 2239 format DspHiLoOp { 2240 0x0: dpa_w_ph({{ 2241 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2242 SIMD_FMT_PH, SIGNED, MODE_L); 2243 }}, IntMultOp); 2244 0x1: dps_w_ph({{ 2245 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2246 SIMD_FMT_PH, SIGNED, MODE_L); 2247 }}, IntMultOp); 2248 0x2: mulsa_w_ph({{ 2249 dspac = dspMulsa(dspac, Rs.sw, Rt.sw, 2250 ACDST, SIMD_FMT_PH ); 2251 }}, IntMultOp); 2252 0x3: dpau_h_qbl({{ 2253 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2254 SIMD_FMT_QB, UNSIGNED, MODE_L); 2255 }}, IntMultOp); 2256 0x4: dpaq_s_w_ph({{ 2257 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2258 ACDST, SIMD_FMT_PH, 2259 SIMD_FMT_W, NOSATURATE, 2260 MODE_L, &dspctl); 2261 }}, IntMultOp); 2262 0x5: dpsq_s_w_ph({{ 2263 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2264 ACDST, SIMD_FMT_PH, 2265 SIMD_FMT_W, NOSATURATE, 2266 MODE_L, &dspctl); 2267 }}, IntMultOp); 2268 0x6: mulsaq_s_w_ph({{ 2269 dspac = dspMulsaq(dspac, Rs.sw, Rt.sw, 2270 ACDST, SIMD_FMT_PH, 2271 &dspctl); 2272 }}, IntMultOp); 2273 0x7: dpau_h_qbr({{ 2274 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2275 SIMD_FMT_QB, UNSIGNED, MODE_R); 2276 }}, IntMultOp); 2277 } 2278 } 2279 0x1: decode OP_LO { 2280 format DspHiLoOp { 2281 0x0: dpax_w_ph({{ 2282 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2283 SIMD_FMT_PH, SIGNED, MODE_X); 2284 }}, IntMultOp); 2285 0x1: dpsx_w_ph({{ 2286 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2287 SIMD_FMT_PH, SIGNED, MODE_X); 2288 }}, IntMultOp); 2289 0x3: dpsu_h_qbl({{ 2290 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2291 SIMD_FMT_QB, UNSIGNED, MODE_L); 2292 }}, IntMultOp); 2293 0x4: dpaq_sa_l_w({{ 2294 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2295 ACDST, SIMD_FMT_W, 2296 SIMD_FMT_L, SATURATE, 2297 MODE_L, &dspctl); 2298 }}, IntMultOp); 2299 0x5: dpsq_sa_l_w({{ 2300 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2301 ACDST, SIMD_FMT_W, 2302 SIMD_FMT_L, SATURATE, 2303 MODE_L, &dspctl); 2304 }}, IntMultOp); 2305 0x7: dpsu_h_qbr({{ 2306 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2307 SIMD_FMT_QB, UNSIGNED, MODE_R); 2308 }}, IntMultOp); 2309 } 2310 } 2311 0x2: decode OP_LO { 2312 format DspHiLoOp { 2313 0x0: maq_sa_w_phl({{ 2314 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2315 ACDST, SIMD_FMT_PH, 2316 MODE_L, SATURATE, &dspctl); 2317 }}, IntMultOp); 2318 0x2: maq_sa_w_phr({{ 2319 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2320 ACDST, SIMD_FMT_PH, 2321 MODE_R, SATURATE, &dspctl); 2322 }}, IntMultOp); 2323 0x4: maq_s_w_phl({{ 2324 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2325 ACDST, SIMD_FMT_PH, 2326 MODE_L, NOSATURATE, &dspctl); 2327 }}, IntMultOp); 2328 0x6: maq_s_w_phr({{ 2329 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2330 ACDST, SIMD_FMT_PH, 2331 MODE_R, NOSATURATE, &dspctl); 2332 }}, IntMultOp); 2333 } 2334 } 2335 0x3: decode OP_LO { 2336 format DspHiLoOp { 2337 0x0: dpaqx_s_w_ph({{ 2338 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2339 ACDST, SIMD_FMT_PH, 2340 SIMD_FMT_W, NOSATURATE, 2341 MODE_X, &dspctl); 2342 }}, IntMultOp); 2343 0x1: dpsqx_s_w_ph({{ 2344 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2345 ACDST, SIMD_FMT_PH, 2346 SIMD_FMT_W, NOSATURATE, 2347 MODE_X, &dspctl); 2348 }}, IntMultOp); 2349 0x2: dpaqx_sa_w_ph({{ 2350 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2351 ACDST, SIMD_FMT_PH, 2352 SIMD_FMT_W, SATURATE, 2353 MODE_X, &dspctl); 2354 }}, IntMultOp); 2355 0x3: dpsqx_sa_w_ph({{ 2356 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2357 ACDST, SIMD_FMT_PH, 2358 SIMD_FMT_W, SATURATE, 2359 MODE_X, &dspctl); 2360 }}, IntMultOp); 2361 } 2362 } 2363 } 2364 2365 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2366 0x1: decode OP_HI { 2367 0x0: decode OP_LO { 2368 format IntOp { 2369 0x0: append({{ 2370 Rt.uw = (Rt.uw << RD) | bits(Rs.uw, RD - 1, 0); 2371 }}); 2372 0x1: prepend({{ 2373 Rt.uw = (Rt.uw >> RD) | 2374 (bits(Rs.uw, RD - 1, 0) << (32 - RD)); 2375 }}); 2376 } 2377 } 2378 0x2: decode OP_LO { 2379 format IntOp { 2380 0x0: balign({{ 2381 Rt.uw = (Rt.uw << (8 * BP)) | 2382 (Rs.uw >> (8 * (4 - BP))); 2383 }}); 2384 } 2385 } 2386 } 2387 2388 } 2389 0x7: decode FUNCTION_LO { 2390 2391 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2392 //(DSP ASE MANUAL) 2393 0x0: decode OP_HI { 2394 0x0: decode OP_LO { 2395 format DspHiLoOp { 2396 0x0: extr_w({{ 2397 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2398 NOROUND, NOSATURATE, &dspctl); 2399 }}); 2400 0x1: extrv_w({{ 2401 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2402 NOROUND, NOSATURATE, &dspctl); 2403 }}); 2404 0x2: extp({{ 2405 Rt.uw = dspExtp(dspac, RS, &dspctl); 2406 }}); 2407 0x3: extpv({{ 2408 Rt.uw = dspExtp(dspac, Rs.uw, &dspctl); 2409 }}); 2410 0x4: extr_r_w({{ 2411 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2412 ROUND, NOSATURATE, &dspctl); 2413 }}); 2414 0x5: extrv_r_w({{ 2415 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2416 ROUND, NOSATURATE, &dspctl); 2417 }}); 2418 0x6: extr_rs_w({{ 2419 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2420 ROUND, SATURATE, &dspctl); 2421 }}); 2422 0x7: extrv_rs_w({{ 2423 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2424 ROUND, SATURATE, &dspctl); 2425 }}); 2426 } 2427 } 2428 0x1: decode OP_LO { 2429 format DspHiLoOp { 2430 0x2: extpdp({{ 2431 Rt.uw = dspExtpd(dspac, RS, &dspctl); 2432 }}); 2433 0x3: extpdpv({{ 2434 Rt.uw = dspExtpd(dspac, Rs.uw, &dspctl); 2435 }}); 2436 0x6: extr_s_h({{ 2437 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2438 NOROUND, SATURATE, &dspctl); 2439 }}); 2440 0x7: extrv_s_h({{ 2441 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, Rs.uw, 2442 NOROUND, SATURATE, &dspctl); 2443 }}); 2444 } 2445 } 2446 0x2: decode OP_LO { 2447 format DspIntOp { 2448 0x2: rddsp({{ 2449 Rd.uw = readDSPControl(&dspctl, RDDSPMASK); 2450 }}); 2451 0x3: wrdsp({{ 2452 writeDSPControl(&dspctl, Rs.uw, WRDSPMASK); 2453 }}); 2454 } 2455 } 2456 0x3: decode OP_LO { 2457 format DspHiLoOp { 2458 0x2: shilo({{ 2459 if (sext<6>(HILOSA) < 0) { 2460 dspac = (uint64_t)dspac << 2461 -sext<6>(HILOSA); 2462 } else { 2463 dspac = (uint64_t)dspac >> 2464 sext<6>(HILOSA); 2465 } 2466 }}); 2467 0x3: shilov({{ 2468 if (sext<6>(Rs.sw<5:0>) < 0) { 2469 dspac = (uint64_t)dspac << 2470 -sext<6>(Rs.sw<5:0>); 2471 } else { 2472 dspac = (uint64_t)dspac >> 2473 sext<6>(Rs.sw<5:0>); 2474 } 2475 }}); 2476 0x7: mthlip({{ 2477 dspac = dspac << 32; 2478 dspac |= Rs.uw; 2479 dspctl = insertBits(dspctl, 5, 0, 2480 dspctl<5:0> + 32); 2481 }}); 2482 } 2483 } 2484 } 2485 0x3: decode OP { 2486#if FULL_SYSTEM 2487 0x0: FailUnimpl::rdhwr(); 2488#else 2489 0x0: decode RD { 2490 29: BasicOp::rdhwr({{ Rt = TpValue; }}); 2491 } 2492#endif 2493 } 2494 } 2495 } 2496 } 2497 2498 0x4: decode OPCODE_LO { 2499 format LoadMemory { 2500 0x0: lb({{ Rt.sw = Mem.sb; }}); 2501 0x1: lh({{ Rt.sw = Mem.sh; }}); 2502 0x3: lw({{ Rt.sw = Mem.sw; }}); 2503 0x4: lbu({{ Rt.uw = Mem.ub;}}); 2504 0x5: lhu({{ Rt.uw = Mem.uh; }}); 2505 } 2506 2507 format LoadUnalignedMemory { 2508 0x2: lwl({{ 2509 uint32_t mem_shift = 24 - (8 * byte_offset); 2510 Rt.uw = mem_word << mem_shift | (Rt.uw & mask(mem_shift)); 2511 }}); 2512 0x6: lwr({{ 2513 uint32_t mem_shift = 8 * byte_offset; 2514 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | 2515 (mem_word >> mem_shift); 2516 }}); 2517 } 2518 } 2519 2520 0x5: decode OPCODE_LO { 2521 format StoreMemory { 2522 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 2523 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 2524 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 2525 } 2526 2527 format StoreUnalignedMemory { 2528 0x2: swl({{ 2529 uint32_t reg_shift = 24 - (8 * byte_offset); 2530 uint32_t mem_shift = 32 - reg_shift; 2531 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2532 (Rt.uw >> reg_shift); 2533 }}); 2534 0x6: swr({{ 2535 uint32_t reg_shift = 8 * byte_offset; 2536 mem_word = Rt.uw << reg_shift | 2537 (mem_word & (mask(reg_shift))); 2538 }}); 2539 } 2540 format CP0Control { 2541 0x7: cache({{ 2542 //Addr CacheEA = Rs.uw + OFFSET; 2543 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2544 }}); 2545 } 2546 } 2547 2548 0x6: decode OPCODE_LO { 2549 format LoadMemory { 2550 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC); 2551 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 2552 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 2553 } 2554 0x2: CP2Unimpl::lwc2(); 2555 0x6: CP2Unimpl::ldc2(); 2556 0x3: Prefetch::pref(); 2557 } 2558 2559 2560 0x7: decode OPCODE_LO { 2561 0x0: StoreCond::sc({{ Mem.uw = Rt.uw; }}, 2562 {{ uint64_t tmp = write_result; 2563 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 2564 }}, mem_flags=LLSC, 2565 inst_flags = IsStoreConditional); 2566 format StoreMemory { 2567 0x1: swc1({{ Mem.uw = Ft.uw; }}); 2568 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 2569 } 2570 0x2: CP2Unimpl::swc2(); 2571 0x6: CP2Unimpl::sdc2(); 2572 } 2573} 2574 2575
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