538 }}); 539 default: CP0Unimpl::unknown(); 540 } 541 } 542 } 543 0xB: decode RD { 544 format MT_Control { 545 0x0: decode POS { 546 0x0: decode SEL { 547 0x1: decode SC { 548 0x0: dvpe({{ 549 MVPControlReg mvpControl = MVPControl; 550 VPEConf0Reg vpeConf0 = VPEConf0; 551 Rt = MVPControl; 552 if (vpeConf0.mvp == 1) 553 mvpControl.evp = 0; 554 MVPControl = mvpControl; 555 }}); 556 0x1: evpe({{ 557 MVPControlReg mvpControl = MVPControl; 558 VPEConf0Reg vpeConf0 = VPEConf0; 559 Rt = MVPControl; 560 if (vpeConf0.mvp == 1) 561 mvpControl.evp = 1; 562 MVPControl = mvpControl; 563 }}); 564 default:CP0Unimpl::unknown(); 565 } 566 default:CP0Unimpl::unknown(); 567 } 568 default:CP0Unimpl::unknown(); 569 } 570 0x1: decode POS { 571 0xF: decode SEL { 572 0x1: decode SC { 573 0x0: dmt({{ 574 VPEControlReg vpeControl = VPEControl; 575 Rt = vpeControl; 576 vpeControl.te = 0; 577 VPEControl = vpeControl; 578 }}); 579 0x1: emt({{ 580 VPEControlReg vpeControl = VPEControl; 581 Rt = vpeControl; 582 vpeControl.te = 1; 583 VPEControl = vpeControl; 584 }}); 585 default:CP0Unimpl::unknown(); 586 } 587 default:CP0Unimpl::unknown(); 588 } 589 default:CP0Unimpl::unknown(); 590 } 591 } 592 0xC: decode POS { 593 0x0: decode SC { 594 0x0: CP0Control::di({{ 595 StatusReg status = Status; 596 ConfigReg config = Config; 597 // Rev 2.0 or beyond? 598 if (config.ar >= 1) { 599 Rt = status; 600 status.ie = 0; 601 } else { 602 // Enable this else branch once we 603 // actually set values for Config on init 604 fault = std::make_shared<ReservedInstructionFault>(); 605 } 606 Status = status; 607 }}); 608 0x1: CP0Control::ei({{ 609 StatusReg status = Status; 610 ConfigReg config = Config; 611 if (config.ar >= 1) { 612 Rt = status; 613 status.ie = 1; 614 } else { 615 fault = std::make_shared<ReservedInstructionFault>(); 616 } 617 }}); 618 default:CP0Unimpl::unknown(); 619 } 620 } 621 default: CP0Unimpl::unknown(); 622 } 623 format CP0Control { 624 0xA: rdpgpr({{ 625 ConfigReg config = Config; 626 if (config.ar >= 1) { 627 // Rev 2 of the architecture 628 panic("Shadow Sets Not Fully Implemented.\n"); 629 } else { 630 fault = std::make_shared<ReservedInstructionFault>(); 631 } 632 }}); 633 0xE: wrpgpr({{ 634 ConfigReg config = Config; 635 if (config.ar >= 1) { 636 // Rev 2 of the architecture 637 panic("Shadow Sets Not Fully Implemented.\n"); 638 } else { 639 fault = std::make_shared<ReservedInstructionFault>(); 640 } 641 }}); 642 } 643 } 644 645 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 646 0x1: decode FUNCTION { 647 format CP0Control { 648 0x18: eret({{ 649 StatusReg status = Status; 650 ConfigReg config = Config; 651 SRSCtlReg srsCtl = SRSCtl; 652 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 653 if (status.erl == 1) { 654 status.erl = 0; 655 NPC = ErrorEPC; 656 // Need to adjust NNPC, otherwise things break 657 NNPC = ErrorEPC + sizeof(MachInst); 658 } else { 659 NPC = EPC; 660 // Need to adjust NNPC, otherwise things break 661 NNPC = EPC + sizeof(MachInst); 662 status.exl = 0; 663 if (config.ar >=1 && 664 srsCtl.hss > 0 && 665 status.bev == 0) { 666 srsCtl.css = srsCtl.pss; 667 //xc->setShadowSet(srsCtl.pss); 668 } 669 } 670 LLFlag = 0; 671 Status = status; 672 SRSCtl = srsCtl; 673 }}, IsReturn, IsSerializing, IsERET); 674 675 0x1F: deret({{ 676 DebugReg debug = Debug; 677 if (debug.dm == 1) { 678 debug.dm = 1; 679 debug.iexi = 0; 680 NPC = DEPC; 681 } else { 682 NPC = NPC; 683 // Undefined; 684 } 685 Debug = debug; 686 }}, IsReturn, IsSerializing, IsERET); 687 } 688 format CP0TLB { 689 0x01: tlbr({{ 690 MipsISA::PTE *PTEntry = 691 xc->tcBase()->getITBPtr()-> 692 getEntry(Index & 0x7FFFFFFF); 693 if (PTEntry == NULL) { 694 fatal("Invalid PTE Entry received on " 695 "a TLBR instruction\n"); 696 } 697 /* Setup PageMask */ 698 // If 1KB pages are not enabled, a read of PageMask 699 // must return 0b00 in bits 12, 11 700 PageMask = (PTEntry->Mask << 11); 701 /* Setup EntryHi */ 702 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 703 /* Setup Entry Lo0 */ 704 EntryLo0 = ((PTEntry->PFN0 << 6) | 705 (PTEntry->C0 << 3) | 706 (PTEntry->D0 << 2) | 707 (PTEntry->V0 << 1) | 708 PTEntry->G); 709 /* Setup Entry Lo1 */ 710 EntryLo1 = ((PTEntry->PFN1 << 6) | 711 (PTEntry->C1 << 3) | 712 (PTEntry->D1 << 2) | 713 (PTEntry->V1 << 1) | 714 PTEntry->G); 715 }}); // Need to hook up to TLB 716 717 0x02: tlbwi({{ 718 //Create PTE 719 MipsISA::PTE newEntry; 720 //Write PTE 721 newEntry.Mask = (Addr)(PageMask >> 11); 722 newEntry.VPN = (Addr)(EntryHi >> 11); 723 /* PageGrain _ ESP Config3 _ SP */ 724 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 725 // If 1KB pages are *NOT* enabled, lowest bits of 726 // the mask are 0b11 for TLB writes 727 newEntry.Mask |= 0x3; 728 // Reset bits 0 and 1 if 1KB pages are not enabled 729 newEntry.VPN &= 0xFFFFFFFC; 730 } 731 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 732 733 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 734 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 735 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 736 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 737 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 738 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 739 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 740 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 741 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 742 /* Now, compute the AddrShiftAmount and OffsetMask - 743 TLB optimizations */ 744 /* Addr Shift Amount for 1KB or larger pages */ 745 if ((newEntry.Mask & 0xFFFF) == 3) { 746 newEntry.AddrShiftAmount = 12; 747 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 748 newEntry.AddrShiftAmount = 10; 749 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 750 newEntry.AddrShiftAmount = 14; 751 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 752 newEntry.AddrShiftAmount = 16; 753 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 754 newEntry.AddrShiftAmount = 18; 755 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 756 newEntry.AddrShiftAmount = 20; 757 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 758 newEntry.AddrShiftAmount = 22; 759 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 760 newEntry.AddrShiftAmount = 24; 761 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 762 newEntry.AddrShiftAmount = 26; 763 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 764 newEntry.AddrShiftAmount = 28; 765 } else { 766 fatal("Invalid Mask Pattern Detected!\n"); 767 } 768 newEntry.OffsetMask = 769 (1 << newEntry.AddrShiftAmount) - 1; 770 771 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 772 Config3Reg config3 = Config3; 773 PageGrainReg pageGrain = PageGrain; 774 int SP = 0; 775 if (bits(config3, config3.sp) == 1 && 776 bits(pageGrain, pageGrain.esp) == 1) { 777 SP = 1; 778 } 779 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 780 }}); 781 0x06: tlbwr({{ 782 //Create PTE 783 MipsISA::PTE newEntry; 784 //Write PTE 785 newEntry.Mask = (Addr)(PageMask >> 11); 786 newEntry.VPN = (Addr)(EntryHi >> 11); 787 /* PageGrain _ ESP Config3 _ SP */ 788 if (bits(PageGrain, 28) == 0 || 789 bits(Config3, 4) == 0) { 790 // If 1KB pages are *NOT* enabled, lowest bits of 791 // the mask are 0b11 for TLB writes 792 newEntry.Mask |= 0x3; 793 // Reset bits 0 and 1 if 1KB pages are not enabled 794 newEntry.VPN &= 0xFFFFFFFC; 795 } 796 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 797 798 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 799 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 800 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 801 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 802 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 803 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 804 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 805 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 806 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 807 /* Now, compute the AddrShiftAmount and OffsetMask - 808 TLB optimizations */ 809 /* Addr Shift Amount for 1KB or larger pages */ 810 if ((newEntry.Mask & 0xFFFF) == 3){ 811 newEntry.AddrShiftAmount = 12; 812 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 813 newEntry.AddrShiftAmount = 10; 814 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 815 newEntry.AddrShiftAmount = 14; 816 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 817 newEntry.AddrShiftAmount = 16; 818 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 819 newEntry.AddrShiftAmount = 18; 820 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 821 newEntry.AddrShiftAmount = 20; 822 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 823 newEntry.AddrShiftAmount = 22; 824 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 825 newEntry.AddrShiftAmount = 24; 826 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 827 newEntry.AddrShiftAmount = 26; 828 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 829 newEntry.AddrShiftAmount = 28; 830 } else { 831 fatal("Invalid Mask Pattern Detected!\n"); 832 } 833 newEntry.OffsetMask = 834 (1 << newEntry.AddrShiftAmount) - 1; 835 836 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 837 Config3Reg config3 = Config3; 838 PageGrainReg pageGrain = PageGrain; 839 int SP = 0; 840 if (bits(config3, config3.sp) == 1 && 841 bits(pageGrain, pageGrain.esp) == 1) { 842 SP = 1; 843 } 844 Ptr->insertAt(newEntry, Random, SP); 845 }}); 846 847 0x08: tlbp({{ 848 Config3Reg config3 = Config3; 849 PageGrainReg pageGrain = PageGrain; 850 EntryHiReg entryHi = EntryHi; 851 int tlbIndex; 852 Addr vpn; 853 if (pageGrain.esp == 1 && config3.sp ==1) { 854 vpn = EntryHi >> 11; 855 } else { 856 // Mask off lower 2 bits 857 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 858 } 859 tlbIndex = xc->tcBase()->getITBPtr()-> 860 probeEntry(vpn, entryHi.asid); 861 // Check TLB for entry matching EntryHi 862 if (tlbIndex != -1) { 863 Index = tlbIndex; 864 } else { 865 // else, set Index = 1 << 31 866 Index = (1 << 31); 867 } 868 }}); 869 } 870 format CP0Unimpl { 871 0x20: wait(); 872 } 873 default: CP0Unimpl::unknown(); 874 } 875 } 876 877 //Table A-13 MIPS32 COP1 Encoding of rs Field 878 0x1: decode RS_MSB { 879 0x0: decode RS_HI { 880 0x0: decode RS_LO { 881 format CP1Control { 882 0x0: mfc1 ({{ Rt_uw = Fs_uw; }}); 883 884 0x2: cfc1({{ 885 switch (FS) { 886 case 0: 887 Rt = FIR; 888 break; 889 case 25: 890 Rt = (FCSR & 0xFE000000) >> 24 | 891 (FCSR & 0x00800000) >> 23; 892 break; 893 case 26: 894 Rt = (FCSR & 0x0003F07C); 895 break; 896 case 28: 897 Rt = (FCSR & 0x00000F80) | 898 (FCSR & 0x01000000) >> 21 | 899 (FCSR & 0x00000003); 900 break; 901 case 31: 902 Rt = FCSR; 903 break; 904 default: 905 warn("FP Control Value (%d) Not Valid"); 906 } 907 }}); 908 909 0x3: mfhc1({{ Rt_uw = Fs_ud<63:32>; }}); 910 911 0x4: mtc1({{ Fs_uw = Rt_uw; }}); 912 913 0x6: ctc1({{ 914 switch (FS) { 915 case 25: 916 FCSR = (Rt_uw<7:1> << 25) | // move 31-25 917 (FCSR & 0x01000000) | // bit 24 918 (FCSR & 0x004FFFFF); // bit 22-0 919 break; 920 case 26: 921 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 922 Rt_uw<17:12> << 12 | // bit 17-12 923 (FCSR & 0x00000F80) << 7 | // bit 11-7 924 Rt_uw<6:2> << 2 | // bit 6-2 925 (FCSR & 0x00000002); // bit 1-0 926 break; 927 case 28: 928 FCSR = (FCSR & 0xFE000000) | // move 31-25 929 Rt_uw<2:2> << 24 | // bit 24 930 (FCSR & 0x00FFF000) << 23 | // bit 23-12 931 Rt_uw<11:7> << 7 | // bit 24 932 (FCSR & 0x000007E) | 933 Rt_uw<1:0>; // bit 22-0 934 break; 935 case 31: 936 FCSR = Rt_uw; 937 break; 938 939 default: 940 panic("FP Control Value (%d) " 941 "Not Available. Ignoring Access " 942 "to Floating Control Status " 943 "Register", FS); 944 } 945 }}); 946 947 0x7: mthc1({{ 948 uint64_t fs_hi = Rt_uw; 949 uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF; 950 Fs_ud = (fs_hi << 32) | fs_lo; 951 }}); 952 953 } 954 format CP1Unimpl { 955 0x1: dmfc1(); 956 0x5: dmtc1(); 957 } 958 } 959 960 0x1: decode RS_LO { 961 0x0: decode ND { 962 format Branch { 963 0x0: decode TF { 964 0x0: bc1f({{ 965 cond = getCondCode(FCSR, BRANCH_CC) == 0; 966 }}); 967 0x1: bc1t({{ 968 cond = getCondCode(FCSR, BRANCH_CC) == 1; 969 }}); 970 } 971 0x1: decode TF { 972 0x0: bc1fl({{ 973 cond = getCondCode(FCSR, BRANCH_CC) == 0; 974 }}, Likely); 975 0x1: bc1tl({{ 976 cond = getCondCode(FCSR, BRANCH_CC) == 1; 977 }}, Likely); 978 } 979 } 980 } 981 format CP1Unimpl { 982 0x1: bc1any2(); 983 0x2: bc1any4(); 984 default: unknown(); 985 } 986 } 987 } 988 989 0x1: decode RS_HI { 990 0x2: decode RS_LO { 991 //Table A-14 MIPS32 COP1 Encoding of Function Field When 992 //rs=S (( single-precision floating point)) 993 0x0: decode FUNCTION_HI { 994 0x0: decode FUNCTION_LO { 995 format FloatOp { 996 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }}); 997 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }}); 998 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }}); 999 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }}); 1000 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }}); 1001 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }}); 1002 0x7: neg_s({{ Fd_sf = -Fs_sf; }}); 1003 } 1004 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }}); 1005 } 1006 0x1: decode FUNCTION_LO { 1007 format FloatConvertOp { 1008 0x0: round_l_s({{ val = Fs_sf; }}, 1009 ToLong, Round); 1010 0x1: trunc_l_s({{ val = Fs_sf; }}, 1011 ToLong, Trunc); 1012 0x2: ceil_l_s({{ val = Fs_sf;}}, 1013 ToLong, Ceil); 1014 0x3: floor_l_s({{ val = Fs_sf; }}, 1015 ToLong, Floor); 1016 0x4: round_w_s({{ val = Fs_sf; }}, 1017 ToWord, Round); 1018 0x5: trunc_w_s({{ val = Fs_sf; }}, 1019 ToWord, Trunc); 1020 0x6: ceil_w_s({{ val = Fs_sf; }}, 1021 ToWord, Ceil); 1022 0x7: floor_w_s({{ val = Fs_sf; }}, 1023 ToWord, Floor); 1024 } 1025 } 1026 1027 0x2: decode FUNCTION_LO { 1028 0x1: decode MOVCF { 1029 format BasicOp { 1030 0x0: movf_s({{ 1031 Fd = (getCondCode(FCSR,CC) == 0) ? 1032 Fs : Fd; 1033 }}); 1034 0x1: movt_s({{ 1035 Fd = (getCondCode(FCSR,CC) == 1) ? 1036 Fs : Fd; 1037 }}); 1038 } 1039 } 1040 1041 format BasicOp { 1042 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1043 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1044 } 1045 1046 format FloatOp { 1047 0x5: recip_s({{ Fd = 1 / Fs; }}); 1048 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 1049 } 1050 format CP1Unimpl { 1051 default: unknown(); 1052 } 1053 } 1054 0x3: CP1Unimpl::unknown(); 1055 1056 0x4: decode FUNCTION_LO { 1057 format FloatConvertOp { 1058 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble); 1059 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord); 1060 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong); 1061 } 1062 1063 0x6: FloatOp::cvt_ps_s({{ 1064 Fd_ud = (uint64_t) Fs_uw << 32 | 1065 (uint64_t) Ft_uw; 1066 }}); 1067 format CP1Unimpl { 1068 default: unknown(); 1069 } 1070 } 1071 0x5: CP1Unimpl::unknown(); 1072 1073 0x6: decode FUNCTION_LO { 1074 format FloatCompareOp { 1075 0x0: c_f_s({{ cond = 0; }}, 1076 SinglePrecision, UnorderedFalse); 1077 0x1: c_un_s({{ cond = 0; }}, 1078 SinglePrecision, UnorderedTrue); 1079 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }}, 1080 UnorderedFalse); 1081 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }}, 1082 UnorderedTrue); 1083 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }}, 1084 UnorderedFalse); 1085 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }}, 1086 UnorderedTrue); 1087 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }}, 1088 UnorderedFalse); 1089 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }}, 1090 UnorderedTrue); 1091 } 1092 } 1093 1094 0x7: decode FUNCTION_LO { 1095 format FloatCompareOp { 1096 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1097 UnorderedFalse, QnanException); 1098 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1099 UnorderedTrue, QnanException); 1100 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }}, 1101 UnorderedFalse, QnanException); 1102 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }}, 1103 UnorderedTrue, QnanException); 1104 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }}, 1105 UnorderedFalse, QnanException); 1106 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }}, 1107 UnorderedTrue, QnanException); 1108 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }}, 1109 UnorderedFalse, QnanException); 1110 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }}, 1111 UnorderedTrue, QnanException); 1112 } 1113 } 1114 } 1115 1116 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1117 //rs=D 1118 0x1: decode FUNCTION_HI { 1119 0x0: decode FUNCTION_LO { 1120 format FloatOp { 1121 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }}); 1122 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }}); 1123 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }}); 1124 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }}); 1125 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }}); 1126 0x5: abs_d({{ Fd_df = fabs(Fs_df); }}); 1127 0x7: neg_d({{ Fd_df = -1 * Fs_df; }}); 1128 } 1129 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }}); 1130 } 1131 1132 0x1: decode FUNCTION_LO { 1133 format FloatConvertOp { 1134 0x0: round_l_d({{ val = Fs_df; }}, 1135 ToLong, Round); 1136 0x1: trunc_l_d({{ val = Fs_df; }}, 1137 ToLong, Trunc); 1138 0x2: ceil_l_d({{ val = Fs_df; }}, 1139 ToLong, Ceil); 1140 0x3: floor_l_d({{ val = Fs_df; }}, 1141 ToLong, Floor); 1142 0x4: round_w_d({{ val = Fs_df; }}, 1143 ToWord, Round); 1144 0x5: trunc_w_d({{ val = Fs_df; }}, 1145 ToWord, Trunc); 1146 0x6: ceil_w_d({{ val = Fs_df; }}, 1147 ToWord, Ceil); 1148 0x7: floor_w_d({{ val = Fs_df; }}, 1149 ToWord, Floor); 1150 } 1151 } 1152 1153 0x2: decode FUNCTION_LO { 1154 0x1: decode MOVCF { 1155 format BasicOp { 1156 0x0: movf_d({{ 1157 Fd_df = (getCondCode(FCSR,CC) == 0) ? 1158 Fs_df : Fd_df; 1159 }}); 1160 0x1: movt_d({{ 1161 Fd_df = (getCondCode(FCSR,CC) == 1) ? 1162 Fs_df : Fd_df; 1163 }}); 1164 } 1165 } 1166 1167 format BasicOp { 1168 0x2: movz_d({{ 1169 Fd_df = (Rt == 0) ? Fs_df : Fd_df; 1170 }}); 1171 0x3: movn_d({{ 1172 Fd_df = (Rt != 0) ? Fs_df : Fd_df; 1173 }}); 1174 } 1175 1176 format FloatOp { 1177 0x5: recip_d({{ Fd_df = 1 / Fs_df; }}); 1178 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }}); 1179 } 1180 format CP1Unimpl { 1181 default: unknown(); 1182 } 1183 1184 } 1185 0x4: decode FUNCTION_LO { 1186 format FloatConvertOp { 1187 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle); 1188 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord); 1189 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong); 1190 } 1191 default: CP1Unimpl::unknown(); 1192 } 1193 1194 0x6: decode FUNCTION_LO { 1195 format FloatCompareOp { 1196 0x0: c_f_d({{ cond = 0; }}, 1197 DoublePrecision, UnorderedFalse); 1198 0x1: c_un_d({{ cond = 0; }}, 1199 DoublePrecision, UnorderedTrue); 1200 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }}, 1201 UnorderedFalse); 1202 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }}, 1203 UnorderedTrue); 1204 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }}, 1205 UnorderedFalse); 1206 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }}, 1207 UnorderedTrue); 1208 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }}, 1209 UnorderedFalse); 1210 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }}, 1211 UnorderedTrue); 1212 } 1213 } 1214 1215 0x7: decode FUNCTION_LO { 1216 format FloatCompareOp { 1217 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1218 UnorderedFalse, QnanException); 1219 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1220 UnorderedTrue, QnanException); 1221 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }}, 1222 UnorderedFalse, QnanException); 1223 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }}, 1224 UnorderedTrue, QnanException); 1225 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }}, 1226 UnorderedFalse, QnanException); 1227 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }}, 1228 UnorderedTrue, QnanException); 1229 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }}, 1230 UnorderedFalse, QnanException); 1231 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }}, 1232 UnorderedTrue, QnanException); 1233 } 1234 } 1235 default: CP1Unimpl::unknown(); 1236 } 1237 0x2: CP1Unimpl::unknown(); 1238 0x3: CP1Unimpl::unknown(); 1239 0x7: CP1Unimpl::unknown(); 1240 1241 //Table A-16 MIPS32 COP1 Encoding of Function 1242 //Field When rs=W 1243 0x4: decode FUNCTION { 1244 format FloatConvertOp { 1245 0x20: cvt_s_w({{ val = Fs_sw; }}, ToSingle); 1246 0x21: cvt_d_w({{ val = Fs_sw; }}, ToDouble); 1247 0x26: CP1Unimpl::cvt_ps_w(); 1248 } 1249 default: CP1Unimpl::unknown(); 1250 } 1251 1252 //Table A-16 MIPS32 COP1 Encoding of Function Field 1253 //When rs=L1 1254 //Note: "1. Format type L is legal only if 64-bit 1255 //floating point operations are enabled." 1256 0x5: decode FUNCTION { 1257 format FloatConvertOp { 1258 0x20: cvt_s_l({{ val = Fs_sd; }}, ToSingle); 1259 0x21: cvt_d_l({{ val = Fs_sd; }}, ToDouble); 1260 0x26: CP1Unimpl::cvt_ps_l(); 1261 } 1262 default: CP1Unimpl::unknown(); 1263 } 1264 1265 //Table A-17 MIPS64 COP1 Encoding of Function Field 1266 //When rs=PS1 1267 //Note: "1. Format type PS is legal only if 64-bit 1268 //floating point operations are enabled. " 1269 0x6: decode FUNCTION_HI { 1270 0x0: decode FUNCTION_LO { 1271 format Float64Op { 1272 0x0: add_ps({{ 1273 Fd1_sf = Fs1_sf + Ft2_sf; 1274 Fd2_sf = Fs2_sf + Ft2_sf; 1275 }}); 1276 0x1: sub_ps({{ 1277 Fd1_sf = Fs1_sf - Ft2_sf; 1278 Fd2_sf = Fs2_sf - Ft2_sf; 1279 }}); 1280 0x2: mul_ps({{ 1281 Fd1_sf = Fs1_sf * Ft2_sf; 1282 Fd2_sf = Fs2_sf * Ft2_sf; 1283 }}); 1284 0x5: abs_ps({{ 1285 Fd1_sf = fabs(Fs1_sf); 1286 Fd2_sf = fabs(Fs2_sf); 1287 }}); 1288 0x6: mov_ps({{ 1289 Fd1_sf = Fs1_sf; 1290 Fd2_sf = Fs2_sf; 1291 }}); 1292 0x7: neg_ps({{ 1293 Fd1_sf = -(Fs1_sf); 1294 Fd2_sf = -(Fs2_sf); 1295 }}); 1296 default: CP1Unimpl::unknown(); 1297 } 1298 } 1299 0x1: CP1Unimpl::unknown(); 1300 0x2: decode FUNCTION_LO { 1301 0x1: decode MOVCF { 1302 format Float64Op { 1303 0x0: movf_ps({{ 1304 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1305 Fs1 : Fd1; 1306 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1307 Fs2 : Fd2; 1308 }}); 1309 0x1: movt_ps({{ 1310 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1311 Fs1 : Fd1; 1312 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1313 Fs2 : Fd2; 1314 }}); 1315 } 1316 } 1317 1318 format Float64Op { 1319 0x2: movz_ps({{ 1320 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1321 Fs1 : Fd1; 1322 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1323 Fs2 : Fd2; 1324 }}); 1325 0x3: movn_ps({{ 1326 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1327 Fs1 : Fd1; 1328 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1329 Fs2 : Fd2; 1330 }}); 1331 } 1332 default: CP1Unimpl::unknown(); 1333 } 1334 0x3: CP1Unimpl::unknown(); 1335 0x4: decode FUNCTION_LO { 1336 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }}); 1337 default: CP1Unimpl::unknown(); 1338 } 1339 1340 0x5: decode FUNCTION_LO { 1341 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }}); 1342 format Float64Op { 1343 0x4: pll({{ 1344 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw; 1345 }}); 1346 0x5: plu({{ 1347 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw; 1348 }}); 1349 0x6: pul({{ 1350 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw; 1351 }}); 1352 0x7: puu({{ 1353 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw; 1354 }}); 1355 } 1356 default: CP1Unimpl::unknown(); 1357 } 1358 1359 0x6: decode FUNCTION_LO { 1360 format FloatPSCompareOp { 1361 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1362 UnorderedFalse); 1363 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1364 UnorderedTrue); 1365 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1366 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1367 UnorderedFalse); 1368 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1369 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1370 UnorderedTrue); 1371 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1372 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1373 UnorderedFalse); 1374 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }}, 1375 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1376 UnorderedTrue); 1377 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }}, 1378 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1379 UnorderedFalse); 1380 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1381 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1382 UnorderedTrue); 1383 } 1384 } 1385 1386 0x7: decode FUNCTION_LO { 1387 format FloatPSCompareOp { 1388 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1389 UnorderedFalse, QnanException); 1390 0x1: c_ngle_ps({{ cond1 = 0; }}, 1391 {{ cond2 = 0; }}, 1392 UnorderedTrue, QnanException); 1393 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1394 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1395 UnorderedFalse, QnanException); 1396 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1397 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1398 UnorderedTrue, QnanException); 1399 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1400 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1401 UnorderedFalse, QnanException); 1402 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1403 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1404 UnorderedTrue, QnanException); 1405 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1406 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1407 UnorderedFalse, QnanException); 1408 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1409 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1410 UnorderedTrue, QnanException); 1411 } 1412 } 1413 } 1414 } 1415 default: CP1Unimpl::unknown(); 1416 } 1417 } 1418 1419 //Table A-19 MIPS32 COP2 Encoding of rs Field 1420 0x2: decode RS_MSB { 1421 format CP2Unimpl { 1422 0x0: decode RS_HI { 1423 0x0: decode RS_LO { 1424 0x0: mfc2(); 1425 0x2: cfc2(); 1426 0x3: mfhc2(); 1427 0x4: mtc2(); 1428 0x6: ctc2(); 1429 0x7: mftc2(); 1430 default: unknown(); 1431 } 1432 1433 0x1: decode ND { 1434 0x0: decode TF { 1435 0x0: bc2f(); 1436 0x1: bc2t(); 1437 default: unknown(); 1438 } 1439 1440 0x1: decode TF { 1441 0x0: bc2fl(); 1442 0x1: bc2tl(); 1443 default: unknown(); 1444 } 1445 default: unknown(); 1446 1447 } 1448 default: unknown(); 1449 } 1450 default: unknown(); 1451 } 1452 } 1453 1454 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1455 //Note: "COP1X instructions are legal only if 64-bit floating point 1456 //operations are enabled." 1457 0x3: decode FUNCTION_HI { 1458 0x0: decode FUNCTION_LO { 1459 format LoadIndexedMemory { 1460 0x0: lwxc1({{ Fd_uw = Mem_uw; }}); 1461 0x1: ldxc1({{ Fd_ud = Mem_ud; }}); 1462 0x5: luxc1({{ Fd_ud = Mem_ud; }}, 1463 {{ EA = (Rs + Rt) & ~7; }}); 1464 } 1465 } 1466 1467 0x1: decode FUNCTION_LO { 1468 format StoreIndexedMemory { 1469 0x0: swxc1({{ Mem_uw = Fs_uw; }}); 1470 0x1: sdxc1({{ Mem_ud = Fs_ud; }}); 1471 0x5: suxc1({{ Mem_ud = Fs_ud; }}, 1472 {{ EA = (Rs + Rt) & ~7; }}); 1473 } 1474 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1475 } 1476 1477 0x3: decode FUNCTION_LO { 1478 0x6: Float64Op::alnv_ps({{ 1479 if (Rs<2:0> == 0) { 1480 Fd_ud = Fs_ud; 1481 } else if (Rs<2:0> == 4) { 1482 if (GuestByteOrder == BigEndianByteOrder) 1483 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; 1484 else 1485 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; 1486 } else { 1487 Fd_ud = Fd_ud; 1488 } 1489 }}); 1490 } 1491 1492 format FloatAccOp { 1493 0x4: decode FUNCTION_LO { 1494 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }}); 1495 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }}); 1496 0x6: madd_ps({{ 1497 Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df; 1498 Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df; 1499 }}); 1500 } 1501 1502 0x5: decode FUNCTION_LO { 1503 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }}); 1504 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }}); 1505 0x6: msub_ps({{ 1506 Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df; 1507 Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df; 1508 }}); 1509 } 1510 1511 0x6: decode FUNCTION_LO { 1512 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }}); 1513 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }}); 1514 0x6: nmadd_ps({{ 1515 Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df); 1516 Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df); 1517 }}); 1518 } 1519 1520 0x7: decode FUNCTION_LO { 1521 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }}); 1522 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }}); 1523 0x6: nmsub_ps({{ 1524 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df); 1525 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df); 1526 }}); 1527 } 1528 } 1529 } 1530 1531 format Branch { 1532 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely); 1533 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely); 1534 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely); 1535 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely); 1536 } 1537 } 1538 1539 0x3: decode OPCODE_LO { 1540 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1541 0x4: decode FUNCTION_HI { 1542 0x0: decode FUNCTION_LO { 1543 0x2: IntOp::mul({{ 1544 int64_t temp1 = Rs_sd * Rt_sd; 1545 Rd_sw = temp1<31:0>; 1546 }}, IntMultOp); 1547 1548 format HiLoRdSelValOp { 1549 0x0: madd({{ 1550 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1551 (Rs_sd * Rt_sd); 1552 }}, IntMultOp); 1553 0x1: maddu({{ 1554 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1555 (Rs_ud * Rt_ud); 1556 }}, IntMultOp); 1557 0x4: msub({{ 1558 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1559 (Rs_sd * Rt_sd); 1560 }}, IntMultOp); 1561 0x5: msubu({{ 1562 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1563 (Rs_ud * Rt_ud); 1564 }}, IntMultOp); 1565 } 1566 } 1567 1568 0x4: decode FUNCTION_LO { 1569 format BasicOp { 1570 0x0: clz({{ 1571 int cnt = 32; 1572 for (int idx = 31; idx >= 0; idx--) { 1573 if (Rs<idx:idx> == 1) { 1574 cnt = 31 - idx; 1575 break; 1576 } 1577 } 1578 Rd_uw = cnt; 1579 }}); 1580 0x1: clo({{ 1581 int cnt = 32; 1582 for (int idx = 31; idx >= 0; idx--) { 1583 if (Rs<idx:idx> == 0) { 1584 cnt = 31 - idx; 1585 break; 1586 } 1587 } 1588 Rd_uw = cnt; 1589 }}); 1590 } 1591 } 1592 1593 0x7: decode FUNCTION_LO { 1594 0x7: FailUnimpl::sdbbp(); 1595 } 1596 } 1597 1598 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1599 //of the Architecture 1600 0x7: decode FUNCTION_HI { 1601 0x0: decode FUNCTION_LO { 1602 format BasicOp { 1603 0x0: ext({{ Rt_uw = bits(Rs_uw, MSB+LSB, LSB); }}); 1604 0x4: ins({{ 1605 Rt_uw = bits(Rt_uw, 31, MSB+1) << (MSB+1) | 1606 bits(Rs_uw, MSB-LSB, 0) << LSB | 1607 bits(Rt_uw, LSB-1, 0); 1608 }}); 1609 } 1610 } 1611 1612 0x1: decode FUNCTION_LO { 1613 format MT_Control { 1614 0x0: fork({{ 1615 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1616 }}, UserMode); 1617 0x1: yield({{ 1618 Rd_sw = yieldThread(xc->tcBase(), fault, Rs_sw, 1619 YQMask); 1620 }}, UserMode); 1621 } 1622 1623 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1624 0x2: decode OP_HI { 1625 0x0: decode OP_LO { 1626 format LoadIndexedMemory { 1627 0x0: lwx({{ Rd_sw = Mem_sw; }}); 1628 0x4: lhx({{ Rd_sw = Mem_sh; }}); 1629 0x6: lbux({{ Rd_uw = Mem_ub; }}); 1630 } 1631 } 1632 } 1633 0x4: DspIntOp::insv({{ 1634 int pos = dspctl<5:0>; 1635 int size = dspctl<12:7> - 1; 1636 Rt_uw = insertBits(Rt_uw, pos+size, 1637 pos, Rs_uw<size:0>); 1638 }}); 1639 } 1640 1641 0x2: decode FUNCTION_LO { 1642 1643 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1644 //(DSP ASE MANUAL) 1645 0x0: decode OP_HI { 1646 0x0: decode OP_LO { 1647 format DspIntOp { 1648 0x0: addu_qb({{ 1649 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1650 NOSATURATE, UNSIGNED, &dspctl); 1651 }}); 1652 0x1: subu_qb({{ 1653 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1654 NOSATURATE, UNSIGNED, &dspctl); 1655 }}); 1656 0x4: addu_s_qb({{ 1657 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1658 SATURATE, UNSIGNED, &dspctl); 1659 }}); 1660 0x5: subu_s_qb({{ 1661 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1662 SATURATE, UNSIGNED, &dspctl); 1663 }}); 1664 0x6: muleu_s_ph_qbl({{ 1665 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1666 MODE_L, &dspctl); 1667 }}, IntMultOp); 1668 0x7: muleu_s_ph_qbr({{ 1669 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1670 MODE_R, &dspctl); 1671 }}, IntMultOp); 1672 } 1673 } 1674 0x1: decode OP_LO { 1675 format DspIntOp { 1676 0x0: addu_ph({{ 1677 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1678 NOSATURATE, UNSIGNED, &dspctl); 1679 }}); 1680 0x1: subu_ph({{ 1681 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1682 NOSATURATE, UNSIGNED, &dspctl); 1683 }}); 1684 0x2: addq_ph({{ 1685 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1686 NOSATURATE, SIGNED, &dspctl); 1687 }}); 1688 0x3: subq_ph({{ 1689 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1690 NOSATURATE, SIGNED, &dspctl); 1691 }}); 1692 0x4: addu_s_ph({{ 1693 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1694 SATURATE, UNSIGNED, &dspctl); 1695 }}); 1696 0x5: subu_s_ph({{ 1697 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1698 SATURATE, UNSIGNED, &dspctl); 1699 }}); 1700 0x6: addq_s_ph({{ 1701 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1702 SATURATE, SIGNED, &dspctl); 1703 }}); 1704 0x7: subq_s_ph({{ 1705 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1706 SATURATE, SIGNED, &dspctl); 1707 }}); 1708 } 1709 } 1710 0x2: decode OP_LO { 1711 format DspIntOp { 1712 0x0: addsc({{ 1713 int64_t dresult; 1714 dresult = Rs_ud + Rt_ud; 1715 Rd_sw = dresult<31:0>; 1716 dspctl = insertBits(dspctl, 13, 13, 1717 dresult<32:32>); 1718 }}); 1719 0x1: addwc({{ 1720 int64_t dresult; 1721 dresult = Rs_sd + Rt_sd + dspctl<13:13>; 1722 Rd_sw = dresult<31:0>; 1723 if (dresult<32:32> != dresult<31:31>) 1724 dspctl = insertBits(dspctl, 20, 20, 1); 1725 }}); 1726 0x2: modsub({{ 1727 Rd_sw = (Rs_sw == 0) ? Rt_sw<23:8> : 1728 Rs_sw - Rt_sw<7:0>; 1729 }}); 1730 0x4: raddu_w_qb({{ 1731 Rd_uw = Rs_uw<31:24> + Rs_uw<23:16> + 1732 Rs_uw<15:8> + Rs_uw<7:0>; 1733 }}); 1734 0x6: addq_s_w({{ 1735 Rd_sw = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W, 1736 SATURATE, SIGNED, &dspctl); 1737 }}); 1738 0x7: subq_s_w({{ 1739 Rd_sw = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W, 1740 SATURATE, SIGNED, &dspctl); 1741 }}); 1742 } 1743 } 1744 0x3: decode OP_LO { 1745 format DspIntOp { 1746 0x4: muleq_s_w_phl({{ 1747 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1748 MODE_L, &dspctl); 1749 }}, IntMultOp); 1750 0x5: muleq_s_w_phr({{ 1751 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1752 MODE_R, &dspctl); 1753 }}, IntMultOp); 1754 0x6: mulq_s_ph({{ 1755 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1756 SATURATE, NOROUND, &dspctl); 1757 }}, IntMultOp); 1758 0x7: mulq_rs_ph({{ 1759 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1760 SATURATE, ROUND, &dspctl); 1761 }}, IntMultOp); 1762 } 1763 } 1764 } 1765 1766 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1767 //(DSP ASE MANUAL) 1768 0x1: decode OP_HI { 1769 0x0: decode OP_LO { 1770 format DspIntOp { 1771 0x0: cmpu_eq_qb({{ 1772 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1773 UNSIGNED, CMP_EQ, &dspctl); 1774 }}); 1775 0x1: cmpu_lt_qb({{ 1776 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1777 UNSIGNED, CMP_LT, &dspctl); 1778 }}); 1779 0x2: cmpu_le_qb({{ 1780 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1781 UNSIGNED, CMP_LE, &dspctl); 1782 }}); 1783 0x3: pick_qb({{ 1784 Rd_uw = dspPick(Rs_uw, Rt_uw, 1785 SIMD_FMT_QB, &dspctl); 1786 }}); 1787 0x4: cmpgu_eq_qb({{ 1788 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1789 UNSIGNED, CMP_EQ ); 1790 }}); 1791 0x5: cmpgu_lt_qb({{ 1792 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1793 UNSIGNED, CMP_LT); 1794 }}); 1795 0x6: cmpgu_le_qb({{ 1796 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1797 UNSIGNED, CMP_LE); 1798 }}); 1799 } 1800 } 1801 0x1: decode OP_LO { 1802 format DspIntOp { 1803 0x0: cmp_eq_ph({{ 1804 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1805 SIGNED, CMP_EQ, &dspctl); 1806 }}); 1807 0x1: cmp_lt_ph({{ 1808 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1809 SIGNED, CMP_LT, &dspctl); 1810 }}); 1811 0x2: cmp_le_ph({{ 1812 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1813 SIGNED, CMP_LE, &dspctl); 1814 }}); 1815 0x3: pick_ph({{ 1816 Rd_uw = dspPick(Rs_uw, Rt_uw, 1817 SIMD_FMT_PH, &dspctl); 1818 }}); 1819 0x4: precrq_qb_ph({{ 1820 Rd_uw = Rs_uw<31:24> << 24 | 1821 Rs_uw<15:8> << 16 | 1822 Rt_uw<31:24> << 8 | 1823 Rt_uw<15:8>; 1824 }}); 1825 0x5: precr_qb_ph({{ 1826 Rd_uw = Rs_uw<23:16> << 24 | 1827 Rs_uw<7:0> << 16 | 1828 Rt_uw<23:16> << 8 | 1829 Rt_uw<7:0>; 1830 }}); 1831 0x6: packrl_ph({{ 1832 Rd_uw = dspPack(Rs_uw, Rt_uw, SIMD_FMT_PH); 1833 }}); 1834 0x7: precrqu_s_qb_ph({{ 1835 Rd_uw = dspPrecrqu(Rs_uw, Rt_uw, &dspctl); 1836 }}); 1837 } 1838 } 1839 0x2: decode OP_LO { 1840 format DspIntOp { 1841 0x4: precrq_ph_w({{ 1842 Rd_uw = Rs_uw<31:16> << 16 | Rt_uw<31:16>; 1843 }}); 1844 0x5: precrq_rs_ph_w({{ 1845 Rd_uw = dspPrecrq(Rs_uw, Rt_uw, 1846 SIMD_FMT_W, &dspctl); 1847 }}); 1848 } 1849 } 1850 0x3: decode OP_LO { 1851 format DspIntOp { 1852 0x0: cmpgdu_eq_qb({{ 1853 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1854 UNSIGNED, CMP_EQ, &dspctl); 1855 }}); 1856 0x1: cmpgdu_lt_qb({{ 1857 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1858 UNSIGNED, CMP_LT, &dspctl); 1859 }}); 1860 0x2: cmpgdu_le_qb({{ 1861 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1862 UNSIGNED, CMP_LE, &dspctl); 1863 }}); 1864 0x6: precr_sra_ph_w({{ 1865 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1866 SIMD_FMT_W, NOROUND); 1867 }}); 1868 0x7: precr_sra_r_ph_w({{ 1869 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1870 SIMD_FMT_W, ROUND); 1871 }}); 1872 } 1873 } 1874 } 1875 1876 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1877 //(DSP ASE MANUAL) 1878 0x2: decode OP_HI { 1879 0x0: decode OP_LO { 1880 format DspIntOp { 1881 0x1: absq_s_qb({{ 1882 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl); 1883 }}); 1884 0x2: repl_qb({{ 1885 Rd_uw = RS_RT<7:0> << 24 | 1886 RS_RT<7:0> << 16 | 1887 RS_RT<7:0> << 8 | 1888 RS_RT<7:0>; 1889 }}); 1890 0x3: replv_qb({{ 1891 Rd_sw = Rt_uw<7:0> << 24 | 1892 Rt_uw<7:0> << 16 | 1893 Rt_uw<7:0> << 8 | 1894 Rt_uw<7:0>; 1895 }}); 1896 0x4: precequ_ph_qbl({{ 1897 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1898 SIMD_FMT_PH, SIGNED, MODE_L); 1899 }}); 1900 0x5: precequ_ph_qbr({{ 1901 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1902 SIMD_FMT_PH, SIGNED, MODE_R); 1903 }}); 1904 0x6: precequ_ph_qbla({{ 1905 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1906 SIMD_FMT_PH, SIGNED, MODE_LA); 1907 }}); 1908 0x7: precequ_ph_qbra({{ 1909 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1910 SIMD_FMT_PH, SIGNED, MODE_RA); 1911 }}); 1912 } 1913 } 1914 0x1: decode OP_LO { 1915 format DspIntOp { 1916 0x1: absq_s_ph({{ 1917 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl); 1918 }}); 1919 0x2: repl_ph({{ 1920 Rd_uw = (sext<10>(RS_RT))<15:0> << 16 | 1921 (sext<10>(RS_RT))<15:0>; 1922 }}); 1923 0x3: replv_ph({{ 1924 Rd_uw = Rt_uw<15:0> << 16 | 1925 Rt_uw<15:0>; 1926 }}); 1927 0x4: preceq_w_phl({{ 1928 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1929 SIMD_FMT_W, SIGNED, MODE_L); 1930 }}); 1931 0x5: preceq_w_phr({{ 1932 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1933 SIMD_FMT_W, SIGNED, MODE_R); 1934 }}); 1935 } 1936 } 1937 0x2: decode OP_LO { 1938 format DspIntOp { 1939 0x1: absq_s_w({{ 1940 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl); 1941 }}); 1942 } 1943 } 1944 0x3: decode OP_LO { 1945 0x3: IntOp::bitrev({{ 1946 Rd_uw = bitrev( Rt_uw<15:0> ); 1947 }}); 1948 format DspIntOp { 1949 0x4: preceu_ph_qbl({{ 1950 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1951 UNSIGNED, SIMD_FMT_PH, 1952 UNSIGNED, MODE_L); 1953 }}); 1954 0x5: preceu_ph_qbr({{ 1955 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1956 UNSIGNED, SIMD_FMT_PH, 1957 UNSIGNED, MODE_R ); 1958 }}); 1959 0x6: preceu_ph_qbla({{ 1960 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1961 UNSIGNED, SIMD_FMT_PH, 1962 UNSIGNED, MODE_LA ); 1963 }}); 1964 0x7: preceu_ph_qbra({{ 1965 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1966 UNSIGNED, SIMD_FMT_PH, 1967 UNSIGNED, MODE_RA); 1968 }}); 1969 } 1970 } 1971 } 1972 1973 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 1974 //(DSP ASE MANUAL) 1975 0x3: decode OP_HI { 1976 0x0: decode OP_LO { 1977 format DspIntOp { 1978 0x0: shll_qb({{ 1979 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_QB, 1980 NOSATURATE, UNSIGNED, &dspctl); 1981 }}); 1982 0x1: shrl_qb({{ 1983 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_QB, 1984 UNSIGNED); 1985 }}); 1986 0x2: shllv_qb({{ 1987 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB, 1988 NOSATURATE, UNSIGNED, &dspctl); 1989 }}); 1990 0x3: shrlv_qb({{ 1991 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB, 1992 UNSIGNED); 1993 }}); 1994 0x4: shra_qb({{ 1995 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 1996 NOROUND, SIGNED, &dspctl); 1997 }}); 1998 0x5: shra_r_qb({{ 1999 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2000 ROUND, SIGNED, &dspctl); 2001 }}); 2002 0x6: shrav_qb({{ 2003 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2004 NOROUND, SIGNED, &dspctl); 2005 }}); 2006 0x7: shrav_r_qb({{ 2007 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2008 ROUND, SIGNED, &dspctl); 2009 }}); 2010 } 2011 } 2012 0x1: decode OP_LO { 2013 format DspIntOp { 2014 0x0: shll_ph({{ 2015 Rd_uw = dspShll(Rt_uw, RS, SIMD_FMT_PH, 2016 NOSATURATE, SIGNED, &dspctl); 2017 }}); 2018 0x1: shra_ph({{ 2019 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2020 NOROUND, SIGNED, &dspctl); 2021 }}); 2022 0x2: shllv_ph({{ 2023 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2024 NOSATURATE, SIGNED, &dspctl); 2025 }}); 2026 0x3: shrav_ph({{ 2027 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2028 NOROUND, SIGNED, &dspctl); 2029 }}); 2030 0x4: shll_s_ph({{ 2031 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_PH, 2032 SATURATE, SIGNED, &dspctl); 2033 }}); 2034 0x5: shra_r_ph({{ 2035 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2036 ROUND, SIGNED, &dspctl); 2037 }}); 2038 0x6: shllv_s_ph({{ 2039 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2040 SATURATE, SIGNED, &dspctl); 2041 }}); 2042 0x7: shrav_r_ph({{ 2043 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2044 ROUND, SIGNED, &dspctl); 2045 }}); 2046 } 2047 } 2048 0x2: decode OP_LO { 2049 format DspIntOp { 2050 0x4: shll_s_w({{ 2051 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_W, 2052 SATURATE, SIGNED, &dspctl); 2053 }}); 2054 0x5: shra_r_w({{ 2055 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_W, 2056 ROUND, SIGNED, &dspctl); 2057 }}); 2058 0x6: shllv_s_w({{ 2059 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W, 2060 SATURATE, SIGNED, &dspctl); 2061 }}); 2062 0x7: shrav_r_w({{ 2063 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W, 2064 ROUND, SIGNED, &dspctl); 2065 }}); 2066 } 2067 } 2068 0x3: decode OP_LO { 2069 format DspIntOp { 2070 0x1: shrl_ph({{ 2071 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_PH, 2072 UNSIGNED); 2073 }}); 2074 0x3: shrlv_ph({{ 2075 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH, 2076 UNSIGNED); 2077 }}); 2078 } 2079 } 2080 } 2081 } 2082 2083 0x3: decode FUNCTION_LO { 2084 2085 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2086 //(DSP ASE Rev2 Manual) 2087 0x0: decode OP_HI { 2088 0x0: decode OP_LO { 2089 format DspIntOp { 2090 0x0: adduh_qb({{ 2091 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2092 NOROUND, UNSIGNED); 2093 }}); 2094 0x1: subuh_qb({{ 2095 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2096 NOROUND, UNSIGNED); 2097 }}); 2098 0x2: adduh_r_qb({{ 2099 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2100 ROUND, UNSIGNED); 2101 }}); 2102 0x3: subuh_r_qb({{ 2103 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2104 ROUND, UNSIGNED); 2105 }}); 2106 } 2107 } 2108 0x1: decode OP_LO { 2109 format DspIntOp { 2110 0x0: addqh_ph({{ 2111 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2112 NOROUND, SIGNED); 2113 }}); 2114 0x1: subqh_ph({{ 2115 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2116 NOROUND, SIGNED); 2117 }}); 2118 0x2: addqh_r_ph({{ 2119 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2120 ROUND, SIGNED); 2121 }}); 2122 0x3: subqh_r_ph({{ 2123 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2124 ROUND, SIGNED); 2125 }}); 2126 0x4: mul_ph({{ 2127 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2128 NOSATURATE, &dspctl); 2129 }}, IntMultOp); 2130 0x6: mul_s_ph({{ 2131 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2132 SATURATE, &dspctl); 2133 }}, IntMultOp); 2134 } 2135 } 2136 0x2: decode OP_LO { 2137 format DspIntOp { 2138 0x0: addqh_w({{ 2139 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2140 NOROUND, SIGNED); 2141 }}); 2142 0x1: subqh_w({{ 2143 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2144 NOROUND, SIGNED); 2145 }}); 2146 0x2: addqh_r_w({{ 2147 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2148 ROUND, SIGNED); 2149 }}); 2150 0x3: subqh_r_w({{ 2151 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2152 ROUND, SIGNED); 2153 }}); 2154 0x6: mulq_s_w({{ 2155 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2156 SATURATE, NOROUND, &dspctl); 2157 }}, IntMultOp); 2158 0x7: mulq_rs_w({{ 2159 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2160 SATURATE, ROUND, &dspctl); 2161 }}, IntMultOp); 2162 } 2163 } 2164 } 2165 } 2166 2167 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2168 0x4: decode SA { 2169 format BasicOp { 2170 0x02: wsbh({{ 2171 Rd_uw = Rt_uw<23:16> << 24 | 2172 Rt_uw<31:24> << 16 | 2173 Rt_uw<7:0> << 8 | 2174 Rt_uw<15:8>; 2175 }}); 2176 0x10: seb({{ Rd_sw = Rt_sb; }}); 2177 0x18: seh({{ Rd_sw = Rt_sh; }}); 2178 } 2179 } 2180 2181 0x6: decode FUNCTION_LO { 2182 2183 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2184 //(DSP ASE MANUAL) 2185 0x0: decode OP_HI { 2186 0x0: decode OP_LO { 2187 format DspHiLoOp { 2188 0x0: dpa_w_ph({{ 2189 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2190 SIMD_FMT_PH, SIGNED, MODE_L); 2191 }}, IntMultOp); 2192 0x1: dps_w_ph({{ 2193 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2194 SIMD_FMT_PH, SIGNED, MODE_L); 2195 }}, IntMultOp); 2196 0x2: mulsa_w_ph({{ 2197 dspac = dspMulsa(dspac, Rs_sw, Rt_sw, 2198 ACDST, SIMD_FMT_PH ); 2199 }}, IntMultOp); 2200 0x3: dpau_h_qbl({{ 2201 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2202 SIMD_FMT_QB, UNSIGNED, MODE_L); 2203 }}, IntMultOp); 2204 0x4: dpaq_s_w_ph({{ 2205 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2206 ACDST, SIMD_FMT_PH, 2207 SIMD_FMT_W, NOSATURATE, 2208 MODE_L, &dspctl); 2209 }}, IntMultOp); 2210 0x5: dpsq_s_w_ph({{ 2211 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2212 ACDST, SIMD_FMT_PH, 2213 SIMD_FMT_W, NOSATURATE, 2214 MODE_L, &dspctl); 2215 }}, IntMultOp); 2216 0x6: mulsaq_s_w_ph({{ 2217 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw, 2218 ACDST, SIMD_FMT_PH, 2219 &dspctl); 2220 }}, IntMultOp); 2221 0x7: dpau_h_qbr({{ 2222 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2223 SIMD_FMT_QB, UNSIGNED, MODE_R); 2224 }}, IntMultOp); 2225 } 2226 } 2227 0x1: decode OP_LO { 2228 format DspHiLoOp { 2229 0x0: dpax_w_ph({{ 2230 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2231 SIMD_FMT_PH, SIGNED, MODE_X); 2232 }}, IntMultOp); 2233 0x1: dpsx_w_ph({{ 2234 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2235 SIMD_FMT_PH, SIGNED, MODE_X); 2236 }}, IntMultOp); 2237 0x3: dpsu_h_qbl({{ 2238 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2239 SIMD_FMT_QB, UNSIGNED, MODE_L); 2240 }}, IntMultOp); 2241 0x4: dpaq_sa_l_w({{ 2242 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2243 ACDST, SIMD_FMT_W, 2244 SIMD_FMT_L, SATURATE, 2245 MODE_L, &dspctl); 2246 }}, IntMultOp); 2247 0x5: dpsq_sa_l_w({{ 2248 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2249 ACDST, SIMD_FMT_W, 2250 SIMD_FMT_L, SATURATE, 2251 MODE_L, &dspctl); 2252 }}, IntMultOp); 2253 0x7: dpsu_h_qbr({{ 2254 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2255 SIMD_FMT_QB, UNSIGNED, MODE_R); 2256 }}, IntMultOp); 2257 } 2258 } 2259 0x2: decode OP_LO { 2260 format DspHiLoOp { 2261 0x0: maq_sa_w_phl({{ 2262 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2263 ACDST, SIMD_FMT_PH, 2264 MODE_L, SATURATE, &dspctl); 2265 }}, IntMultOp); 2266 0x2: maq_sa_w_phr({{ 2267 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2268 ACDST, SIMD_FMT_PH, 2269 MODE_R, SATURATE, &dspctl); 2270 }}, IntMultOp); 2271 0x4: maq_s_w_phl({{ 2272 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2273 ACDST, SIMD_FMT_PH, 2274 MODE_L, NOSATURATE, &dspctl); 2275 }}, IntMultOp); 2276 0x6: maq_s_w_phr({{ 2277 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2278 ACDST, SIMD_FMT_PH, 2279 MODE_R, NOSATURATE, &dspctl); 2280 }}, IntMultOp); 2281 } 2282 } 2283 0x3: decode OP_LO { 2284 format DspHiLoOp { 2285 0x0: dpaqx_s_w_ph({{ 2286 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2287 ACDST, SIMD_FMT_PH, 2288 SIMD_FMT_W, NOSATURATE, 2289 MODE_X, &dspctl); 2290 }}, IntMultOp); 2291 0x1: dpsqx_s_w_ph({{ 2292 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2293 ACDST, SIMD_FMT_PH, 2294 SIMD_FMT_W, NOSATURATE, 2295 MODE_X, &dspctl); 2296 }}, IntMultOp); 2297 0x2: dpaqx_sa_w_ph({{ 2298 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2299 ACDST, SIMD_FMT_PH, 2300 SIMD_FMT_W, SATURATE, 2301 MODE_X, &dspctl); 2302 }}, IntMultOp); 2303 0x3: dpsqx_sa_w_ph({{ 2304 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2305 ACDST, SIMD_FMT_PH, 2306 SIMD_FMT_W, SATURATE, 2307 MODE_X, &dspctl); 2308 }}, IntMultOp); 2309 } 2310 } 2311 } 2312 2313 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2314 0x1: decode OP_HI { 2315 0x0: decode OP_LO { 2316 format IntOp { 2317 0x0: append({{ 2318 Rt_uw = (Rt_uw << RD) | bits(Rs_uw, RD - 1, 0); 2319 }}); 2320 0x1: prepend({{ 2321 Rt_uw = (Rt_uw >> RD) | 2322 (bits(Rs_uw, RD - 1, 0) << (32 - RD)); 2323 }}); 2324 } 2325 } 2326 0x2: decode OP_LO { 2327 format IntOp { 2328 0x0: balign({{ 2329 Rt_uw = (Rt_uw << (8 * BP)) | 2330 (Rs_uw >> (8 * (4 - BP))); 2331 }}); 2332 } 2333 } 2334 } 2335 2336 } 2337 0x7: decode FUNCTION_LO { 2338 2339 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2340 //(DSP ASE MANUAL) 2341 0x0: decode OP_HI { 2342 0x0: decode OP_LO { 2343 format DspHiLoOp { 2344 0x0: extr_w({{ 2345 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2346 NOROUND, NOSATURATE, &dspctl); 2347 }}); 2348 0x1: extrv_w({{ 2349 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2350 NOROUND, NOSATURATE, &dspctl); 2351 }}); 2352 0x2: extp({{ 2353 Rt_uw = dspExtp(dspac, RS, &dspctl); 2354 }}); 2355 0x3: extpv({{ 2356 Rt_uw = dspExtp(dspac, Rs_uw, &dspctl); 2357 }}); 2358 0x4: extr_r_w({{ 2359 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2360 ROUND, NOSATURATE, &dspctl); 2361 }}); 2362 0x5: extrv_r_w({{ 2363 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2364 ROUND, NOSATURATE, &dspctl); 2365 }}); 2366 0x6: extr_rs_w({{ 2367 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2368 ROUND, SATURATE, &dspctl); 2369 }}); 2370 0x7: extrv_rs_w({{ 2371 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2372 ROUND, SATURATE, &dspctl); 2373 }}); 2374 } 2375 } 2376 0x1: decode OP_LO { 2377 format DspHiLoOp { 2378 0x2: extpdp({{ 2379 Rt_uw = dspExtpd(dspac, RS, &dspctl); 2380 }}); 2381 0x3: extpdpv({{ 2382 Rt_uw = dspExtpd(dspac, Rs_uw, &dspctl); 2383 }}); 2384 0x6: extr_s_h({{ 2385 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2386 NOROUND, SATURATE, &dspctl); 2387 }}); 2388 0x7: extrv_s_h({{ 2389 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, Rs_uw, 2390 NOROUND, SATURATE, &dspctl); 2391 }}); 2392 } 2393 } 2394 0x2: decode OP_LO { 2395 format DspIntOp { 2396 0x2: rddsp({{ 2397 Rd_uw = readDSPControl(&dspctl, RDDSPMASK); 2398 }}); 2399 0x3: wrdsp({{ 2400 writeDSPControl(&dspctl, Rs_uw, WRDSPMASK); 2401 }}); 2402 } 2403 } 2404 0x3: decode OP_LO { 2405 format DspHiLoOp { 2406 0x2: shilo({{ 2407 if ((int64_t)sext<6>(HILOSA) < 0) { 2408 dspac = (uint64_t)dspac << 2409 -sext<6>(HILOSA); 2410 } else { 2411 dspac = (uint64_t)dspac >> 2412 sext<6>(HILOSA); 2413 } 2414 }}); 2415 0x3: shilov({{ 2416 if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) { 2417 dspac = (uint64_t)dspac << 2418 -sext<6>(Rs_sw<5:0>); 2419 } else { 2420 dspac = (uint64_t)dspac >> 2421 sext<6>(Rs_sw<5:0>); 2422 } 2423 }}); 2424 0x7: mthlip({{ 2425 dspac = dspac << 32; 2426 dspac |= Rs_uw; 2427 dspctl = insertBits(dspctl, 5, 0, 2428 dspctl<5:0> + 32); 2429 }}); 2430 } 2431 } 2432 } 2433 0x3: decode OP default FailUnimpl::rdhwr() { 2434 0x0: decode FullSystemInt { 2435 0: decode RD { 2436 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2437 } 2438 } 2439 } 2440 } 2441 } 2442 } 2443 2444 0x4: decode OPCODE_LO { 2445 format LoadMemory { 2446 0x0: lb({{ Rt_sw = Mem_sb; }}); 2447 0x1: lh({{ Rt_sw = Mem_sh; }}); 2448 0x3: lw({{ Rt_sw = Mem_sw; }}); 2449 0x4: lbu({{ Rt_uw = Mem_ub;}}); 2450 0x5: lhu({{ Rt_uw = Mem_uh; }}); 2451 } 2452 2453 format LoadUnalignedMemory { 2454 0x2: lwl({{ 2455 uint32_t mem_shift = 24 - (8 * byte_offset); 2456 Rt_uw = mem_word << mem_shift | (Rt_uw & mask(mem_shift)); 2457 }}); 2458 0x6: lwr({{ 2459 uint32_t mem_shift = 8 * byte_offset; 2460 Rt_uw = (Rt_uw & (mask(mem_shift) << (32 - mem_shift))) | 2461 (mem_word >> mem_shift); 2462 }}); 2463 } 2464 } 2465 2466 0x5: decode OPCODE_LO { 2467 format StoreMemory { 2468 0x0: sb({{ Mem_ub = Rt<7:0>; }}); 2469 0x1: sh({{ Mem_uh = Rt<15:0>; }}); 2470 0x3: sw({{ Mem_uw = Rt<31:0>; }}); 2471 } 2472 2473 format StoreUnalignedMemory { 2474 0x2: swl({{ 2475 uint32_t reg_shift = 24 - (8 * byte_offset); 2476 uint32_t mem_shift = 32 - reg_shift; 2477 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2478 (Rt_uw >> reg_shift); 2479 }}); 2480 0x6: swr({{ 2481 uint32_t reg_shift = 8 * byte_offset; 2482 mem_word = Rt_uw << reg_shift | 2483 (mem_word & (mask(reg_shift))); 2484 }}); 2485 } 2486 format CP0Control { 2487 0x7: cache({{ 2488 //Addr CacheEA = Rs_uw + OFFSET; 2489 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2490 }}); 2491 } 2492 } 2493 2494 0x6: decode OPCODE_LO { 2495 format LoadMemory { 2496 0x0: ll({{ Rt_uw = Mem_uw; }}, mem_flags=LLSC); 2497 0x1: lwc1({{ Ft_uw = Mem_uw; }}); 2498 0x5: ldc1({{ Ft_ud = Mem_ud; }}); 2499 } 2500 0x2: CP2Unimpl::lwc2(); 2501 0x6: CP2Unimpl::ldc2(); 2502 0x3: Prefetch::pref(); 2503 } 2504 2505 2506 0x7: decode OPCODE_LO { 2507 0x0: StoreCond::sc({{ Mem_uw = Rt_uw; }}, 2508 {{ uint64_t tmp = write_result; 2509 Rt_uw = (tmp == 0 || tmp == 1) ? tmp : Rt_uw; 2510 }}, mem_flags=LLSC, 2511 inst_flags = IsStoreConditional); 2512 format StoreMemory { 2513 0x1: swc1({{ Mem_uw = Ft_uw; }}); 2514 0x5: sdc1({{ Mem_ud = Ft_ud; }}); 2515 } 2516 0x2: CP2Unimpl::swc2(); 2517 0x6: CP2Unimpl::sdc2(); 2518 } 2519} 2520 2521
| 587 }}); 588 default: CP0Unimpl::unknown(); 589 } 590 } 591 } 592 0xB: decode RD { 593 format MT_Control { 594 0x0: decode POS { 595 0x0: decode SEL { 596 0x1: decode SC { 597 0x0: dvpe({{ 598 MVPControlReg mvpControl = MVPControl; 599 VPEConf0Reg vpeConf0 = VPEConf0; 600 Rt = MVPControl; 601 if (vpeConf0.mvp == 1) 602 mvpControl.evp = 0; 603 MVPControl = mvpControl; 604 }}); 605 0x1: evpe({{ 606 MVPControlReg mvpControl = MVPControl; 607 VPEConf0Reg vpeConf0 = VPEConf0; 608 Rt = MVPControl; 609 if (vpeConf0.mvp == 1) 610 mvpControl.evp = 1; 611 MVPControl = mvpControl; 612 }}); 613 default:CP0Unimpl::unknown(); 614 } 615 default:CP0Unimpl::unknown(); 616 } 617 default:CP0Unimpl::unknown(); 618 } 619 0x1: decode POS { 620 0xF: decode SEL { 621 0x1: decode SC { 622 0x0: dmt({{ 623 VPEControlReg vpeControl = VPEControl; 624 Rt = vpeControl; 625 vpeControl.te = 0; 626 VPEControl = vpeControl; 627 }}); 628 0x1: emt({{ 629 VPEControlReg vpeControl = VPEControl; 630 Rt = vpeControl; 631 vpeControl.te = 1; 632 VPEControl = vpeControl; 633 }}); 634 default:CP0Unimpl::unknown(); 635 } 636 default:CP0Unimpl::unknown(); 637 } 638 default:CP0Unimpl::unknown(); 639 } 640 } 641 0xC: decode POS { 642 0x0: decode SC { 643 0x0: CP0Control::di({{ 644 StatusReg status = Status; 645 ConfigReg config = Config; 646 // Rev 2.0 or beyond? 647 if (config.ar >= 1) { 648 Rt = status; 649 status.ie = 0; 650 } else { 651 // Enable this else branch once we 652 // actually set values for Config on init 653 fault = std::make_shared<ReservedInstructionFault>(); 654 } 655 Status = status; 656 }}); 657 0x1: CP0Control::ei({{ 658 StatusReg status = Status; 659 ConfigReg config = Config; 660 if (config.ar >= 1) { 661 Rt = status; 662 status.ie = 1; 663 } else { 664 fault = std::make_shared<ReservedInstructionFault>(); 665 } 666 }}); 667 default:CP0Unimpl::unknown(); 668 } 669 } 670 default: CP0Unimpl::unknown(); 671 } 672 format CP0Control { 673 0xA: rdpgpr({{ 674 ConfigReg config = Config; 675 if (config.ar >= 1) { 676 // Rev 2 of the architecture 677 panic("Shadow Sets Not Fully Implemented.\n"); 678 } else { 679 fault = std::make_shared<ReservedInstructionFault>(); 680 } 681 }}); 682 0xE: wrpgpr({{ 683 ConfigReg config = Config; 684 if (config.ar >= 1) { 685 // Rev 2 of the architecture 686 panic("Shadow Sets Not Fully Implemented.\n"); 687 } else { 688 fault = std::make_shared<ReservedInstructionFault>(); 689 } 690 }}); 691 } 692 } 693 694 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 695 0x1: decode FUNCTION { 696 format CP0Control { 697 0x18: eret({{ 698 StatusReg status = Status; 699 ConfigReg config = Config; 700 SRSCtlReg srsCtl = SRSCtl; 701 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 702 if (status.erl == 1) { 703 status.erl = 0; 704 NPC = ErrorEPC; 705 // Need to adjust NNPC, otherwise things break 706 NNPC = ErrorEPC + sizeof(MachInst); 707 } else { 708 NPC = EPC; 709 // Need to adjust NNPC, otherwise things break 710 NNPC = EPC + sizeof(MachInst); 711 status.exl = 0; 712 if (config.ar >=1 && 713 srsCtl.hss > 0 && 714 status.bev == 0) { 715 srsCtl.css = srsCtl.pss; 716 //xc->setShadowSet(srsCtl.pss); 717 } 718 } 719 LLFlag = 0; 720 Status = status; 721 SRSCtl = srsCtl; 722 }}, IsReturn, IsSerializing, IsERET); 723 724 0x1F: deret({{ 725 DebugReg debug = Debug; 726 if (debug.dm == 1) { 727 debug.dm = 1; 728 debug.iexi = 0; 729 NPC = DEPC; 730 } else { 731 NPC = NPC; 732 // Undefined; 733 } 734 Debug = debug; 735 }}, IsReturn, IsSerializing, IsERET); 736 } 737 format CP0TLB { 738 0x01: tlbr({{ 739 MipsISA::PTE *PTEntry = 740 xc->tcBase()->getITBPtr()-> 741 getEntry(Index & 0x7FFFFFFF); 742 if (PTEntry == NULL) { 743 fatal("Invalid PTE Entry received on " 744 "a TLBR instruction\n"); 745 } 746 /* Setup PageMask */ 747 // If 1KB pages are not enabled, a read of PageMask 748 // must return 0b00 in bits 12, 11 749 PageMask = (PTEntry->Mask << 11); 750 /* Setup EntryHi */ 751 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 752 /* Setup Entry Lo0 */ 753 EntryLo0 = ((PTEntry->PFN0 << 6) | 754 (PTEntry->C0 << 3) | 755 (PTEntry->D0 << 2) | 756 (PTEntry->V0 << 1) | 757 PTEntry->G); 758 /* Setup Entry Lo1 */ 759 EntryLo1 = ((PTEntry->PFN1 << 6) | 760 (PTEntry->C1 << 3) | 761 (PTEntry->D1 << 2) | 762 (PTEntry->V1 << 1) | 763 PTEntry->G); 764 }}); // Need to hook up to TLB 765 766 0x02: tlbwi({{ 767 //Create PTE 768 MipsISA::PTE newEntry; 769 //Write PTE 770 newEntry.Mask = (Addr)(PageMask >> 11); 771 newEntry.VPN = (Addr)(EntryHi >> 11); 772 /* PageGrain _ ESP Config3 _ SP */ 773 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 774 // If 1KB pages are *NOT* enabled, lowest bits of 775 // the mask are 0b11 for TLB writes 776 newEntry.Mask |= 0x3; 777 // Reset bits 0 and 1 if 1KB pages are not enabled 778 newEntry.VPN &= 0xFFFFFFFC; 779 } 780 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 781 782 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 783 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 784 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 785 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 786 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 787 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 788 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 789 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 790 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 791 /* Now, compute the AddrShiftAmount and OffsetMask - 792 TLB optimizations */ 793 /* Addr Shift Amount for 1KB or larger pages */ 794 if ((newEntry.Mask & 0xFFFF) == 3) { 795 newEntry.AddrShiftAmount = 12; 796 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 797 newEntry.AddrShiftAmount = 10; 798 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 799 newEntry.AddrShiftAmount = 14; 800 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 801 newEntry.AddrShiftAmount = 16; 802 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 803 newEntry.AddrShiftAmount = 18; 804 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 805 newEntry.AddrShiftAmount = 20; 806 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 807 newEntry.AddrShiftAmount = 22; 808 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 809 newEntry.AddrShiftAmount = 24; 810 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 811 newEntry.AddrShiftAmount = 26; 812 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 813 newEntry.AddrShiftAmount = 28; 814 } else { 815 fatal("Invalid Mask Pattern Detected!\n"); 816 } 817 newEntry.OffsetMask = 818 (1 << newEntry.AddrShiftAmount) - 1; 819 820 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 821 Config3Reg config3 = Config3; 822 PageGrainReg pageGrain = PageGrain; 823 int SP = 0; 824 if (bits(config3, config3.sp) == 1 && 825 bits(pageGrain, pageGrain.esp) == 1) { 826 SP = 1; 827 } 828 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 829 }}); 830 0x06: tlbwr({{ 831 //Create PTE 832 MipsISA::PTE newEntry; 833 //Write PTE 834 newEntry.Mask = (Addr)(PageMask >> 11); 835 newEntry.VPN = (Addr)(EntryHi >> 11); 836 /* PageGrain _ ESP Config3 _ SP */ 837 if (bits(PageGrain, 28) == 0 || 838 bits(Config3, 4) == 0) { 839 // If 1KB pages are *NOT* enabled, lowest bits of 840 // the mask are 0b11 for TLB writes 841 newEntry.Mask |= 0x3; 842 // Reset bits 0 and 1 if 1KB pages are not enabled 843 newEntry.VPN &= 0xFFFFFFFC; 844 } 845 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 846 847 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 848 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 849 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 850 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 851 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 852 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 853 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 854 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 855 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 856 /* Now, compute the AddrShiftAmount and OffsetMask - 857 TLB optimizations */ 858 /* Addr Shift Amount for 1KB or larger pages */ 859 if ((newEntry.Mask & 0xFFFF) == 3){ 860 newEntry.AddrShiftAmount = 12; 861 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 862 newEntry.AddrShiftAmount = 10; 863 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 864 newEntry.AddrShiftAmount = 14; 865 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 866 newEntry.AddrShiftAmount = 16; 867 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 868 newEntry.AddrShiftAmount = 18; 869 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 870 newEntry.AddrShiftAmount = 20; 871 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 872 newEntry.AddrShiftAmount = 22; 873 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 874 newEntry.AddrShiftAmount = 24; 875 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 876 newEntry.AddrShiftAmount = 26; 877 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 878 newEntry.AddrShiftAmount = 28; 879 } else { 880 fatal("Invalid Mask Pattern Detected!\n"); 881 } 882 newEntry.OffsetMask = 883 (1 << newEntry.AddrShiftAmount) - 1; 884 885 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 886 Config3Reg config3 = Config3; 887 PageGrainReg pageGrain = PageGrain; 888 int SP = 0; 889 if (bits(config3, config3.sp) == 1 && 890 bits(pageGrain, pageGrain.esp) == 1) { 891 SP = 1; 892 } 893 Ptr->insertAt(newEntry, Random, SP); 894 }}); 895 896 0x08: tlbp({{ 897 Config3Reg config3 = Config3; 898 PageGrainReg pageGrain = PageGrain; 899 EntryHiReg entryHi = EntryHi; 900 int tlbIndex; 901 Addr vpn; 902 if (pageGrain.esp == 1 && config3.sp ==1) { 903 vpn = EntryHi >> 11; 904 } else { 905 // Mask off lower 2 bits 906 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 907 } 908 tlbIndex = xc->tcBase()->getITBPtr()-> 909 probeEntry(vpn, entryHi.asid); 910 // Check TLB for entry matching EntryHi 911 if (tlbIndex != -1) { 912 Index = tlbIndex; 913 } else { 914 // else, set Index = 1 << 31 915 Index = (1 << 31); 916 } 917 }}); 918 } 919 format CP0Unimpl { 920 0x20: wait(); 921 } 922 default: CP0Unimpl::unknown(); 923 } 924 } 925 926 //Table A-13 MIPS32 COP1 Encoding of rs Field 927 0x1: decode RS_MSB { 928 0x0: decode RS_HI { 929 0x0: decode RS_LO { 930 format CP1Control { 931 0x0: mfc1 ({{ Rt_uw = Fs_uw; }}); 932 933 0x2: cfc1({{ 934 switch (FS) { 935 case 0: 936 Rt = FIR; 937 break; 938 case 25: 939 Rt = (FCSR & 0xFE000000) >> 24 | 940 (FCSR & 0x00800000) >> 23; 941 break; 942 case 26: 943 Rt = (FCSR & 0x0003F07C); 944 break; 945 case 28: 946 Rt = (FCSR & 0x00000F80) | 947 (FCSR & 0x01000000) >> 21 | 948 (FCSR & 0x00000003); 949 break; 950 case 31: 951 Rt = FCSR; 952 break; 953 default: 954 warn("FP Control Value (%d) Not Valid"); 955 } 956 }}); 957 958 0x3: mfhc1({{ Rt_uw = Fs_ud<63:32>; }}); 959 960 0x4: mtc1({{ Fs_uw = Rt_uw; }}); 961 962 0x6: ctc1({{ 963 switch (FS) { 964 case 25: 965 FCSR = (Rt_uw<7:1> << 25) | // move 31-25 966 (FCSR & 0x01000000) | // bit 24 967 (FCSR & 0x004FFFFF); // bit 22-0 968 break; 969 case 26: 970 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 971 Rt_uw<17:12> << 12 | // bit 17-12 972 (FCSR & 0x00000F80) << 7 | // bit 11-7 973 Rt_uw<6:2> << 2 | // bit 6-2 974 (FCSR & 0x00000002); // bit 1-0 975 break; 976 case 28: 977 FCSR = (FCSR & 0xFE000000) | // move 31-25 978 Rt_uw<2:2> << 24 | // bit 24 979 (FCSR & 0x00FFF000) << 23 | // bit 23-12 980 Rt_uw<11:7> << 7 | // bit 24 981 (FCSR & 0x000007E) | 982 Rt_uw<1:0>; // bit 22-0 983 break; 984 case 31: 985 FCSR = Rt_uw; 986 break; 987 988 default: 989 panic("FP Control Value (%d) " 990 "Not Available. Ignoring Access " 991 "to Floating Control Status " 992 "Register", FS); 993 } 994 }}); 995 996 0x7: mthc1({{ 997 uint64_t fs_hi = Rt_uw; 998 uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF; 999 Fs_ud = (fs_hi << 32) | fs_lo; 1000 }}); 1001 1002 } 1003 format CP1Unimpl { 1004 0x1: dmfc1(); 1005 0x5: dmtc1(); 1006 } 1007 } 1008 1009 0x1: decode RS_LO { 1010 0x0: decode ND { 1011 format Branch { 1012 0x0: decode TF { 1013 0x0: bc1f({{ 1014 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1015 }}); 1016 0x1: bc1t({{ 1017 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1018 }}); 1019 } 1020 0x1: decode TF { 1021 0x0: bc1fl({{ 1022 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1023 }}, Likely); 1024 0x1: bc1tl({{ 1025 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1026 }}, Likely); 1027 } 1028 } 1029 } 1030 format CP1Unimpl { 1031 0x1: bc1any2(); 1032 0x2: bc1any4(); 1033 default: unknown(); 1034 } 1035 } 1036 } 1037 1038 0x1: decode RS_HI { 1039 0x2: decode RS_LO { 1040 //Table A-14 MIPS32 COP1 Encoding of Function Field When 1041 //rs=S (( single-precision floating point)) 1042 0x0: decode FUNCTION_HI { 1043 0x0: decode FUNCTION_LO { 1044 format FloatOp { 1045 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }}); 1046 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }}); 1047 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }}); 1048 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }}); 1049 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }}); 1050 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }}); 1051 0x7: neg_s({{ Fd_sf = -Fs_sf; }}); 1052 } 1053 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }}); 1054 } 1055 0x1: decode FUNCTION_LO { 1056 format FloatConvertOp { 1057 0x0: round_l_s({{ val = Fs_sf; }}, 1058 ToLong, Round); 1059 0x1: trunc_l_s({{ val = Fs_sf; }}, 1060 ToLong, Trunc); 1061 0x2: ceil_l_s({{ val = Fs_sf;}}, 1062 ToLong, Ceil); 1063 0x3: floor_l_s({{ val = Fs_sf; }}, 1064 ToLong, Floor); 1065 0x4: round_w_s({{ val = Fs_sf; }}, 1066 ToWord, Round); 1067 0x5: trunc_w_s({{ val = Fs_sf; }}, 1068 ToWord, Trunc); 1069 0x6: ceil_w_s({{ val = Fs_sf; }}, 1070 ToWord, Ceil); 1071 0x7: floor_w_s({{ val = Fs_sf; }}, 1072 ToWord, Floor); 1073 } 1074 } 1075 1076 0x2: decode FUNCTION_LO { 1077 0x1: decode MOVCF { 1078 format BasicOp { 1079 0x0: movf_s({{ 1080 Fd = (getCondCode(FCSR,CC) == 0) ? 1081 Fs : Fd; 1082 }}); 1083 0x1: movt_s({{ 1084 Fd = (getCondCode(FCSR,CC) == 1) ? 1085 Fs : Fd; 1086 }}); 1087 } 1088 } 1089 1090 format BasicOp { 1091 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1092 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1093 } 1094 1095 format FloatOp { 1096 0x5: recip_s({{ Fd = 1 / Fs; }}); 1097 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 1098 } 1099 format CP1Unimpl { 1100 default: unknown(); 1101 } 1102 } 1103 0x3: CP1Unimpl::unknown(); 1104 1105 0x4: decode FUNCTION_LO { 1106 format FloatConvertOp { 1107 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble); 1108 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord); 1109 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong); 1110 } 1111 1112 0x6: FloatOp::cvt_ps_s({{ 1113 Fd_ud = (uint64_t) Fs_uw << 32 | 1114 (uint64_t) Ft_uw; 1115 }}); 1116 format CP1Unimpl { 1117 default: unknown(); 1118 } 1119 } 1120 0x5: CP1Unimpl::unknown(); 1121 1122 0x6: decode FUNCTION_LO { 1123 format FloatCompareOp { 1124 0x0: c_f_s({{ cond = 0; }}, 1125 SinglePrecision, UnorderedFalse); 1126 0x1: c_un_s({{ cond = 0; }}, 1127 SinglePrecision, UnorderedTrue); 1128 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }}, 1129 UnorderedFalse); 1130 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }}, 1131 UnorderedTrue); 1132 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }}, 1133 UnorderedFalse); 1134 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }}, 1135 UnorderedTrue); 1136 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }}, 1137 UnorderedFalse); 1138 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }}, 1139 UnorderedTrue); 1140 } 1141 } 1142 1143 0x7: decode FUNCTION_LO { 1144 format FloatCompareOp { 1145 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1146 UnorderedFalse, QnanException); 1147 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1148 UnorderedTrue, QnanException); 1149 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }}, 1150 UnorderedFalse, QnanException); 1151 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }}, 1152 UnorderedTrue, QnanException); 1153 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }}, 1154 UnorderedFalse, QnanException); 1155 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }}, 1156 UnorderedTrue, QnanException); 1157 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }}, 1158 UnorderedFalse, QnanException); 1159 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }}, 1160 UnorderedTrue, QnanException); 1161 } 1162 } 1163 } 1164 1165 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1166 //rs=D 1167 0x1: decode FUNCTION_HI { 1168 0x0: decode FUNCTION_LO { 1169 format FloatOp { 1170 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }}); 1171 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }}); 1172 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }}); 1173 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }}); 1174 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }}); 1175 0x5: abs_d({{ Fd_df = fabs(Fs_df); }}); 1176 0x7: neg_d({{ Fd_df = -1 * Fs_df; }}); 1177 } 1178 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }}); 1179 } 1180 1181 0x1: decode FUNCTION_LO { 1182 format FloatConvertOp { 1183 0x0: round_l_d({{ val = Fs_df; }}, 1184 ToLong, Round); 1185 0x1: trunc_l_d({{ val = Fs_df; }}, 1186 ToLong, Trunc); 1187 0x2: ceil_l_d({{ val = Fs_df; }}, 1188 ToLong, Ceil); 1189 0x3: floor_l_d({{ val = Fs_df; }}, 1190 ToLong, Floor); 1191 0x4: round_w_d({{ val = Fs_df; }}, 1192 ToWord, Round); 1193 0x5: trunc_w_d({{ val = Fs_df; }}, 1194 ToWord, Trunc); 1195 0x6: ceil_w_d({{ val = Fs_df; }}, 1196 ToWord, Ceil); 1197 0x7: floor_w_d({{ val = Fs_df; }}, 1198 ToWord, Floor); 1199 } 1200 } 1201 1202 0x2: decode FUNCTION_LO { 1203 0x1: decode MOVCF { 1204 format BasicOp { 1205 0x0: movf_d({{ 1206 Fd_df = (getCondCode(FCSR,CC) == 0) ? 1207 Fs_df : Fd_df; 1208 }}); 1209 0x1: movt_d({{ 1210 Fd_df = (getCondCode(FCSR,CC) == 1) ? 1211 Fs_df : Fd_df; 1212 }}); 1213 } 1214 } 1215 1216 format BasicOp { 1217 0x2: movz_d({{ 1218 Fd_df = (Rt == 0) ? Fs_df : Fd_df; 1219 }}); 1220 0x3: movn_d({{ 1221 Fd_df = (Rt != 0) ? Fs_df : Fd_df; 1222 }}); 1223 } 1224 1225 format FloatOp { 1226 0x5: recip_d({{ Fd_df = 1 / Fs_df; }}); 1227 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }}); 1228 } 1229 format CP1Unimpl { 1230 default: unknown(); 1231 } 1232 1233 } 1234 0x4: decode FUNCTION_LO { 1235 format FloatConvertOp { 1236 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle); 1237 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord); 1238 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong); 1239 } 1240 default: CP1Unimpl::unknown(); 1241 } 1242 1243 0x6: decode FUNCTION_LO { 1244 format FloatCompareOp { 1245 0x0: c_f_d({{ cond = 0; }}, 1246 DoublePrecision, UnorderedFalse); 1247 0x1: c_un_d({{ cond = 0; }}, 1248 DoublePrecision, UnorderedTrue); 1249 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }}, 1250 UnorderedFalse); 1251 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }}, 1252 UnorderedTrue); 1253 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }}, 1254 UnorderedFalse); 1255 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }}, 1256 UnorderedTrue); 1257 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }}, 1258 UnorderedFalse); 1259 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }}, 1260 UnorderedTrue); 1261 } 1262 } 1263 1264 0x7: decode FUNCTION_LO { 1265 format FloatCompareOp { 1266 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1267 UnorderedFalse, QnanException); 1268 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1269 UnorderedTrue, QnanException); 1270 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }}, 1271 UnorderedFalse, QnanException); 1272 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }}, 1273 UnorderedTrue, QnanException); 1274 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }}, 1275 UnorderedFalse, QnanException); 1276 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }}, 1277 UnorderedTrue, QnanException); 1278 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }}, 1279 UnorderedFalse, QnanException); 1280 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }}, 1281 UnorderedTrue, QnanException); 1282 } 1283 } 1284 default: CP1Unimpl::unknown(); 1285 } 1286 0x2: CP1Unimpl::unknown(); 1287 0x3: CP1Unimpl::unknown(); 1288 0x7: CP1Unimpl::unknown(); 1289 1290 //Table A-16 MIPS32 COP1 Encoding of Function 1291 //Field When rs=W 1292 0x4: decode FUNCTION { 1293 format FloatConvertOp { 1294 0x20: cvt_s_w({{ val = Fs_sw; }}, ToSingle); 1295 0x21: cvt_d_w({{ val = Fs_sw; }}, ToDouble); 1296 0x26: CP1Unimpl::cvt_ps_w(); 1297 } 1298 default: CP1Unimpl::unknown(); 1299 } 1300 1301 //Table A-16 MIPS32 COP1 Encoding of Function Field 1302 //When rs=L1 1303 //Note: "1. Format type L is legal only if 64-bit 1304 //floating point operations are enabled." 1305 0x5: decode FUNCTION { 1306 format FloatConvertOp { 1307 0x20: cvt_s_l({{ val = Fs_sd; }}, ToSingle); 1308 0x21: cvt_d_l({{ val = Fs_sd; }}, ToDouble); 1309 0x26: CP1Unimpl::cvt_ps_l(); 1310 } 1311 default: CP1Unimpl::unknown(); 1312 } 1313 1314 //Table A-17 MIPS64 COP1 Encoding of Function Field 1315 //When rs=PS1 1316 //Note: "1. Format type PS is legal only if 64-bit 1317 //floating point operations are enabled. " 1318 0x6: decode FUNCTION_HI { 1319 0x0: decode FUNCTION_LO { 1320 format Float64Op { 1321 0x0: add_ps({{ 1322 Fd1_sf = Fs1_sf + Ft2_sf; 1323 Fd2_sf = Fs2_sf + Ft2_sf; 1324 }}); 1325 0x1: sub_ps({{ 1326 Fd1_sf = Fs1_sf - Ft2_sf; 1327 Fd2_sf = Fs2_sf - Ft2_sf; 1328 }}); 1329 0x2: mul_ps({{ 1330 Fd1_sf = Fs1_sf * Ft2_sf; 1331 Fd2_sf = Fs2_sf * Ft2_sf; 1332 }}); 1333 0x5: abs_ps({{ 1334 Fd1_sf = fabs(Fs1_sf); 1335 Fd2_sf = fabs(Fs2_sf); 1336 }}); 1337 0x6: mov_ps({{ 1338 Fd1_sf = Fs1_sf; 1339 Fd2_sf = Fs2_sf; 1340 }}); 1341 0x7: neg_ps({{ 1342 Fd1_sf = -(Fs1_sf); 1343 Fd2_sf = -(Fs2_sf); 1344 }}); 1345 default: CP1Unimpl::unknown(); 1346 } 1347 } 1348 0x1: CP1Unimpl::unknown(); 1349 0x2: decode FUNCTION_LO { 1350 0x1: decode MOVCF { 1351 format Float64Op { 1352 0x0: movf_ps({{ 1353 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1354 Fs1 : Fd1; 1355 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1356 Fs2 : Fd2; 1357 }}); 1358 0x1: movt_ps({{ 1359 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1360 Fs1 : Fd1; 1361 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1362 Fs2 : Fd2; 1363 }}); 1364 } 1365 } 1366 1367 format Float64Op { 1368 0x2: movz_ps({{ 1369 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1370 Fs1 : Fd1; 1371 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1372 Fs2 : Fd2; 1373 }}); 1374 0x3: movn_ps({{ 1375 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1376 Fs1 : Fd1; 1377 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1378 Fs2 : Fd2; 1379 }}); 1380 } 1381 default: CP1Unimpl::unknown(); 1382 } 1383 0x3: CP1Unimpl::unknown(); 1384 0x4: decode FUNCTION_LO { 1385 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }}); 1386 default: CP1Unimpl::unknown(); 1387 } 1388 1389 0x5: decode FUNCTION_LO { 1390 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }}); 1391 format Float64Op { 1392 0x4: pll({{ 1393 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw; 1394 }}); 1395 0x5: plu({{ 1396 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw; 1397 }}); 1398 0x6: pul({{ 1399 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw; 1400 }}); 1401 0x7: puu({{ 1402 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw; 1403 }}); 1404 } 1405 default: CP1Unimpl::unknown(); 1406 } 1407 1408 0x6: decode FUNCTION_LO { 1409 format FloatPSCompareOp { 1410 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1411 UnorderedFalse); 1412 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1413 UnorderedTrue); 1414 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1415 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1416 UnorderedFalse); 1417 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1418 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1419 UnorderedTrue); 1420 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1421 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1422 UnorderedFalse); 1423 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }}, 1424 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1425 UnorderedTrue); 1426 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }}, 1427 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1428 UnorderedFalse); 1429 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1430 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1431 UnorderedTrue); 1432 } 1433 } 1434 1435 0x7: decode FUNCTION_LO { 1436 format FloatPSCompareOp { 1437 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1438 UnorderedFalse, QnanException); 1439 0x1: c_ngle_ps({{ cond1 = 0; }}, 1440 {{ cond2 = 0; }}, 1441 UnorderedTrue, QnanException); 1442 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1443 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1444 UnorderedFalse, QnanException); 1445 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1446 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1447 UnorderedTrue, QnanException); 1448 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1449 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1450 UnorderedFalse, QnanException); 1451 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1452 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1453 UnorderedTrue, QnanException); 1454 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1455 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1456 UnorderedFalse, QnanException); 1457 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1458 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1459 UnorderedTrue, QnanException); 1460 } 1461 } 1462 } 1463 } 1464 default: CP1Unimpl::unknown(); 1465 } 1466 } 1467 1468 //Table A-19 MIPS32 COP2 Encoding of rs Field 1469 0x2: decode RS_MSB { 1470 format CP2Unimpl { 1471 0x0: decode RS_HI { 1472 0x0: decode RS_LO { 1473 0x0: mfc2(); 1474 0x2: cfc2(); 1475 0x3: mfhc2(); 1476 0x4: mtc2(); 1477 0x6: ctc2(); 1478 0x7: mftc2(); 1479 default: unknown(); 1480 } 1481 1482 0x1: decode ND { 1483 0x0: decode TF { 1484 0x0: bc2f(); 1485 0x1: bc2t(); 1486 default: unknown(); 1487 } 1488 1489 0x1: decode TF { 1490 0x0: bc2fl(); 1491 0x1: bc2tl(); 1492 default: unknown(); 1493 } 1494 default: unknown(); 1495 1496 } 1497 default: unknown(); 1498 } 1499 default: unknown(); 1500 } 1501 } 1502 1503 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1504 //Note: "COP1X instructions are legal only if 64-bit floating point 1505 //operations are enabled." 1506 0x3: decode FUNCTION_HI { 1507 0x0: decode FUNCTION_LO { 1508 format LoadIndexedMemory { 1509 0x0: lwxc1({{ Fd_uw = Mem_uw; }}); 1510 0x1: ldxc1({{ Fd_ud = Mem_ud; }}); 1511 0x5: luxc1({{ Fd_ud = Mem_ud; }}, 1512 {{ EA = (Rs + Rt) & ~7; }}); 1513 } 1514 } 1515 1516 0x1: decode FUNCTION_LO { 1517 format StoreIndexedMemory { 1518 0x0: swxc1({{ Mem_uw = Fs_uw; }}); 1519 0x1: sdxc1({{ Mem_ud = Fs_ud; }}); 1520 0x5: suxc1({{ Mem_ud = Fs_ud; }}, 1521 {{ EA = (Rs + Rt) & ~7; }}); 1522 } 1523 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1524 } 1525 1526 0x3: decode FUNCTION_LO { 1527 0x6: Float64Op::alnv_ps({{ 1528 if (Rs<2:0> == 0) { 1529 Fd_ud = Fs_ud; 1530 } else if (Rs<2:0> == 4) { 1531 if (GuestByteOrder == BigEndianByteOrder) 1532 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; 1533 else 1534 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; 1535 } else { 1536 Fd_ud = Fd_ud; 1537 } 1538 }}); 1539 } 1540 1541 format FloatAccOp { 1542 0x4: decode FUNCTION_LO { 1543 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }}); 1544 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }}); 1545 0x6: madd_ps({{ 1546 Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df; 1547 Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df; 1548 }}); 1549 } 1550 1551 0x5: decode FUNCTION_LO { 1552 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }}); 1553 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }}); 1554 0x6: msub_ps({{ 1555 Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df; 1556 Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df; 1557 }}); 1558 } 1559 1560 0x6: decode FUNCTION_LO { 1561 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }}); 1562 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }}); 1563 0x6: nmadd_ps({{ 1564 Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df); 1565 Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df); 1566 }}); 1567 } 1568 1569 0x7: decode FUNCTION_LO { 1570 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }}); 1571 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }}); 1572 0x6: nmsub_ps({{ 1573 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df); 1574 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df); 1575 }}); 1576 } 1577 } 1578 } 1579 1580 format Branch { 1581 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely); 1582 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely); 1583 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely); 1584 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely); 1585 } 1586 } 1587 1588 0x3: decode OPCODE_LO { 1589 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1590 0x4: decode FUNCTION_HI { 1591 0x0: decode FUNCTION_LO { 1592 0x2: IntOp::mul({{ 1593 int64_t temp1 = Rs_sd * Rt_sd; 1594 Rd_sw = temp1<31:0>; 1595 }}, IntMultOp); 1596 1597 format HiLoRdSelValOp { 1598 0x0: madd({{ 1599 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1600 (Rs_sd * Rt_sd); 1601 }}, IntMultOp); 1602 0x1: maddu({{ 1603 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1604 (Rs_ud * Rt_ud); 1605 }}, IntMultOp); 1606 0x4: msub({{ 1607 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1608 (Rs_sd * Rt_sd); 1609 }}, IntMultOp); 1610 0x5: msubu({{ 1611 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1612 (Rs_ud * Rt_ud); 1613 }}, IntMultOp); 1614 } 1615 } 1616 1617 0x4: decode FUNCTION_LO { 1618 format BasicOp { 1619 0x0: clz({{ 1620 int cnt = 32; 1621 for (int idx = 31; idx >= 0; idx--) { 1622 if (Rs<idx:idx> == 1) { 1623 cnt = 31 - idx; 1624 break; 1625 } 1626 } 1627 Rd_uw = cnt; 1628 }}); 1629 0x1: clo({{ 1630 int cnt = 32; 1631 for (int idx = 31; idx >= 0; idx--) { 1632 if (Rs<idx:idx> == 0) { 1633 cnt = 31 - idx; 1634 break; 1635 } 1636 } 1637 Rd_uw = cnt; 1638 }}); 1639 } 1640 } 1641 1642 0x7: decode FUNCTION_LO { 1643 0x7: FailUnimpl::sdbbp(); 1644 } 1645 } 1646 1647 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1648 //of the Architecture 1649 0x7: decode FUNCTION_HI { 1650 0x0: decode FUNCTION_LO { 1651 format BasicOp { 1652 0x0: ext({{ Rt_uw = bits(Rs_uw, MSB+LSB, LSB); }}); 1653 0x4: ins({{ 1654 Rt_uw = bits(Rt_uw, 31, MSB+1) << (MSB+1) | 1655 bits(Rs_uw, MSB-LSB, 0) << LSB | 1656 bits(Rt_uw, LSB-1, 0); 1657 }}); 1658 } 1659 } 1660 1661 0x1: decode FUNCTION_LO { 1662 format MT_Control { 1663 0x0: fork({{ 1664 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1665 }}, UserMode); 1666 0x1: yield({{ 1667 Rd_sw = yieldThread(xc->tcBase(), fault, Rs_sw, 1668 YQMask); 1669 }}, UserMode); 1670 } 1671 1672 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1673 0x2: decode OP_HI { 1674 0x0: decode OP_LO { 1675 format LoadIndexedMemory { 1676 0x0: lwx({{ Rd_sw = Mem_sw; }}); 1677 0x4: lhx({{ Rd_sw = Mem_sh; }}); 1678 0x6: lbux({{ Rd_uw = Mem_ub; }}); 1679 } 1680 } 1681 } 1682 0x4: DspIntOp::insv({{ 1683 int pos = dspctl<5:0>; 1684 int size = dspctl<12:7> - 1; 1685 Rt_uw = insertBits(Rt_uw, pos+size, 1686 pos, Rs_uw<size:0>); 1687 }}); 1688 } 1689 1690 0x2: decode FUNCTION_LO { 1691 1692 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1693 //(DSP ASE MANUAL) 1694 0x0: decode OP_HI { 1695 0x0: decode OP_LO { 1696 format DspIntOp { 1697 0x0: addu_qb({{ 1698 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1699 NOSATURATE, UNSIGNED, &dspctl); 1700 }}); 1701 0x1: subu_qb({{ 1702 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1703 NOSATURATE, UNSIGNED, &dspctl); 1704 }}); 1705 0x4: addu_s_qb({{ 1706 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1707 SATURATE, UNSIGNED, &dspctl); 1708 }}); 1709 0x5: subu_s_qb({{ 1710 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1711 SATURATE, UNSIGNED, &dspctl); 1712 }}); 1713 0x6: muleu_s_ph_qbl({{ 1714 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1715 MODE_L, &dspctl); 1716 }}, IntMultOp); 1717 0x7: muleu_s_ph_qbr({{ 1718 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1719 MODE_R, &dspctl); 1720 }}, IntMultOp); 1721 } 1722 } 1723 0x1: decode OP_LO { 1724 format DspIntOp { 1725 0x0: addu_ph({{ 1726 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1727 NOSATURATE, UNSIGNED, &dspctl); 1728 }}); 1729 0x1: subu_ph({{ 1730 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1731 NOSATURATE, UNSIGNED, &dspctl); 1732 }}); 1733 0x2: addq_ph({{ 1734 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1735 NOSATURATE, SIGNED, &dspctl); 1736 }}); 1737 0x3: subq_ph({{ 1738 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1739 NOSATURATE, SIGNED, &dspctl); 1740 }}); 1741 0x4: addu_s_ph({{ 1742 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1743 SATURATE, UNSIGNED, &dspctl); 1744 }}); 1745 0x5: subu_s_ph({{ 1746 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1747 SATURATE, UNSIGNED, &dspctl); 1748 }}); 1749 0x6: addq_s_ph({{ 1750 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1751 SATURATE, SIGNED, &dspctl); 1752 }}); 1753 0x7: subq_s_ph({{ 1754 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1755 SATURATE, SIGNED, &dspctl); 1756 }}); 1757 } 1758 } 1759 0x2: decode OP_LO { 1760 format DspIntOp { 1761 0x0: addsc({{ 1762 int64_t dresult; 1763 dresult = Rs_ud + Rt_ud; 1764 Rd_sw = dresult<31:0>; 1765 dspctl = insertBits(dspctl, 13, 13, 1766 dresult<32:32>); 1767 }}); 1768 0x1: addwc({{ 1769 int64_t dresult; 1770 dresult = Rs_sd + Rt_sd + dspctl<13:13>; 1771 Rd_sw = dresult<31:0>; 1772 if (dresult<32:32> != dresult<31:31>) 1773 dspctl = insertBits(dspctl, 20, 20, 1); 1774 }}); 1775 0x2: modsub({{ 1776 Rd_sw = (Rs_sw == 0) ? Rt_sw<23:8> : 1777 Rs_sw - Rt_sw<7:0>; 1778 }}); 1779 0x4: raddu_w_qb({{ 1780 Rd_uw = Rs_uw<31:24> + Rs_uw<23:16> + 1781 Rs_uw<15:8> + Rs_uw<7:0>; 1782 }}); 1783 0x6: addq_s_w({{ 1784 Rd_sw = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W, 1785 SATURATE, SIGNED, &dspctl); 1786 }}); 1787 0x7: subq_s_w({{ 1788 Rd_sw = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W, 1789 SATURATE, SIGNED, &dspctl); 1790 }}); 1791 } 1792 } 1793 0x3: decode OP_LO { 1794 format DspIntOp { 1795 0x4: muleq_s_w_phl({{ 1796 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1797 MODE_L, &dspctl); 1798 }}, IntMultOp); 1799 0x5: muleq_s_w_phr({{ 1800 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1801 MODE_R, &dspctl); 1802 }}, IntMultOp); 1803 0x6: mulq_s_ph({{ 1804 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1805 SATURATE, NOROUND, &dspctl); 1806 }}, IntMultOp); 1807 0x7: mulq_rs_ph({{ 1808 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1809 SATURATE, ROUND, &dspctl); 1810 }}, IntMultOp); 1811 } 1812 } 1813 } 1814 1815 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1816 //(DSP ASE MANUAL) 1817 0x1: decode OP_HI { 1818 0x0: decode OP_LO { 1819 format DspIntOp { 1820 0x0: cmpu_eq_qb({{ 1821 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1822 UNSIGNED, CMP_EQ, &dspctl); 1823 }}); 1824 0x1: cmpu_lt_qb({{ 1825 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1826 UNSIGNED, CMP_LT, &dspctl); 1827 }}); 1828 0x2: cmpu_le_qb({{ 1829 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1830 UNSIGNED, CMP_LE, &dspctl); 1831 }}); 1832 0x3: pick_qb({{ 1833 Rd_uw = dspPick(Rs_uw, Rt_uw, 1834 SIMD_FMT_QB, &dspctl); 1835 }}); 1836 0x4: cmpgu_eq_qb({{ 1837 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1838 UNSIGNED, CMP_EQ ); 1839 }}); 1840 0x5: cmpgu_lt_qb({{ 1841 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1842 UNSIGNED, CMP_LT); 1843 }}); 1844 0x6: cmpgu_le_qb({{ 1845 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1846 UNSIGNED, CMP_LE); 1847 }}); 1848 } 1849 } 1850 0x1: decode OP_LO { 1851 format DspIntOp { 1852 0x0: cmp_eq_ph({{ 1853 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1854 SIGNED, CMP_EQ, &dspctl); 1855 }}); 1856 0x1: cmp_lt_ph({{ 1857 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1858 SIGNED, CMP_LT, &dspctl); 1859 }}); 1860 0x2: cmp_le_ph({{ 1861 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1862 SIGNED, CMP_LE, &dspctl); 1863 }}); 1864 0x3: pick_ph({{ 1865 Rd_uw = dspPick(Rs_uw, Rt_uw, 1866 SIMD_FMT_PH, &dspctl); 1867 }}); 1868 0x4: precrq_qb_ph({{ 1869 Rd_uw = Rs_uw<31:24> << 24 | 1870 Rs_uw<15:8> << 16 | 1871 Rt_uw<31:24> << 8 | 1872 Rt_uw<15:8>; 1873 }}); 1874 0x5: precr_qb_ph({{ 1875 Rd_uw = Rs_uw<23:16> << 24 | 1876 Rs_uw<7:0> << 16 | 1877 Rt_uw<23:16> << 8 | 1878 Rt_uw<7:0>; 1879 }}); 1880 0x6: packrl_ph({{ 1881 Rd_uw = dspPack(Rs_uw, Rt_uw, SIMD_FMT_PH); 1882 }}); 1883 0x7: precrqu_s_qb_ph({{ 1884 Rd_uw = dspPrecrqu(Rs_uw, Rt_uw, &dspctl); 1885 }}); 1886 } 1887 } 1888 0x2: decode OP_LO { 1889 format DspIntOp { 1890 0x4: precrq_ph_w({{ 1891 Rd_uw = Rs_uw<31:16> << 16 | Rt_uw<31:16>; 1892 }}); 1893 0x5: precrq_rs_ph_w({{ 1894 Rd_uw = dspPrecrq(Rs_uw, Rt_uw, 1895 SIMD_FMT_W, &dspctl); 1896 }}); 1897 } 1898 } 1899 0x3: decode OP_LO { 1900 format DspIntOp { 1901 0x0: cmpgdu_eq_qb({{ 1902 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1903 UNSIGNED, CMP_EQ, &dspctl); 1904 }}); 1905 0x1: cmpgdu_lt_qb({{ 1906 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1907 UNSIGNED, CMP_LT, &dspctl); 1908 }}); 1909 0x2: cmpgdu_le_qb({{ 1910 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1911 UNSIGNED, CMP_LE, &dspctl); 1912 }}); 1913 0x6: precr_sra_ph_w({{ 1914 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1915 SIMD_FMT_W, NOROUND); 1916 }}); 1917 0x7: precr_sra_r_ph_w({{ 1918 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1919 SIMD_FMT_W, ROUND); 1920 }}); 1921 } 1922 } 1923 } 1924 1925 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1926 //(DSP ASE MANUAL) 1927 0x2: decode OP_HI { 1928 0x0: decode OP_LO { 1929 format DspIntOp { 1930 0x1: absq_s_qb({{ 1931 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl); 1932 }}); 1933 0x2: repl_qb({{ 1934 Rd_uw = RS_RT<7:0> << 24 | 1935 RS_RT<7:0> << 16 | 1936 RS_RT<7:0> << 8 | 1937 RS_RT<7:0>; 1938 }}); 1939 0x3: replv_qb({{ 1940 Rd_sw = Rt_uw<7:0> << 24 | 1941 Rt_uw<7:0> << 16 | 1942 Rt_uw<7:0> << 8 | 1943 Rt_uw<7:0>; 1944 }}); 1945 0x4: precequ_ph_qbl({{ 1946 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1947 SIMD_FMT_PH, SIGNED, MODE_L); 1948 }}); 1949 0x5: precequ_ph_qbr({{ 1950 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1951 SIMD_FMT_PH, SIGNED, MODE_R); 1952 }}); 1953 0x6: precequ_ph_qbla({{ 1954 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1955 SIMD_FMT_PH, SIGNED, MODE_LA); 1956 }}); 1957 0x7: precequ_ph_qbra({{ 1958 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1959 SIMD_FMT_PH, SIGNED, MODE_RA); 1960 }}); 1961 } 1962 } 1963 0x1: decode OP_LO { 1964 format DspIntOp { 1965 0x1: absq_s_ph({{ 1966 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl); 1967 }}); 1968 0x2: repl_ph({{ 1969 Rd_uw = (sext<10>(RS_RT))<15:0> << 16 | 1970 (sext<10>(RS_RT))<15:0>; 1971 }}); 1972 0x3: replv_ph({{ 1973 Rd_uw = Rt_uw<15:0> << 16 | 1974 Rt_uw<15:0>; 1975 }}); 1976 0x4: preceq_w_phl({{ 1977 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1978 SIMD_FMT_W, SIGNED, MODE_L); 1979 }}); 1980 0x5: preceq_w_phr({{ 1981 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1982 SIMD_FMT_W, SIGNED, MODE_R); 1983 }}); 1984 } 1985 } 1986 0x2: decode OP_LO { 1987 format DspIntOp { 1988 0x1: absq_s_w({{ 1989 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl); 1990 }}); 1991 } 1992 } 1993 0x3: decode OP_LO { 1994 0x3: IntOp::bitrev({{ 1995 Rd_uw = bitrev( Rt_uw<15:0> ); 1996 }}); 1997 format DspIntOp { 1998 0x4: preceu_ph_qbl({{ 1999 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 2000 UNSIGNED, SIMD_FMT_PH, 2001 UNSIGNED, MODE_L); 2002 }}); 2003 0x5: preceu_ph_qbr({{ 2004 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 2005 UNSIGNED, SIMD_FMT_PH, 2006 UNSIGNED, MODE_R ); 2007 }}); 2008 0x6: preceu_ph_qbla({{ 2009 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 2010 UNSIGNED, SIMD_FMT_PH, 2011 UNSIGNED, MODE_LA ); 2012 }}); 2013 0x7: preceu_ph_qbra({{ 2014 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 2015 UNSIGNED, SIMD_FMT_PH, 2016 UNSIGNED, MODE_RA); 2017 }}); 2018 } 2019 } 2020 } 2021 2022 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 2023 //(DSP ASE MANUAL) 2024 0x3: decode OP_HI { 2025 0x0: decode OP_LO { 2026 format DspIntOp { 2027 0x0: shll_qb({{ 2028 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_QB, 2029 NOSATURATE, UNSIGNED, &dspctl); 2030 }}); 2031 0x1: shrl_qb({{ 2032 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_QB, 2033 UNSIGNED); 2034 }}); 2035 0x2: shllv_qb({{ 2036 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB, 2037 NOSATURATE, UNSIGNED, &dspctl); 2038 }}); 2039 0x3: shrlv_qb({{ 2040 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB, 2041 UNSIGNED); 2042 }}); 2043 0x4: shra_qb({{ 2044 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2045 NOROUND, SIGNED, &dspctl); 2046 }}); 2047 0x5: shra_r_qb({{ 2048 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2049 ROUND, SIGNED, &dspctl); 2050 }}); 2051 0x6: shrav_qb({{ 2052 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2053 NOROUND, SIGNED, &dspctl); 2054 }}); 2055 0x7: shrav_r_qb({{ 2056 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2057 ROUND, SIGNED, &dspctl); 2058 }}); 2059 } 2060 } 2061 0x1: decode OP_LO { 2062 format DspIntOp { 2063 0x0: shll_ph({{ 2064 Rd_uw = dspShll(Rt_uw, RS, SIMD_FMT_PH, 2065 NOSATURATE, SIGNED, &dspctl); 2066 }}); 2067 0x1: shra_ph({{ 2068 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2069 NOROUND, SIGNED, &dspctl); 2070 }}); 2071 0x2: shllv_ph({{ 2072 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2073 NOSATURATE, SIGNED, &dspctl); 2074 }}); 2075 0x3: shrav_ph({{ 2076 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2077 NOROUND, SIGNED, &dspctl); 2078 }}); 2079 0x4: shll_s_ph({{ 2080 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_PH, 2081 SATURATE, SIGNED, &dspctl); 2082 }}); 2083 0x5: shra_r_ph({{ 2084 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2085 ROUND, SIGNED, &dspctl); 2086 }}); 2087 0x6: shllv_s_ph({{ 2088 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2089 SATURATE, SIGNED, &dspctl); 2090 }}); 2091 0x7: shrav_r_ph({{ 2092 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2093 ROUND, SIGNED, &dspctl); 2094 }}); 2095 } 2096 } 2097 0x2: decode OP_LO { 2098 format DspIntOp { 2099 0x4: shll_s_w({{ 2100 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_W, 2101 SATURATE, SIGNED, &dspctl); 2102 }}); 2103 0x5: shra_r_w({{ 2104 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_W, 2105 ROUND, SIGNED, &dspctl); 2106 }}); 2107 0x6: shllv_s_w({{ 2108 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W, 2109 SATURATE, SIGNED, &dspctl); 2110 }}); 2111 0x7: shrav_r_w({{ 2112 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W, 2113 ROUND, SIGNED, &dspctl); 2114 }}); 2115 } 2116 } 2117 0x3: decode OP_LO { 2118 format DspIntOp { 2119 0x1: shrl_ph({{ 2120 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_PH, 2121 UNSIGNED); 2122 }}); 2123 0x3: shrlv_ph({{ 2124 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH, 2125 UNSIGNED); 2126 }}); 2127 } 2128 } 2129 } 2130 } 2131 2132 0x3: decode FUNCTION_LO { 2133 2134 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2135 //(DSP ASE Rev2 Manual) 2136 0x0: decode OP_HI { 2137 0x0: decode OP_LO { 2138 format DspIntOp { 2139 0x0: adduh_qb({{ 2140 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2141 NOROUND, UNSIGNED); 2142 }}); 2143 0x1: subuh_qb({{ 2144 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2145 NOROUND, UNSIGNED); 2146 }}); 2147 0x2: adduh_r_qb({{ 2148 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2149 ROUND, UNSIGNED); 2150 }}); 2151 0x3: subuh_r_qb({{ 2152 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2153 ROUND, UNSIGNED); 2154 }}); 2155 } 2156 } 2157 0x1: decode OP_LO { 2158 format DspIntOp { 2159 0x0: addqh_ph({{ 2160 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2161 NOROUND, SIGNED); 2162 }}); 2163 0x1: subqh_ph({{ 2164 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2165 NOROUND, SIGNED); 2166 }}); 2167 0x2: addqh_r_ph({{ 2168 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2169 ROUND, SIGNED); 2170 }}); 2171 0x3: subqh_r_ph({{ 2172 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2173 ROUND, SIGNED); 2174 }}); 2175 0x4: mul_ph({{ 2176 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2177 NOSATURATE, &dspctl); 2178 }}, IntMultOp); 2179 0x6: mul_s_ph({{ 2180 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2181 SATURATE, &dspctl); 2182 }}, IntMultOp); 2183 } 2184 } 2185 0x2: decode OP_LO { 2186 format DspIntOp { 2187 0x0: addqh_w({{ 2188 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2189 NOROUND, SIGNED); 2190 }}); 2191 0x1: subqh_w({{ 2192 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2193 NOROUND, SIGNED); 2194 }}); 2195 0x2: addqh_r_w({{ 2196 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2197 ROUND, SIGNED); 2198 }}); 2199 0x3: subqh_r_w({{ 2200 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2201 ROUND, SIGNED); 2202 }}); 2203 0x6: mulq_s_w({{ 2204 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2205 SATURATE, NOROUND, &dspctl); 2206 }}, IntMultOp); 2207 0x7: mulq_rs_w({{ 2208 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2209 SATURATE, ROUND, &dspctl); 2210 }}, IntMultOp); 2211 } 2212 } 2213 } 2214 } 2215 2216 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2217 0x4: decode SA { 2218 format BasicOp { 2219 0x02: wsbh({{ 2220 Rd_uw = Rt_uw<23:16> << 24 | 2221 Rt_uw<31:24> << 16 | 2222 Rt_uw<7:0> << 8 | 2223 Rt_uw<15:8>; 2224 }}); 2225 0x10: seb({{ Rd_sw = Rt_sb; }}); 2226 0x18: seh({{ Rd_sw = Rt_sh; }}); 2227 } 2228 } 2229 2230 0x6: decode FUNCTION_LO { 2231 2232 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2233 //(DSP ASE MANUAL) 2234 0x0: decode OP_HI { 2235 0x0: decode OP_LO { 2236 format DspHiLoOp { 2237 0x0: dpa_w_ph({{ 2238 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2239 SIMD_FMT_PH, SIGNED, MODE_L); 2240 }}, IntMultOp); 2241 0x1: dps_w_ph({{ 2242 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2243 SIMD_FMT_PH, SIGNED, MODE_L); 2244 }}, IntMultOp); 2245 0x2: mulsa_w_ph({{ 2246 dspac = dspMulsa(dspac, Rs_sw, Rt_sw, 2247 ACDST, SIMD_FMT_PH ); 2248 }}, IntMultOp); 2249 0x3: dpau_h_qbl({{ 2250 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2251 SIMD_FMT_QB, UNSIGNED, MODE_L); 2252 }}, IntMultOp); 2253 0x4: dpaq_s_w_ph({{ 2254 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2255 ACDST, SIMD_FMT_PH, 2256 SIMD_FMT_W, NOSATURATE, 2257 MODE_L, &dspctl); 2258 }}, IntMultOp); 2259 0x5: dpsq_s_w_ph({{ 2260 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2261 ACDST, SIMD_FMT_PH, 2262 SIMD_FMT_W, NOSATURATE, 2263 MODE_L, &dspctl); 2264 }}, IntMultOp); 2265 0x6: mulsaq_s_w_ph({{ 2266 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw, 2267 ACDST, SIMD_FMT_PH, 2268 &dspctl); 2269 }}, IntMultOp); 2270 0x7: dpau_h_qbr({{ 2271 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2272 SIMD_FMT_QB, UNSIGNED, MODE_R); 2273 }}, IntMultOp); 2274 } 2275 } 2276 0x1: decode OP_LO { 2277 format DspHiLoOp { 2278 0x0: dpax_w_ph({{ 2279 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2280 SIMD_FMT_PH, SIGNED, MODE_X); 2281 }}, IntMultOp); 2282 0x1: dpsx_w_ph({{ 2283 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2284 SIMD_FMT_PH, SIGNED, MODE_X); 2285 }}, IntMultOp); 2286 0x3: dpsu_h_qbl({{ 2287 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2288 SIMD_FMT_QB, UNSIGNED, MODE_L); 2289 }}, IntMultOp); 2290 0x4: dpaq_sa_l_w({{ 2291 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2292 ACDST, SIMD_FMT_W, 2293 SIMD_FMT_L, SATURATE, 2294 MODE_L, &dspctl); 2295 }}, IntMultOp); 2296 0x5: dpsq_sa_l_w({{ 2297 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2298 ACDST, SIMD_FMT_W, 2299 SIMD_FMT_L, SATURATE, 2300 MODE_L, &dspctl); 2301 }}, IntMultOp); 2302 0x7: dpsu_h_qbr({{ 2303 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2304 SIMD_FMT_QB, UNSIGNED, MODE_R); 2305 }}, IntMultOp); 2306 } 2307 } 2308 0x2: decode OP_LO { 2309 format DspHiLoOp { 2310 0x0: maq_sa_w_phl({{ 2311 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2312 ACDST, SIMD_FMT_PH, 2313 MODE_L, SATURATE, &dspctl); 2314 }}, IntMultOp); 2315 0x2: maq_sa_w_phr({{ 2316 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2317 ACDST, SIMD_FMT_PH, 2318 MODE_R, SATURATE, &dspctl); 2319 }}, IntMultOp); 2320 0x4: maq_s_w_phl({{ 2321 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2322 ACDST, SIMD_FMT_PH, 2323 MODE_L, NOSATURATE, &dspctl); 2324 }}, IntMultOp); 2325 0x6: maq_s_w_phr({{ 2326 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2327 ACDST, SIMD_FMT_PH, 2328 MODE_R, NOSATURATE, &dspctl); 2329 }}, IntMultOp); 2330 } 2331 } 2332 0x3: decode OP_LO { 2333 format DspHiLoOp { 2334 0x0: dpaqx_s_w_ph({{ 2335 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2336 ACDST, SIMD_FMT_PH, 2337 SIMD_FMT_W, NOSATURATE, 2338 MODE_X, &dspctl); 2339 }}, IntMultOp); 2340 0x1: dpsqx_s_w_ph({{ 2341 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2342 ACDST, SIMD_FMT_PH, 2343 SIMD_FMT_W, NOSATURATE, 2344 MODE_X, &dspctl); 2345 }}, IntMultOp); 2346 0x2: dpaqx_sa_w_ph({{ 2347 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2348 ACDST, SIMD_FMT_PH, 2349 SIMD_FMT_W, SATURATE, 2350 MODE_X, &dspctl); 2351 }}, IntMultOp); 2352 0x3: dpsqx_sa_w_ph({{ 2353 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2354 ACDST, SIMD_FMT_PH, 2355 SIMD_FMT_W, SATURATE, 2356 MODE_X, &dspctl); 2357 }}, IntMultOp); 2358 } 2359 } 2360 } 2361 2362 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2363 0x1: decode OP_HI { 2364 0x0: decode OP_LO { 2365 format IntOp { 2366 0x0: append({{ 2367 Rt_uw = (Rt_uw << RD) | bits(Rs_uw, RD - 1, 0); 2368 }}); 2369 0x1: prepend({{ 2370 Rt_uw = (Rt_uw >> RD) | 2371 (bits(Rs_uw, RD - 1, 0) << (32 - RD)); 2372 }}); 2373 } 2374 } 2375 0x2: decode OP_LO { 2376 format IntOp { 2377 0x0: balign({{ 2378 Rt_uw = (Rt_uw << (8 * BP)) | 2379 (Rs_uw >> (8 * (4 - BP))); 2380 }}); 2381 } 2382 } 2383 } 2384 2385 } 2386 0x7: decode FUNCTION_LO { 2387 2388 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2389 //(DSP ASE MANUAL) 2390 0x0: decode OP_HI { 2391 0x0: decode OP_LO { 2392 format DspHiLoOp { 2393 0x0: extr_w({{ 2394 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2395 NOROUND, NOSATURATE, &dspctl); 2396 }}); 2397 0x1: extrv_w({{ 2398 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2399 NOROUND, NOSATURATE, &dspctl); 2400 }}); 2401 0x2: extp({{ 2402 Rt_uw = dspExtp(dspac, RS, &dspctl); 2403 }}); 2404 0x3: extpv({{ 2405 Rt_uw = dspExtp(dspac, Rs_uw, &dspctl); 2406 }}); 2407 0x4: extr_r_w({{ 2408 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2409 ROUND, NOSATURATE, &dspctl); 2410 }}); 2411 0x5: extrv_r_w({{ 2412 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2413 ROUND, NOSATURATE, &dspctl); 2414 }}); 2415 0x6: extr_rs_w({{ 2416 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2417 ROUND, SATURATE, &dspctl); 2418 }}); 2419 0x7: extrv_rs_w({{ 2420 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2421 ROUND, SATURATE, &dspctl); 2422 }}); 2423 } 2424 } 2425 0x1: decode OP_LO { 2426 format DspHiLoOp { 2427 0x2: extpdp({{ 2428 Rt_uw = dspExtpd(dspac, RS, &dspctl); 2429 }}); 2430 0x3: extpdpv({{ 2431 Rt_uw = dspExtpd(dspac, Rs_uw, &dspctl); 2432 }}); 2433 0x6: extr_s_h({{ 2434 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2435 NOROUND, SATURATE, &dspctl); 2436 }}); 2437 0x7: extrv_s_h({{ 2438 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, Rs_uw, 2439 NOROUND, SATURATE, &dspctl); 2440 }}); 2441 } 2442 } 2443 0x2: decode OP_LO { 2444 format DspIntOp { 2445 0x2: rddsp({{ 2446 Rd_uw = readDSPControl(&dspctl, RDDSPMASK); 2447 }}); 2448 0x3: wrdsp({{ 2449 writeDSPControl(&dspctl, Rs_uw, WRDSPMASK); 2450 }}); 2451 } 2452 } 2453 0x3: decode OP_LO { 2454 format DspHiLoOp { 2455 0x2: shilo({{ 2456 if ((int64_t)sext<6>(HILOSA) < 0) { 2457 dspac = (uint64_t)dspac << 2458 -sext<6>(HILOSA); 2459 } else { 2460 dspac = (uint64_t)dspac >> 2461 sext<6>(HILOSA); 2462 } 2463 }}); 2464 0x3: shilov({{ 2465 if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) { 2466 dspac = (uint64_t)dspac << 2467 -sext<6>(Rs_sw<5:0>); 2468 } else { 2469 dspac = (uint64_t)dspac >> 2470 sext<6>(Rs_sw<5:0>); 2471 } 2472 }}); 2473 0x7: mthlip({{ 2474 dspac = dspac << 32; 2475 dspac |= Rs_uw; 2476 dspctl = insertBits(dspctl, 5, 0, 2477 dspctl<5:0> + 32); 2478 }}); 2479 } 2480 } 2481 } 2482 0x3: decode OP default FailUnimpl::rdhwr() { 2483 0x0: decode FullSystemInt { 2484 0: decode RD { 2485 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2486 } 2487 } 2488 } 2489 } 2490 } 2491 } 2492 2493 0x4: decode OPCODE_LO { 2494 format LoadMemory { 2495 0x0: lb({{ Rt_sw = Mem_sb; }}); 2496 0x1: lh({{ Rt_sw = Mem_sh; }}); 2497 0x3: lw({{ Rt_sw = Mem_sw; }}); 2498 0x4: lbu({{ Rt_uw = Mem_ub;}}); 2499 0x5: lhu({{ Rt_uw = Mem_uh; }}); 2500 } 2501 2502 format LoadUnalignedMemory { 2503 0x2: lwl({{ 2504 uint32_t mem_shift = 24 - (8 * byte_offset); 2505 Rt_uw = mem_word << mem_shift | (Rt_uw & mask(mem_shift)); 2506 }}); 2507 0x6: lwr({{ 2508 uint32_t mem_shift = 8 * byte_offset; 2509 Rt_uw = (Rt_uw & (mask(mem_shift) << (32 - mem_shift))) | 2510 (mem_word >> mem_shift); 2511 }}); 2512 } 2513 } 2514 2515 0x5: decode OPCODE_LO { 2516 format StoreMemory { 2517 0x0: sb({{ Mem_ub = Rt<7:0>; }}); 2518 0x1: sh({{ Mem_uh = Rt<15:0>; }}); 2519 0x3: sw({{ Mem_uw = Rt<31:0>; }}); 2520 } 2521 2522 format StoreUnalignedMemory { 2523 0x2: swl({{ 2524 uint32_t reg_shift = 24 - (8 * byte_offset); 2525 uint32_t mem_shift = 32 - reg_shift; 2526 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2527 (Rt_uw >> reg_shift); 2528 }}); 2529 0x6: swr({{ 2530 uint32_t reg_shift = 8 * byte_offset; 2531 mem_word = Rt_uw << reg_shift | 2532 (mem_word & (mask(reg_shift))); 2533 }}); 2534 } 2535 format CP0Control { 2536 0x7: cache({{ 2537 //Addr CacheEA = Rs_uw + OFFSET; 2538 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2539 }}); 2540 } 2541 } 2542 2543 0x6: decode OPCODE_LO { 2544 format LoadMemory { 2545 0x0: ll({{ Rt_uw = Mem_uw; }}, mem_flags=LLSC); 2546 0x1: lwc1({{ Ft_uw = Mem_uw; }}); 2547 0x5: ldc1({{ Ft_ud = Mem_ud; }}); 2548 } 2549 0x2: CP2Unimpl::lwc2(); 2550 0x6: CP2Unimpl::ldc2(); 2551 0x3: Prefetch::pref(); 2552 } 2553 2554 2555 0x7: decode OPCODE_LO { 2556 0x0: StoreCond::sc({{ Mem_uw = Rt_uw; }}, 2557 {{ uint64_t tmp = write_result; 2558 Rt_uw = (tmp == 0 || tmp == 1) ? tmp : Rt_uw; 2559 }}, mem_flags=LLSC, 2560 inst_flags = IsStoreConditional); 2561 format StoreMemory { 2562 0x1: swc1({{ Mem_uw = Ft_uw; }}); 2563 0x5: sdc1({{ Mem_ud = Ft_ud; }}); 2564 } 2565 0x2: CP2Unimpl::swc2(); 2566 0x6: CP2Unimpl::sdc2(); 2567 } 2568} 2569 2570
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