1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30// Brett Miller
31
32////////////////////////////////////////////////////////////////////
33//
34// The actual MIPS32 ISA decoder
35// -----------------------------
36// The following instructions are specified in the MIPS32 ISA
37// Specification. Decoding closely follows the style specified
38// in the MIPS32 ISA specification document starting with Table
39// A-2 (document available @ http://www.mips.com)

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52
53 format BasicOp {
54 //Table A-3 Note: "Specific encodings of the rd, rs, and
55 //rt fields are used to distinguish SLL, SSNOP, and EHB
56 //functions
57 0x0: decode RS {
58 0x0: decode RT_RD {
59 0x0: decode SA default Nop::nop() {
60 0x1: WarnUnimpl::ssnop();
61 0x3: WarnUnimpl::ehb();
62 }
63 default: sll({{ Rd = Rt.uw << SA; }});
64 }
65 }
66
67 0x2: decode RS_SRL {
68 0x0:decode SRL {
69 0: srl({{ Rd = Rt.uw >> SA; }});

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114 }
115 }
116
117 0x1: decode FUNCTION_LO {
118 //Table A-3 Note: "Specific encodings of the hint field are
119 //used to distinguish JR from JR.HB and JALR from JALR.HB"
120 format Jump {
121 0x0: decode HINT {
122 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
123 default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
124 }
125
126 0x1: decode HINT {
127 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
128 , ClearHazards);
129 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
130 }
131 }
132
133 format BasicOp {
134 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
135 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
136 0x4: syscall({{ xc->syscall(R2); }},
137 IsSerializeAfter, IsNonSpeculative,
138 IsSyscall);
139 0x7: sync({{ ; }}, IsMemBarrier);
140 }
141
142 format FailUnimpl {
143 0x5: break();
144 }
145 }
146
147 0x2: decode FUNCTION_LO {
148 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
149 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
150 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
151 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
152 }
153
154 0x3: decode FUNCTION_LO {
155 format HiLoRdSelValOp {
156 0x0: mult({{ val = Rs.sd * Rt.sd; }});
157 0x1: multu({{ val = Rs.ud * Rt.ud; }});
158 }
159
160 format HiLoOp {
161 0x2: div({{ if (Rt.sd != 0) {
162 HI0 = Rs.sd % Rt.sd;
163 LO0 = Rs.sd / Rt.sd;
164 }
165 }});
166 0x3: divu({{ if (Rt.ud != 0) {
167 HI0 = Rs.ud % Rt.ud;
168 LO0 = Rs.ud / Rt.ud;
169 }
170 }});
171 }
172 }
173
174 0x4: decode HINT {
175 0x0: decode FUNCTION_LO {
176 format IntOp {
177 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
178 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
179 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
180 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
181 0x4: and({{ Rd = Rs & Rt;}});
182 0x5: or({{ Rd = Rs | Rt;}});
183 0x6: xor({{ Rd = Rs ^ Rt;}});
184 0x7: nor({{ Rd = ~(Rs | Rt);}});
185 }
186 }
187 }

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195 }
196 }
197
198 0x6: decode FUNCTION_LO {
199 format Trap {
200 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
201 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
202 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
203 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
204 0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
205 0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
206 }
207 }
208 }
209
210 0x1: decode REGIMM_HI {
211 0x0: decode REGIMM_LO {
212 format Branch {
213 0x0: bltz({{ cond = (Rs.sw < 0); }});
214 0x1: bgez({{ cond = (Rs.sw >= 0); }});
215 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
216 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
217 }
218 }
219
220 0x1: decode REGIMM_LO {
221 format Trap {
222 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
223 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
224 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
225 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
226 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
227 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
228 }
229 }
230
231 0x2: decode REGIMM_LO {
232 format Branch {
233 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
234 0x1: decode RS {
235 0x0: bal ({{ cond = 1; }}, IsCall, Link);

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263 0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
264 0x6: blez({{ cond = (Rs.sw <= 0); }});
265 0x7: bgtz({{ cond = (Rs.sw > 0); }});
266 }
267 }
268
269 0x1: decode OPCODE_LO {
270 format IntImmOp {
271 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
272 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
273 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
274
275 //Edited to include MIPS AVP Pass/Fail instructions and
276 //default to the sltiu instruction
277 0x3: decode RS_RT_INTIMM {
278 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }});
279 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }});

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289 }
290 }
291 }
292
293 0x2: decode OPCODE_LO {
294 //Table A-11 MIPS32 COP0 Encoding of rs Field
295 0x0: decode RS_MSB {
296 0x0: decode RS {
297 format CP0Control {
298 0x0: mfc0({{ Rt = CP0_RD_SEL; }});
299 0x4: mtc0({{ CP0_RD_SEL = Rt; }});
300 }
301
302
303 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
304 0x8: decode MT_U {
305 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
306 Ctrl_Base_DepTag);
307 }});
308 0x1: decode SEL {
309 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
310 0x1: decode RT {

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316 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
317 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
318 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
319 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
320 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
321 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
322 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
323 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
324 }
325 0x2: decode MT_H {
326 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
327 FP_Base_DepTag);
328 }});
329 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
330 FP_Base_DepTag);
331 }});
332 }
333 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
334 FP_Base_DepTag);
335 switch (RT)
336 {
337 case 0:
338 data = xc->readRegOtherThread(MipsISA::FIR +
339 Ctrl_Base_DepTag);
340 break;

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352 break;
353 case 31:
354 data = fcsr_val;
355 break;
356 default:
357 fatal("FP Control Value (%d) Not Valid");
358 }
359 }});
360 }
361 }
362 }
363
364 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
365 0xC: decode MT_U {
366 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
367 Rt);
368 }});
369 0x1: decode SEL {

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399 Rt);
400 }});
401 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
402 Rt);
403 }});
404 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
405 }});
406 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
407 }
408 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
409 FP_Base_DepTag);
410 data = insertBits(data, top_bit, bottom_bit, Rt);
411 xc->setRegOtherThread(RD + FP_Base_DepTag, data);
412 }});
413 0x3: cttc1({{ uint32_t data;
414 switch (RD)

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441 break;
442
443 default:
444 panic("FP Control Value (%d) Not Available. Ignoring Access to"
445 "Floating Control Status Register", FS);
446 }
447 xc->setRegOtherThread(FCSR, data);
448 }});
449 }
450 }
451 }
452
453
454 0xB: decode RD {
455 format MT_Control {
456 0x0: decode POS {

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461 MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
462 }
463 }});
464 0x1: evpe({{ Rt = MVPControl;
465 if (VPEConf0<VPEC0_MVP:> == 1) {
466 MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
467 }
468 }});
469 }
470 }
471 }
472
473 0x1: decode POS {
474 0xF: decode SEL {
475 0x1: decode SC {
476 0x0: dmt({{ Rt = VPEControl;
477 VPEControl = insertBits(VPEControl, VPEC_TE, 0);
478 }});
479 0x1: emt({{ Rt = VPEControl;
480 VPEControl = insertBits(VPEControl, VPEC_TE, 1);
481 }});
482
483 }
484 }
485 }
486 }
487 0xC: decode POS {
488 0x0: decode SC {
489 0x0: CP0Control::di({{
490 if(Config_AR >= 1) // Rev 2.0 or beyond?
491 {
492 Rt = Status;

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503 Rt = Status;
504 Status_IE = 1;
505 }
506 else
507 {
508 fault = new ReservedInstructionFault();
509 }
510 }});
511 }
512 }
513 }
514
515 format CP0Control {
516 0xA: rdpgpr({{
517 if(Config_AR >= 1)
518 { // Rev 2 of the architecture
519 Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
520 }
521 else
522 {
523 fault = new ReservedInstructionFault();
524 }
525 }});
526 0xE: wrpgpr({{
527 if(Config_AR >= 1)
528 { // Rev 2 of the architecture
529 xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
530 }
531 else
532 {
533 fault = new ReservedInstructionFault();
534 }
535
536 }});
537
538 }
539
540 }
541
542 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
543 0x1: decode FUNCTION {
544 format CP0Control {
545 0x18: eret({{
546 if(Status_ERL == 1){
547 Status_ERL = 0;
548 NPC = ErrorEPC;
549 }
550 else{
551 NPC = EPC;
552 Status_EXL = 0;
553 if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
554 SRSCtl_CSS = SRSCtl_PSS;
555 }
556 }
557 // LLFlag = 0;
558 // ClearHazards(); ?
559 }});
560
561 0x1F: deret({{
562 //if(Debug_DM == 1){
563 //Debug_DM = 1;
564 //Debug_IEXI = 0;
565 //NPC = DEPC;
566 //}
567 panic("deret not implemented");
568 }});
569 }
570
571 format FailUnimpl {
572 0x01: tlbr(); // Need to hook up to TLB
573 0x02: tlbwi(); // Need to hook up to TLB
574 0x06: tlbwr();// Need to hook up to TLB
575 0x08: tlbp();// Need to hook up to TLB
576
577 0x20: wait();
578 }
579
580 }
581 }
582
583 //Table A-13 MIPS32 COP1 Encoding of rs Field
584 0x1: decode RS_MSB {
585
586 0x0: decode RS_HI {
587 0x0: decode RS_LO {

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602 break;
603 case 28:
604 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
605 break;
606 case 31:
607 Rt = FCSR;
608 break;
609 default:
610 panic("FP Control Value (%d) Not Valid");
611 }
612 }});
613
614 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
615
616 0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
617
618 0x6: ctc1({{
619 switch (FS)

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653
654 0x7: mthc1({{
655 uint64_t fs_hi = Rt.uw;
656 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
657 Fs.ud = (fs_hi << 32) | fs_lo;
658 }});
659
660 }
661 }
662
663 0x1: decode ND {
664 format Branch {
665 0x0: decode TF {
666 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
667 }});
668 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
669 }});
670 }
671 0x1: decode TF {
672 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
673 }}, Likely);
674 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
675 }}, Likely);
676 }
677 }
678 }
679 }
680
681 0x1: decode RS_HI {
682 0x2: decode RS_LO {
683 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
684 //(( single-precision floating point))
685 0x0: decode FUNCTION_HI {
686 0x0: decode FUNCTION_LO {

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730 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
731 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
732 }
733
734 format FloatOp {
735 0x5: recip_s({{ Fd = 1 / Fs; }});
736 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
737 }
738 }
739
740 0x4: decode FUNCTION_LO {
741 format FloatConvertOp {
742 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
743 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
744 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
745 }
746
747 0x6: FloatOp::cvt_ps_s({{
748 Fd.ud = (uint64_t) Fs.uw << 32 |
749 (uint64_t) Ft.uw;
750 }});
751 }
752
753 0x6: decode FUNCTION_LO {
754 format FloatCompareOp {
755 0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
756 UnorderedFalse);
757 0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
758 UnorderedTrue);
759 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},

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846 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
847 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
848 }
849
850 format FloatOp {
851 0x5: recip_d({{ Fd.df = 1 / Fs.df }});
852 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
853 }
854 }
855
856 0x4: decode FUNCTION_LO {
857 format FloatConvertOp {
858 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
859 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
860 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
861 }
862 }
863
864 0x6: decode FUNCTION_LO {
865 format FloatCompareOp {
866 0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
867 UnorderedFalse);
868 0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
869 UnorderedTrue);

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897 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
898 UnorderedTrue, QnanException);
899 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
900 UnorderedFalse, QnanException);
901 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
902 UnorderedTrue, QnanException);
903 }
904 }
905 }
906
907 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
908 0x4: decode FUNCTION {
909 format FloatConvertOp {
910 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
911 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
912 0x26: FailUnimpl::cvt_ps_w();
913 }
914 }
915
916 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
917 //Note: "1. Format type L is legal only if 64-bit floating point operations
918 //are enabled."
919 0x5: decode FUNCTION_HI {
920 format FloatConvertOp {
921 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
922 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
923 0x26: FailUnimpl::cvt_ps_l();
924 }
925 }
926
927 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
928 //Note: "1. Format type PS is legal only if 64-bit floating point operations
929 //are enabled. "
930 0x6: decode FUNCTION_HI {
931 0x0: decode FUNCTION_LO {
932 format Float64Op {

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949 0x6: mov_ps({{
950 Fd1.sf = Fs1.sf;
951 Fd2.sf = Fs2.sf;
952 }});
953 0x7: neg_ps({{
954 Fd1.sf = -(Fs1.sf);
955 Fd2.sf = -(Fs2.sf);
956 }});
957 }
958 }
959
960 0x2: decode FUNCTION_LO {
961 0x1: decode MOVCF {
962 format Float64Op {
963 0x0: movf_ps({{
964 Fd1 = (getCondCode(FCSR, CC) == 0) ?
965 Fs1 : Fd1;
966 Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
967 Fs2 : Fd2;

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984 }});
985 0x3: movn_ps({{
986 Fd1 = (getCondCode(FCSR, CC) == 1) ?
987 Fs1 : Fd1;
988 Fd2 = (getCondCode(FCSR, CC) == 1) ?
989 Fs2 : Fd2;
990 }});
991 }
992
993 }
994
995 0x4: decode FUNCTION_LO {
996 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
997 }
998
999 0x5: decode FUNCTION_LO {
1000 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
1001
1002 format Float64Op {
1003 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1004 Ft1.uw;
1005 }});
1006 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1007 Ft2.uw;
1008 }});
1009 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1010 Ft1.uw;
1011 }});
1012 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1013 Ft2.uw;
1014 }});
1015 }
1016 }
1017
1018 0x6: decode FUNCTION_LO {
1019 format FloatPSCompareOp {
1020 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1021 UnorderedFalse);
1022 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1023 UnorderedTrue);

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1066 UnorderedFalse, QnanException);
1067 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1068 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1069 UnorderedTrue, QnanException);
1070 }
1071 }
1072 }
1073 }
1074 }
1075 }
1076
1077 //Table A-19 MIPS32 COP2 Encoding of rs Field
1078 0x2: decode RS_MSB {
1079 format FailUnimpl {
1080 0x0: decode RS_HI {
1081 0x0: decode RS_LO {
1082 0x0: mfc2();
1083 0x2: cfc2();
1084 0x3: mfhc2();
1085 0x4: mtc2();
1086 0x6: ctc2();
1087 0x7: mftc2();
1088 }
1089
1090 0x1: decode ND {
1091 0x0: decode TF {
1092 0x0: bc2f();
1093 0x1: bc2t();
1094 }
1095
1096 0x1: decode TF {
1097 0x0: bc2fl();
1098 0x1: bc2tl();
1099 }
1100 }
1101 }
1102 }
1103 }
1104
1105 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1106 //Note: "COP1X instructions are legal only if 64-bit floating point
1107 //operations are enabled."
1108 0x3: decode FUNCTION_HI {
1109 0x0: decode FUNCTION_LO {

--- 82 unchanged lines hidden (view full) ---

1192 }
1193
1194 0x3: decode OPCODE_LO {
1195 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1196 0x4: decode FUNCTION_HI {
1197 0x0: decode FUNCTION_LO {
1198 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
1199 Rd.sw = temp1<31:0>;
1200 }});
1201
1202 format HiLoRdSelValOp {
1203 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
1204 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
1205 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
1206 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
1207 }
1208 }
1209
1210 0x4: decode FUNCTION_LO {
1211 format BasicOp {
1212 0x0: clz({{ int cnt = 32;
1213 for (int idx = 31; idx >= 0; idx--) {
1214 if( Rs<idx:idx> == 1) {

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1281 NOSATURATE, UNSIGNED, &dspctl ); }});
1282 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1283 NOSATURATE, UNSIGNED, &dspctl ); }});
1284 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1285 SATURATE, UNSIGNED, &dspctl ); }});
1286 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1287 SATURATE, UNSIGNED, &dspctl ); }});
1288 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1289 MODE_L, &dspctl ); }});
1290 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1291 MODE_R, &dspctl ); }});
1292 }
1293 }
1294 0x1: decode OP_LO {
1295 format DspIntOp {
1296 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1297 NOSATURATE, UNSIGNED, &dspctl ); }});
1298 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1299 NOSATURATE, UNSIGNED, &dspctl ); }});

--- 30 unchanged lines hidden (view full) ---

1330 SATURATE, SIGNED, &dspctl ); }});
1331 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W,
1332 SATURATE, SIGNED, &dspctl ); }});
1333 }
1334 }
1335 0x3: decode OP_LO {
1336 format DspIntOp {
1337 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1338 MODE_L, &dspctl ); }});
1339 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1340 MODE_R, &dspctl ); }});
1341 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1342 SATURATE, NOROUND, &dspctl ); }});
1343 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1344 SATURATE, ROUND, &dspctl ); }});
1345 }
1346 }
1347 }
1348
1349 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL)
1350 0x1: decode OP_HI {
1351 0x0: decode OP_LO {
1352 format DspIntOp {

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1554 NOROUND, SIGNED ); }});
1555 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1556 NOROUND, SIGNED ); }});
1557 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1558 ROUND, SIGNED ); }});
1559 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1560 ROUND, SIGNED ); }});
1561 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1562 NOSATURATE, &dspctl ); }});
1563 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1564 SATURATE, &dspctl ); }});
1565 }
1566 }
1567 0x2: decode OP_LO {
1568 format DspIntOp {
1569 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1570 NOROUND, SIGNED ); }});
1571 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1572 NOROUND, SIGNED ); }});
1573 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1574 ROUND, SIGNED ); }});
1575 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1576 ROUND, SIGNED ); }});
1577 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1578 SATURATE, NOROUND, &dspctl ); }});
1579 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1580 SATURATE, ROUND, &dspctl ); }});
1581 }
1582 }
1583 }
1584 }
1585
1586 //Table A-10 MIPS32 BSHFL Encoding of sa Field
1587 0x4: decode SA {
1588 format BasicOp {

--- 9 unchanged lines hidden (view full) ---

1598
1599 0x6: decode FUNCTION_LO {
1600
1601 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL)
1602 0x0: decode OP_HI {
1603 0x0: decode OP_LO {
1604 format DspHiLoOp {
1605 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1606 SIMD_FMT_PH, SIGNED, MODE_L ); }});
1607 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1608 SIMD_FMT_PH, SIGNED, MODE_L ); }});
1609 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw,
1610 ACDST, SIMD_FMT_PH ); }});
1611 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1612 SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1613 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1614 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1615 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1616 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1617 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw,
1618 ACDST, SIMD_FMT_PH, &dspctl ); }});
1619 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1620 SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1621 }
1622 }
1623 0x1: decode OP_LO {
1624 format DspHiLoOp {
1625 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1626 SIMD_FMT_PH, SIGNED, MODE_X ); }});
1627 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1628 SIMD_FMT_PH, SIGNED, MODE_X ); }});
1629 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1630 SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1631 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1632 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1633 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1634 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1635 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1636 SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1637 }
1638 }
1639 0x2: decode OP_LO {
1640 format DspHiLoOp {
1641 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1642 MODE_L, SATURATE, &dspctl ); }});
1643 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1644 MODE_R, SATURATE, &dspctl ); }});
1645 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1646 MODE_L, NOSATURATE, &dspctl ); }});
1647 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1648 MODE_R, NOSATURATE, &dspctl ); }});
1649 }
1650 }
1651 0x3: decode OP_LO {
1652 format DspHiLoOp {
1653 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1654 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1655 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1656 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1657 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1658 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1659 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1660 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1661 }
1662 }
1663 }
1664
1665 //Table 3.3 MIPS32 APPEND Encoding of the op Field
1666 0x1: decode OP_HI {
1667 0x0: decode OP_LO {
1668 format IntOp {
1669 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
1670 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
1671 }
1672 }
1673 0x2: decode OP_LO {
1674 format IntOp {
1675 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }});
1676 }
1677 }
1678 }
1679
1680 0x7: FailUnimpl::rdhwr();
1681 }
1682
1683 0x7: decode FUNCTION_LO {
1684
1685 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL)
1686 0x0: decode OP_HI {
1687 0x0: decode OP_LO {
1688 format DspHiLoOp {
1689 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1690 NOROUND, NOSATURATE, &dspctl ); }});

--- 39 unchanged lines hidden (view full) ---

1730 dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }});
1731 0x7: mthlip({{ dspac = dspac << 32;
1732 dspac |= Rs.uw;
1733 dspctl = insertBits( dspctl, 5, 0,
1734 dspctl<5:0>+32 ); }});
1735 }
1736 }
1737 }
1738 }
1739 }
1740 }
1741
1742 0x4: decode OPCODE_LO {
1743 format LoadMemory {
1744 0x0: lb({{ Rt.sw = Mem.sb; }});
1745 0x1: lh({{ Rt.sw = Mem.sh; }});
1746 0x3: lw({{ Rt.sw = Mem.sw; }});
1747 0x4: lbu({{ Rt.uw = Mem.ub; }});
1748 0x5: lhu({{ Rt.uw = Mem.uh; }});
1749 }
1750
1751 format LoadUnalignedMemory {
1752 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1753 Rt.uw = mem_word << mem_shift |
1754 Rt.uw & mask(mem_shift);
1755 }});
1756 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1757 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1758 mem_word >> mem_shift;
1759 }});
1760 }
1761 }
1762
1763 0x5: decode OPCODE_LO {
1764 format StoreMemory {
1765 0x0: sb({{ Mem.ub = Rt<7:0>; }});
1766 0x1: sh({{ Mem.uh = Rt<15:0>; }});
1767 0x3: sw({{ Mem.uw = Rt<31:0>; }});
1768 }
1769
1770 format StoreUnalignedMemory {
1771 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
1772 uint32_t mem_shift = 32 - reg_shift;
1773 mem_word = mem_word & (mask(reg_shift) << mem_shift) |
1774 Rt.uw >> reg_shift;
1775 }});
1776 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
1777 mem_word = Rt.uw << reg_shift |
1778 mem_word & (mask(reg_shift));
1779 }});
1780 }
1781
1782 0x7: FailUnimpl::cache();
1783 }
1784
1785 0x6: decode OPCODE_LO {
1786 format LoadMemory {
1787 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
1788 0x1: lwc1({{ Ft.uw = Mem.uw; }});
1789 0x5: ldc1({{ Ft.ud = Mem.ud; }});
1790 }
1791
1792 0x3: Prefetch::pref();
1793 }
1794
1795
1796 0x7: decode OPCODE_LO {
1797 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1798 {{ uint64_t tmp = write_result;
1799 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1800 }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
1801
1802 format StoreMemory {
1803 0x1: swc1({{ Mem.uw = Ft.uw; }});
1804 0x5: sdc1({{ Mem.ud = Ft.ud; }});
1805 }
1806 }
1807}
1808
1809