1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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379 0x1: dmfc0();
380 0x5: dmtc0();
381 default: unknown();
382 }
383 format MT_MFTR {
384 // Decode MIPS MT MFTR instruction into sub-instructions
385 0x8: decode MT_U {
386 0x0: mftc0({{
387 data = xc->readRegOtherThread((RT << 3 | SEL) +
388 Misc_Reg_Base);
389 }});
390 0x1: decode SEL {
391 0x0: mftgpr({{
392 data = xc->readRegOtherThread(RT);
393 }});
394 0x1: decode RT {
395 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }});
396 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }});
397 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }});
398 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }});
399 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }});
400 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }});
401 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }});
402 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }});
403 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }});
404 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }});
405 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }});
406 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }});
407 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }});
408 default: CP0Unimpl::unknown();
409 }
410 0x2: decode MT_H {
411 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
412 FP_Reg_Base);
413 }});
414 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
415 FP_Reg_Base);
416 }});
417 }
418 0x3: cftc1({{
419 uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
420 FP_Reg_Base);
421 switch (RT) {
422 case 0:
423 data = xc->readRegOtherThread(FLOATREG_FIR +
424 Misc_Reg_Base);
425 break;
426 case 25:
427 data = (fcsr_val & 0xFE000000 >> 24) |
428 (fcsr_val & 0x00800000 >> 23);
429 break;
430 case 26:
431 data = fcsr_val & 0x0003F07C;
432 break;

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445 default: CP0Unimpl::unknown();
446 }
447 }
448 }
449
450 format MT_MTTR {
451 // Decode MIPS MT MTTR instruction into sub-instructions
452 0xC: decode MT_U {
453 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base,
454 Rt);
455 }});
456 0x1: decode SEL {
457 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
458 0x1: decode RT {
459 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt);
460 }});
461 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0,
462 Rt);
463 }});
464 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0,
465 Rt);
466 }});
467 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1,
468 Rt);
469 }});
470 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1,
471 Rt);
472 }});
473 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1,
474 Rt);
475 }});
476 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2,
477 Rt);
478 }});
479 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2,
480 Rt);
481 }});
482 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2,
483 Rt);
484 }});
485 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3,
486 Rt);
487 }});
488 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3,
489 Rt);
490 }});
491 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt);
492 }});
493 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }});
494 default: CP0Unimpl::unknown();
495
496 }
497 0x2: mttc1({{
498 uint64_t data = xc->readRegOtherThread(RD +
499 FP_Reg_Base);
500 data = insertBits(data, MT_H ? 63 : 31,
501 MT_H ? 32 : 0, Rt);
502 xc->setRegOtherThread(RD + FP_Reg_Base,
503 data);
504 }});
505 0x3: cttc1({{
506 uint32_t data;
507 switch (RD) {
508 case 25:
509 data = (Rt_uw<7:1> << 25) | // move 31-25
510 (FCSR & 0x01000000) | // bit 24

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529 data = Rt_uw;
530 break;
531 default:
532 panic("FP Control Value (%d) "
533 "Not Available. Ignoring "
534 "Access to Floating Control "
535 "S""tatus Register", FS);
536 }
537 xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data);
538 }});
539 default: CP0Unimpl::unknown();
540 }
541 }
542 }
543 0xB: decode RD {
544 format MT_Control {
545 0x0: decode POS {

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