1// -*- mode:c++ -*-
2
3////////////////////////////////////////////////////////////////////
4//
5// The actual MIPS32 ISA decoder
6// -----------------------------
7// The following instructions are specified in the MIPS32 ISA
8// Specification. Decoding closely follows the style specified
9// in the MIPS32 ISA specification document starting with Table
10// A-2 (document available @ www.mips.com)
11//
12decode OPCODE_HI default Unknown::unknown() {
13 //Table A-2
14 0x0: decode OPCODE_LO {
15 0x0: decode FUNCTION_HI {
16 0x0: decode FUNCTION_LO {
17 0x1: decode MOVCI {
18 format BasicOp {
19 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
20 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
21 }
22 }
23
24 format BasicOp {
25 //Table A-3 Note: "Specific encodings of the rd, rs, and
26 //rt fields are used to distinguish SLL, SSNOP, and EHB
27 //functions
28 0x0: decode RS {
29 0x0: decode RT_RD {
30 0x0: decode SA default Nop::nop(){
31 0x1: WarnUnimpl::ssnop();
32 0x3: WarnUnimpl::ehb();
33 }
34 default: sll({{ Rd = Rt.uw << SA; }});
35 }
36 }
37
38 0x2: decode RS_SRL {
39 0x0:decode SRL {
40 0: srl({{ Rd = Rt.uw >> SA; }});
41
42 //Hardcoded assuming 32-bit ISA, probably need parameter here
43 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
44 }
45 }
46
47 0x3: decode RS {
48 0x0: sra({{
49 uint32_t temp = Rt >> SA;
50 if ( (Rt & 0x80000000) > 0 ) {
51 uint32_t mask = 0x80000000;
52 for(int i=0; i < SA; i++) {
53 temp |= mask;
54 mask = mask >> 1;
55 }
56 }
57 Rd = temp;
58 }});
59 }
60
61 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
62
63 0x6: decode SRLV {
64 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});

--- 16 unchanged lines hidden (view full) ---

81 }
82
83 Rd = temp;
84 }});
85 }
86 }
87
88 0x1: decode FUNCTION_LO {
89 //Table A-3 Note: "Specific encodings of the hint field are
90 //used to distinguish JR from JR.HB and JALR from JALR.HB"
91 format Jump {
92 0x0: decode HINT {
93 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
94 default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
95 }
96
97 0x1: decode HINT {
98 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall, Link
99 , ClearHazards);
100 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall,
101 Link);
102 }
103 }
104
105 format BasicOp {
106 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
107 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
108 0x4: syscall({{ xc->syscall(R2); }}, IsNonSpeculative);
109 0x7: sync({{ ; }}, IsMemBarrier);
110 }
111
112 format FailUnimpl {
113 0x5: break();
114 }
115 }
116
117 0x2: decode FUNCTION_LO {
118 format HiLoMiscOp {
119 0x0: mfhi({{ Rd = HI; }});
120 0x1: mthi({{ HI = Rs; }});
121 0x2: mflo({{ Rd = LO; }});
122 0x3: mtlo({{ LO = Rs; }});
123 }
124 }
125
126 0x3: decode FUNCTION_LO {
127 format HiLoOp {
128 0x0: mult({{ val = Rs.sd * Rt.sd; }});
129 0x1: multu({{ val = Rs.ud * Rt.ud; }});
130 }
131
132 format HiLoMiscOp {
133 0x2: div({{
134 HI = Rs.sd % Rt.sd;
135 LO = Rs.sd / Rt.sd;
136 }});
137 0x3: divu({{
138 HI = Rs.ud % Rt.ud;
139 LO = Rs.ud / Rt.ud;
140 }});
141 }
142 }
143
144 0x4: decode HINT {

--- 32 unchanged lines hidden (view full) ---

177 }
178 }
179
180 0x1: decode REGIMM_HI {
181 0x0: decode REGIMM_LO {
182 format Branch {
183 0x0: bltz({{ cond = (Rs.sw < 0); }});
184 0x1: bgez({{ cond = (Rs.sw >= 0); }});
185 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
186 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
187 }
188 }
189
190 0x1: decode REGIMM_LO {
191 format Trap {
192 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
193 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
194 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
195 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
196 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
197 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
198 }
199 }
200
201 0x2: decode REGIMM_LO {
202 format Branch {
203 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
204 0x1: decode RS {
205 0x0: bal ({{ cond = 1; }}, IsCall, Link);
206 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
207 }
208 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
209 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
210 }
211 }
212
213 0x3: decode REGIMM_LO {
214 format WarnUnimpl {
215 0x7: synci();
216 }
217 }
218 }
219
220 format Jump {
221 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
222 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall,
223 Link);
224 }
225
226 format Branch {
227 0x4: decode RS_RT {
228 0x0: b({{ cond = 1; }});
229 default: beq({{ cond = (Rs.sw == Rt.sw); }});
230 }
231 0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
232 0x6: blez({{ cond = (Rs.sw <= 0); }});
233 0x7: bgtz({{ cond = (Rs.sw > 0); }});
234 }
235 }
236
237 0x1: decode OPCODE_LO {
238 format IntImmOp {
239 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
240 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
241 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
242 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
243 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
244 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
245 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
246
247 0x7: decode RS {
248 0x0: lui({{ Rt = imm << 16}});
249 }
250 }
251 }
252
253 0x2: decode OPCODE_LO {
254 //Table A-11 MIPS32 COP0 Encoding of rs Field
255 0x0: decode RS_MSB {
256 0x0: decode RS {
257 format CP0Control {
258 0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }});
259 0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }});
260 }
261
262 format MipsMT {
263 0x8: mftr();
264 0xC: mttr();
265 0xB: decode RD {
266 0x0: decode SC {
267 0x0: dvpe();
268 0x1: evpe();
269 }
270 0x1: decode SC {
271 0x0: dmt();
272 0x1: emt();
273 0xC: decode SC {
274 0x0: di();
275 0x1: ei();
276 }
277 }
278 }
279 }
280
281 format FailUnimpl {
282 0xA: rdpgpr();
283 0xE: wrpgpr();
284 }
285 }
286
287 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
288 0x1: decode FUNCTION {
289 format FailUnimpl {
290 0x01: tlbr();
291 0x02: tlbwi();
292 0x06: tlbwr();
293 0x08: tlbp();
294
295 0x18: eret();
296 0x1F: deret();
297 0x20: wait();
298 }
299 }
300 }
301
302 //Table A-13 MIPS32 COP1 Encoding of rs Field
303 0x1: decode RS_MSB {
304
305 0x0: decode RS_HI {
306 0x0: decode RS_LO {
307 format CP1Control {
308 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }});
309
310 0x2: cfc1({{
311 switch (FS)
312 {
313 case 0:
314 Rt = FIR;
315 break;
316 case 25:
317 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23;
318 break;
319 case 26:
320 Rt = 0 | (FCSR & 0x0003F07C);
321 break;
322 case 28:
323 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
324 break;
325 case 31:
326 Rt = FCSR;
327 break;
328 default:
329 panic("FP Control Value (%d) Not Valid");
330 }
331 }});
332
333 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
334
335 0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
336
337 0x6: ctc1({{
338 switch (FS)
339 {
340 case 25:
341 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25
342 | (FCSR & 0x01000000) // bit 24
343 | (FCSR & 0x004FFFFF);// bit 22...0
344 break;

--- 19 unchanged lines hidden (view full) ---

364 FCSR = Rt.uw;
365 break;
366
367 default:
368 panic("FP Control Value (%d) Not Available. Ignoring Access to"
369 "Floating Control Status Register", FS);
370 }
371 }});
372
373 0x7: mthc1({{
374 uint64_t fs_hi = Rt.uw;
375 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
376 Fs.ud = (fs_hi << 32) | fs_lo;
377 }});
378
379 }
380 }
381
382 0x1: decode ND {
383 format Branch {
384 0x0: decode TF {
385 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
386 }});
387 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
388 }});
389 }
390 0x1: decode TF {
391 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
392 }}, Likely);
393 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
394 }}, Likely);
395 }
396 }
397 }
398 }
399
400 0x1: decode RS_HI {
401 0x2: decode RS_LO {
402 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
403 //(( single-precision floating point))
404 0x0: decode FUNCTION_HI {
405 0x0: decode FUNCTION_LO {
406 format FloatOp {
407 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}});
408 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}});
409 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}});
410 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
411 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
412 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
413 0x6: mov_s({{ Fd.sf = Fs.sf;}});
414 0x7: neg_s({{ Fd.sf = -Fs.sf;}});
415 }
416 }
417
418 0x1: decode FUNCTION_LO {
419 format FloatConvertOp {
420 0x0: round_l_s({{ val = Fs.sf; }}, ToLong,
421 Round);
422 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong,
423 Trunc);
424 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong,
425 Ceil);
426 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong,
427 Floor);
428 0x4: round_w_s({{ val = Fs.sf; }}, ToWord,
429 Round);
430 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord,
431 Trunc);
432 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord,
433 Ceil);
434 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord,
435 Floor);
436 }
437 }
438
439 0x2: decode FUNCTION_LO {
440 0x1: decode MOVCF {
441 format BasicOp {
442 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }});
443 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }});
444 }
445 }
446
447 format BasicOp {
448 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
449 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
450 }
451
452 format FloatOp {
453 0x5: recip_s({{ Fd = 1 / Fs; }});
454 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
455 }
456 }
457
458 0x4: decode FUNCTION_LO {
459 format FloatConvertOp {
460 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
461 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
462 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
463 }
464
465 0x6: FloatOp::cvt_ps_s({{
466 Fd.ud = (uint64_t) Fs.uw << 32 |
467 (uint64_t) Ft.uw;
468 }});
469 }
470
471 0x6: decode FUNCTION_LO {
472 format FloatCompareOp {
473 0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
474 UnorderedFalse);
475 0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
476 UnorderedTrue);
477 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},
478 UnorderedFalse);
479 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }},
480 UnorderedTrue);
481 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }},
482 UnorderedFalse);
483 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }},
484 UnorderedTrue);
485 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }},
486 UnorderedFalse);
487 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }},
488 UnorderedTrue);
489 }
490 }
491
492 0x7: decode FUNCTION_LO {
493 format FloatCompareOp {
494 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision,
495 UnorderedFalse, QnanException);
496 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision,
497 UnorderedTrue, QnanException);
498 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}},
499 UnorderedFalse, QnanException);
500 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }},
501 UnorderedTrue, QnanException);
502 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }},
503 UnorderedFalse, QnanException);
504 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }},
505 UnorderedTrue, QnanException);
506 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }},
507 UnorderedFalse, QnanException);
508 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }},
509 UnorderedTrue, QnanException);
510 }
511 }
512 }
513
514 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
515 0x1: decode FUNCTION_HI {
516 0x0: decode FUNCTION_LO {
517 format FloatOp {
518 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }});
519 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }});
520 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }});
521 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }});
522 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }});
523 0x5: abs_d({{ Fd.df = fabs(Fs.df); }});
524 0x6: mov_d({{ Fd.df = Fs.df; }});
525 0x7: neg_d({{ Fd.df = -1 * Fs.df; }});
526 }
527 }
528
529 0x1: decode FUNCTION_LO {
530 format FloatConvertOp {
531 0x0: round_l_d({{ val = Fs.df; }}, ToLong,
532 Round);
533 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong,
534 Trunc);
535 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong,
536 Ceil);
537 0x3: floor_l_d({{ val = Fs.df; }}, ToLong,
538 Floor);
539 0x4: round_w_d({{ val = Fs.df; }}, ToWord,
540 Round);
541 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord,
542 Trunc);
543 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord,
544 Ceil);
545 0x7: floor_w_d({{ val = Fs.df; }}, ToWord,
546 Floor);
547 }
548 }
549
550 0x2: decode FUNCTION_LO {
551 0x1: decode MOVCF {
552 format BasicOp {
553 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ?
554 Fs.df : Fd.df;
555 }});
556 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ?
557 Fs.df : Fd.df;
558 }});
559 }
560 }
561
562 format BasicOp {
563 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
564 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
565 }
566
567 format FloatOp {
568 0x5: recip_d({{ Fd.df = 1 / Fs.df }});
569 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
570 }
571 }
572
573 0x4: decode FUNCTION_LO {
574 format FloatConvertOp {
575 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
576 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
577 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
578 }
579 }
580
581 0x6: decode FUNCTION_LO {
582 format FloatCompareOp {
583 0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
584 UnorderedFalse);
585 0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
586 UnorderedTrue);
587 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }},
588 UnorderedFalse);
589 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }},
590 UnorderedTrue);
591 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }},
592 UnorderedFalse);
593 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }},
594 UnorderedTrue);
595 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }},
596 UnorderedFalse);
597 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }},
598 UnorderedTrue);
599 }
600 }
601
602 0x7: decode FUNCTION_LO {
603 format FloatCompareOp {
604 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision,
605 UnorderedFalse, QnanException);
606 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision,
607 UnorderedTrue, QnanException);
608 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }},
609 UnorderedFalse, QnanException);
610 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }},
611 UnorderedTrue, QnanException);
612 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }},
613 UnorderedFalse, QnanException);
614 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
615 UnorderedTrue, QnanException);
616 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
617 UnorderedFalse, QnanException);
618 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
619 UnorderedTrue, QnanException);
620 }
621 }
622 }
623
624 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
625 0x4: decode FUNCTION {
626 format FloatConvertOp {
627 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
628 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
629 0x26: FailUnimpl::cvt_ps_w();
630 }
631 }
632
633 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
634 //Note: "1. Format type L is legal only if 64-bit floating point operations
635 //are enabled."
636 0x5: decode FUNCTION_HI {
637 format FloatConvertOp {
638 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
639 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
640 0x26: FailUnimpl::cvt_ps_l();
641 }
642 }
643
644 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
645 //Note: "1. Format type PS is legal only if 64-bit floating point operations
646 //are enabled. "
647 0x6: decode FUNCTION_HI {
648 0x0: decode FUNCTION_LO {
649 format Float64Op {
650 0x0: add_ps({{
651 Fd1.sf = Fs1.sf + Ft2.sf;
652 Fd2.sf = Fs2.sf + Ft2.sf;
653 }});
654 0x1: sub_ps({{
655 Fd1.sf = Fs1.sf - Ft2.sf;
656 Fd2.sf = Fs2.sf - Ft2.sf;
657 }});
658 0x2: mul_ps({{
659 Fd1.sf = Fs1.sf * Ft2.sf;
660 Fd2.sf = Fs2.sf * Ft2.sf;
661 }});
662 0x5: abs_ps({{
663 Fd1.sf = fabs(Fs1.sf);
664 Fd2.sf = fabs(Fs2.sf);
665 }});
666 0x6: mov_ps({{
667 Fd1.sf = Fs1.sf;
668 Fd2.sf = Fs2.sf;
669 }});
670 0x7: neg_ps({{
671 Fd1.sf = -(Fs1.sf);
672 Fd2.sf = -(Fs2.sf);
673 }});
674 }
675 }
676
677 0x2: decode FUNCTION_LO {
678 0x1: decode MOVCF {
679 format Float64Op {
680 0x0: movf_ps({{
681 Fd1 = (getCondCode(FCSR, CC) == 0) ?
682 Fs1 : Fd1;
683 Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
684 Fs2 : Fd2;
685 }});
686 0x1: movt_ps({{
687 Fd2 = (getCondCode(FCSR, CC) == 1) ?
688 Fs1 : Fd1;
689 Fd2 = (getCondCode(FCSR, CC+1) == 1) ?
690 Fs2 : Fd2;
691 }});
692 }
693 }
694
695 format Float64Op {
696 0x2: movz_ps({{
697 Fd1 = (getCondCode(FCSR, CC) == 0) ?
698 Fs1 : Fd1;
699 Fd2 = (getCondCode(FCSR, CC) == 0) ?
700 Fs2 : Fd2;
701 }});
702 0x3: movn_ps({{
703 Fd1 = (getCondCode(FCSR, CC) == 1) ?
704 Fs1 : Fd1;
705 Fd2 = (getCondCode(FCSR, CC) == 1) ?
706 Fs2 : Fd2;
707 }});
708 }
709
710 }
711
712 0x4: decode FUNCTION_LO {
713 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
714 }
715
716 0x5: decode FUNCTION_LO {
717 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
718
719 format Float64Op {
720 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
721 Ft1.uw;
722 }});
723 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
724 Ft2.uw;
725 }});
726 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
727 Ft1.uw;
728 }});
729 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
730 Ft2.uw;
731 }});
732 }
733 }
734
735 0x6: decode FUNCTION_LO {
736 format FloatPSCompareOp {
737 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
738 UnorderedFalse);
739 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
740 UnorderedTrue);
741 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
742 {{ cond2 = (Fs2.sf == Ft2.sf); }},
743 UnorderedFalse);
744 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
745 {{ cond2 = (Fs2.sf == Ft2.sf); }},
746 UnorderedTrue);
747 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
748 {{ cond2 = (Fs2.sf < Ft2.sf); }},
749 UnorderedFalse);
750 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }},
751 {{ cond2 = (Fs2.sf < Ft2.sf); }},
752 UnorderedTrue);
753 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }},
754 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
755 UnorderedFalse);
756 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
757 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
758 UnorderedTrue);
759 }
760 }
761
762 0x7: decode FUNCTION_LO {
763 format FloatPSCompareOp {
764 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
765 UnorderedFalse, QnanException);
766 0x1: c_ngle_ps({{ cond1 = 0; }},
767 {{ cond2 = 0; }},
768 UnorderedTrue, QnanException);
769 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
770 {{ cond2 = (Fs2.sf == Ft2.sf); }},
771 UnorderedFalse, QnanException);
772 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
773 {{ cond2 = (Fs2.sf == Ft2.sf); }},
774 UnorderedTrue, QnanException);
775 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
776 {{ cond2 = (Fs2.sf < Ft2.sf); }},
777 UnorderedFalse, QnanException);
778 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
779 {{ cond2 = (Fs2.sf < Ft2.sf); }},
780 UnorderedTrue, QnanException);
781 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
782 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
783 UnorderedFalse, QnanException);
784 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
785 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
786 UnorderedTrue, QnanException);
787 }
788 }
789 }
790 }
791 }
792 }
793
794 //Table A-19 MIPS32 COP2 Encoding of rs Field
795 0x2: decode RS_MSB {
796 format FailUnimpl {
797 0x0: decode RS_HI {
798 0x0: decode RS_LO {
799 0x0: mfc2();
800 0x2: cfc2();
801 0x3: mfhc2();
802 0x4: mtc2();
803 0x6: ctc2();
804 0x7: mftc2();
805 }
806
807 0x1: decode ND {
808 0x0: decode TF {
809 0x0: bc2f();
810 0x1: bc2t();
811 }
812
813 0x1: decode TF {
814 0x0: bc2fl();
815 0x1: bc2tl();
816 }
817 }
818 }
819 }
820 }
821
822 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
823 //Note: "COP1X instructions are legal only if 64-bit floating point
824 //operations are enabled."
825 0x3: decode FUNCTION_HI {
826 0x0: decode FUNCTION_LO {
827 format LoadIndexedMemory {
828 0x0: lwxc1({{ Ft.uw = Mem.uw;}});
829 0x1: ldxc1({{ Ft.ud = Mem.ud;}});
830 0x5: luxc1({{ Ft.uw = Mem.ud;}});
831 }
832 }
833
834 0x1: decode FUNCTION_LO {
835 format StoreIndexedMemory {
836 0x0: swxc1({{ Mem.uw = Ft.uw;}});
837 0x1: sdxc1({{ Mem.ud = Ft.ud;}});
838 0x5: suxc1({{ Mem.ud = Ft.ud;}});
839 }
840
841 0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
842 }
843
844 0x3: decode FUNCTION_LO {
845 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) {
846 Fd.ud = Fs.ud;
847 } else if (Rs<2:0> == 4) {
848 #if BYTE_ORDER == BIG_ENDIAN
849 Fd.ud = Fs.ud<31:0> << 32 |
850 Ft.ud<63:32>;
851 #elif BYTE_ORDER == LITTLE_ENDIAN
852 Fd.ud = Ft.ud<31:0> << 32 |
853 Fs.ud<63:32>;
854 #endif
855 } else {
856 Fd.ud = Fd.ud;
857 }
858 }});
859 }
860
861 format FloatAccOp {
862 0x4: decode FUNCTION_LO {
863 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
864 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
865 0x6: madd_ps({{
866 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
867 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
868 }});
869 }
870
871 0x5: decode FUNCTION_LO {
872 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
873 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
874 0x6: msub_ps({{
875 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
876 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
877 }});
878 }
879
880 0x6: decode FUNCTION_LO {
881 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
882 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
883 0x6: nmadd_ps({{
884 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df);
885 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df);
886 }});
887 }
888
889 0x7: decode FUNCTION_LO {
890 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
891 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
892 0x6: nmsub_ps({{
893 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df);
894 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df);
895 }});
896 }
897
898 }
899 }
900
901 format Branch {
902 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely);
903 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely);
904 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely);
905 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely);
906 }
907 }
908
909 0x3: decode OPCODE_LO {
910 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
911 0x4: decode FUNCTION_HI {
912 0x0: decode FUNCTION_LO {
913 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
914 Rd.sw = temp1<31:0>
915 }});
916
917 format HiLoOp {
918 0x0: madd({{ val = ((int64_t) HI << 32 | LO) +
919 (Rs.sd * Rt.sd);
920 }});
921 0x1: maddu({{ val = ((uint64_t) HI << 32 | LO) +
922 (Rs.ud * Rt.ud);
923 }});
924 0x4: msub({{ val = ((int64_t) HI << 32 | LO) -
925 (Rs.sd * Rt.sd);
926 }});
927 0x5: msubu({{ val = ((uint64_t) HI << 32 | LO) -
928 (Rs.ud * Rt.ud);
929 }});
930 }
931 }
932
933 0x4: decode FUNCTION_LO {
934 format BasicOp {
935 0x0: clz({{ int cnt = 32;
936 for (int idx = 31; idx >= 0; idx--) {
937 if( Rs<idx:idx> == 1) {
938 cnt = 31 - idx;
939 break;
940 }
941 }
942 Rd.uw = cnt;
943 }});
944 0x1: clo({{ int cnt = 32;
945 for (int idx = 31; idx >= 0; idx--) {
946 if( Rs<idx:idx> == 0) {
947 cnt = 31 - idx;
948 break;
949 }
950 }
951 Rd.uw = cnt;
952 }});
953 }
954 }
955
956 0x7: decode FUNCTION_LO {
957 0x7: FailUnimpl::sdbbp();
958 }
959 }
960
961 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
962 //of the Architecture
963 0x7: decode FUNCTION_HI {
964 0x0: decode FUNCTION_LO {
965 format BasicOp {
966 0x1: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }});
967 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
968 bits(Rs.uw, MSB-LSB, 0) << LSB |
969 bits(Rt.uw, LSB-1, 0);
970 }});
971 }
972 }
973
974 0x1: decode FUNCTION_LO {
975 format MipsMT {
976 0x0: fork();
977 0x1: yield();
978 }
979 }
980
981 //Table A-10 MIPS32 BSHFL Encoding of sa Field
982 0x4: decode SA {
983 format BasicOp {
984 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 |
985 Rt.uw<31:24> << 16 |
986 Rt.uw<7:0> << 8 |
987 Rt.uw<15:8>;
988 }});
989 0x10: seb({{ Rd.sw = Rt.sw<7:0>}});
990 0x18: seh({{ Rd.sw = Rt.sw<15:0>}});
991 }
992 }
993
994 0x6: decode FUNCTION_LO {
995 0x7: FailUnimpl::rdhwr();
996 }
997 }
998 }
999
1000 0x4: decode OPCODE_LO {
1001 format LoadMemory {
1002 0x0: lb({{ Rt.sw = Mem.sb; }});
1003 0x1: lh({{ Rt.sw = Mem.sh; }});
1004 0x3: lw({{ Rt.sw = Mem.sw; }});
1005 0x4: lbu({{ Rt.uw = Mem.ub; }});
1006 0x5: lhu({{ Rt.uw = Mem.uh; }});
1007 }
1008
1009 format LoadUnalignedMemory {
1010 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1011 Rt.uw = mem_word << mem_shift |
1012 Rt.uw & mask(mem_shift);
1013 }});
1014 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1015 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1016 mem_word >> mem_shift;
1017 }});
1018 }
1019 }
1020
1021 0x5: decode OPCODE_LO {
1022 format StoreMemory {
1023 0x0: sb({{ Mem.ub = Rt<7:0>; }});
1024 0x1: sh({{ Mem.uh = Rt<15:0>; }});
1025 0x3: sw({{ Mem.uw = Rt<31:0>; }});
1026 }
1027
1028 format StoreUnalignedMemory {
1029 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
1030 uint32_t mem_shift = 32 - reg_shift;
1031 mem_word = mem_word & (mask(reg_shift) << mem_shift) |
1032 Rt.uw >> reg_shift;
1033 }});
1034 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
1035 mem_word = Rt.uw << reg_shift |
1036 mem_word & (mask(reg_shift));
1037 }});
1038 }
1039
1040 0x7: FailUnimpl::cache();
1041 }
1042
1043 0x6: decode OPCODE_LO {
1044 format LoadMemory {
1045 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
1046 0x1: lwc1({{ Ft.uw = Mem.uw; }});
1047 0x5: ldc1({{ Ft.ud = Mem.ud; }});
1048 }
1049
1050 0x3: Prefetch::pref();
1051 }
1052
1053
1054 0x7: decode OPCODE_LO {
1055 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1056 {{ uint64_t tmp = write_result;
1057 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1058 }}, mem_flags=LOCKED);
1059
1060 format StoreMemory {
1061 0x1: swc1({{ Mem.uw = Ft.uw; }});
1062 0x5: sdc1({{ Mem.ud = Ft.ud; }});
1063 }
1064 }
1065}
1066
1067