isa.hh (9180:ee8d7a51651d) isa.hh (9384:877293183bdf)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include <queue>
35#include <string>
36#include <vector>
37
38#include "arch/mips/registers.hh"
39#include "arch/mips/types.hh"
40#include "sim/eventq.hh"
41#include "sim/fault_fwd.hh"
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 25 unchanged lines hidden (view full) ---

34#include <queue>
35#include <string>
36#include <vector>
37
38#include "arch/mips/registers.hh"
39#include "arch/mips/types.hh"
40#include "sim/eventq.hh"
41#include "sim/fault_fwd.hh"
42#include "sim/sim_object.hh"
42
43class BaseCPU;
44class Checkpoint;
45class EventManager;
43
44class BaseCPU;
45class Checkpoint;
46class EventManager;
47struct MipsISAParams;
46class ThreadContext;
47
48namespace MipsISA
49{
48class ThreadContext;
49
50namespace MipsISA
51{
50 class ISA
52 class ISA : public SimObject
51 {
52 public:
53 // The MIPS name for this file is CP0 or Coprocessor 0
54 typedef ISA CP0;
55
53 {
54 public:
55 // The MIPS name for this file is CP0 or Coprocessor 0
56 typedef ISA CP0;
57
58 typedef MipsISAParams Params;
59
56 protected:
57 // Number of threads and vpes an individual ISA state can handle
58 uint8_t numThreads;
59 uint8_t numVpes;
60
61 enum BankType {
62 perProcessor,
63 perThreadContext,
64 perVirtProcessor
65 };
66
67 std::vector<std::vector<MiscReg> > miscRegFile;
68 std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
69 std::vector<BankType> bankType;
70
71 public:
60 protected:
61 // Number of threads and vpes an individual ISA state can handle
62 uint8_t numThreads;
63 uint8_t numVpes;
64
65 enum BankType {
66 perProcessor,
67 perThreadContext,
68 perVirtProcessor
69 };
70
71 std::vector<std::vector<MiscReg> > miscRegFile;
72 std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
73 std::vector<BankType> bankType;
74
75 public:
72 ISA(uint8_t num_threads = 1, uint8_t num_vpes = 1);
73
74 void clear();
75
76 void configCP();
77
78 unsigned getVPENum(ThreadID tid);
79
80 //////////////////////////////////////////////////////////
81 //

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150 void updateCPU(BaseCPU *cpu);
151
152 // Keep a List of CPU Events that need to be deallocated
153 std::queue<CP0Event*> cp0EventRemoveList;
154
155 static std::string miscRegNames[NumMiscRegs];
156
157 public:
76 void clear();
77
78 void configCP();
79
80 unsigned getVPENum(ThreadID tid);
81
82 //////////////////////////////////////////////////////////
83 //

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152 void updateCPU(BaseCPU *cpu);
153
154 // Keep a List of CPU Events that need to be deallocated
155 std::queue<CP0Event*> cp0EventRemoveList;
156
157 static std::string miscRegNames[NumMiscRegs];
158
159 public:
160 const Params *params() const;
158
161
162 ISA(Params *p);
163
159 int
160 flattenIntIndex(int reg)
161 {
162 return reg;
163 }
164
165 int
166 flattenFloatIndex(int reg)

--- 13 unchanged lines hidden --- 		164 int
165 flattenIntIndex(int reg)
166 {
167 return reg;
168 }
169
170 int
171 flattenFloatIndex(int reg)

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