isa.hh (13610:5d5404ac6288) isa.hh (13615:5cc9363f5ab7)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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63 uint8_t numVpes;
64
65 enum BankType {
66 perProcessor,
67 perThreadContext,
68 perVirtProcessor
69 };
70
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 54 unchanged lines hidden (view full) ---

63 uint8_t numVpes;
64
65 enum BankType {
66 perProcessor,
67 perThreadContext,
68 perVirtProcessor
69 };
70
71 std::vector<std::vector<MiscReg> > miscRegFile;
72 std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
71 std::vector<std::vector<RegVal> > miscRegFile;
72 std::vector<std::vector<RegVal> > miscRegFile_WriteMask;
73 std::vector<BankType> bankType;
74
75 public:
76 void clear();
77
78 void configCP();
79
80 unsigned getVPENum(ThreadID tid) const;
81
82 //////////////////////////////////////////////////////////
83 //
84 // READ/WRITE CP0 STATE
85 //
86 //
87 //////////////////////////////////////////////////////////
88 //@TODO: MIPS MT's register view automatically connects
89 // Status to TCStatus depending on current thread
90 void updateCP0ReadView(int misc_reg, ThreadID tid) { }
73 std::vector<BankType> bankType;
74
75 public:
76 void clear();
77
78 void configCP();
79
80 unsigned getVPENum(ThreadID tid) const;
81
82 //////////////////////////////////////////////////////////
83 //
84 // READ/WRITE CP0 STATE
85 //
86 //
87 //////////////////////////////////////////////////////////
88 //@TODO: MIPS MT's register view automatically connects
89 // Status to TCStatus depending on current thread
90 void updateCP0ReadView(int misc_reg, ThreadID tid) { }
91 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
91 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
92
93 //template <class TC>
92
93 //template <class TC>
94 MiscReg readMiscReg(int misc_reg,
95 ThreadContext *tc, ThreadID tid = 0);
94 RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
96
95
97 MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val);
98 void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0);
99 void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
96 RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
97 void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
98 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
100
101 //template <class TC>
99
100 //template <class TC>
102 void setMiscReg(int misc_reg, MiscReg val,
101 void setMiscReg(int misc_reg, RegVal val,
103 ThreadContext *tc, ThreadID tid=0);
104
105 //////////////////////////////////////////////////////////
106 //
107 // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
108 // TO SCHEDULE EVENTS
109 //
110 //////////////////////////////////////////////////////////

--- 80 unchanged lines hidden --- 		102 ThreadContext *tc, ThreadID tid=0);
103
104 //////////////////////////////////////////////////////////
105 //
106 // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
107 // TO SCHEDULE EVENTS
108 //
109 //////////////////////////////////////////////////////////

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