isa.hh (10935:acd48ddd725f) | isa.hh (12106:7784fac1b159) |
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1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#define __ARCH_MIPS_ISA_HH__ 33 34#include <queue> 35#include <string> 36#include <vector> 37 38#include "arch/mips/registers.hh" 39#include "arch/mips/types.hh" | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#define __ARCH_MIPS_ISA_HH__ 33 34#include <queue> 35#include <string> 36#include <vector> 37 38#include "arch/mips/registers.hh" 39#include "arch/mips/types.hh" |
40#include "cpu/reg_class.hh" |
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40#include "sim/eventq.hh" 41#include "sim/sim_object.hh" 42 43class BaseCPU; 44class Checkpoint; 45class EventManager; 46struct MipsISAParams; 47class ThreadContext; --- 112 unchanged lines hidden (view full) --- 160 161 /// Explicitly import the otherwise hidden startup 162 using SimObject::startup; 163 164 const Params *params() const; 165 166 ISA(Params *p); 167 | 41#include "sim/eventq.hh" 42#include "sim/sim_object.hh" 43 44class BaseCPU; 45class Checkpoint; 46class EventManager; 47struct MipsISAParams; 48class ThreadContext; --- 112 unchanged lines hidden (view full) --- 161 162 /// Explicitly import the otherwise hidden startup 163 using SimObject::startup; 164 165 const Params *params() const; 166 167 ISA(Params *p); 168 |
169 RegId flattenRegId(const RegId& regId) const { return regId; } 170 |
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168 int 169 flattenIntIndex(int reg) const 170 { 171 return reg; 172 } 173 174 int 175 flattenFloatIndex(int reg) const --- 21 unchanged lines hidden --- | 171 int 172 flattenIntIndex(int reg) const 173 { 174 return reg; 175 } 176 177 int 178 flattenFloatIndex(int reg) const --- 21 unchanged lines hidden --- |