isa.hh (10474:799c8ee4ecba) isa.hh (10698:829adc48e175)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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71 std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
72 std::vector<BankType> bankType;
73
74 public:
75 void clear();
76
77 void configCP();
78
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 62 unchanged lines hidden (view full) ---

71 std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
72 std::vector<BankType> bankType;
73
74 public:
75 void clear();
76
77 void configCP();
78
79 unsigned getVPENum(ThreadID tid);
79 unsigned getVPENum(ThreadID tid) const;
80
81 //////////////////////////////////////////////////////////
82 //
83 // READ/WRITE CP0 STATE
84 //
85 //
86 //////////////////////////////////////////////////////////
87 //@TODO: MIPS MT's register view automatically connects
88 // Status to TCStatus depending on current thread
89 void updateCP0ReadView(int misc_reg, ThreadID tid) { }
80
81 //////////////////////////////////////////////////////////
82 //
83 // READ/WRITE CP0 STATE
84 //
85 //
86 //////////////////////////////////////////////////////////
87 //@TODO: MIPS MT's register view automatically connects
88 // Status to TCStatus depending on current thread
89 void updateCP0ReadView(int misc_reg, ThreadID tid) { }
90 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
90 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
91
92 //template <class TC>
93 MiscReg readMiscReg(int misc_reg,
94 ThreadContext *tc, ThreadID tid = 0);
95
96 MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
97 void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
98 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,

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92 //template <class TC>
93 MiscReg readMiscReg(int misc_reg,
94 ThreadContext *tc, ThreadID tid = 0);
95
96 MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
97 void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
98 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,

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