1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_MIPS_ISA_HH__
32#define __ARCH_MIPS_ISA_HH__
33
34#include <queue>
35#include <string>
36#include <vector>
37
38#include "arch/mips/registers.hh"
39#include "arch/mips/types.hh"
40#include "sim/eventq.hh"
41#include "sim/fault_fwd.hh"
42
43class BaseCPU;
44class Checkpoint;
45class EventManager;
46class ThreadContext;
47
48namespace MipsISA
49{
50 class ISA
51 {
52 public:
53 // The MIPS name for this file is CP0 or Coprocessor 0
54 typedef ISA CP0;
55
56 protected:
57 // Number of threads and vpes an individual ISA state can handle
58 uint8_t numThreads;
59 uint8_t numVpes;
60
61 enum BankType {
62 perProcessor,
63 perThreadContext,
64 perVirtProcessor
65 };
66
67 std::vector<std::vector<MiscReg> > miscRegFile;
68 std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
69 std::vector<BankType> bankType;
70
71 public:
72 ISA(uint8_t num_threads = 1, uint8_t num_vpes = 1);
73
74 void clear();
75
76 void configCP();
77
78 unsigned getVPENum(ThreadID tid);
79
80 //////////////////////////////////////////////////////////
81 //
82 // READ/WRITE CP0 STATE
83 //
84 //
85 //////////////////////////////////////////////////////////
86 //@TODO: MIPS MT's register view automatically connects
87 // Status to TCStatus depending on current thread
88 void updateCP0ReadView(int misc_reg, ThreadID tid) { }
89 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
90
91 //template <class TC>
92 MiscReg readMiscReg(int misc_reg,
93 ThreadContext *tc, ThreadID tid = 0);
94
95 MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
96 void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
97 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
98 ThreadID tid = 0);
99
100 //template <class TC>
101 void setMiscReg(int misc_reg, const MiscReg &val,
102 ThreadContext *tc, ThreadID tid = 0);
103
104 //////////////////////////////////////////////////////////
105 //
106 // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
107 // TO SCHEDULE EVENTS
108 //
109 //////////////////////////////////////////////////////////
110
111 // Flag that is set when CP0 state has been written to.
112 bool cp0Updated;
113
114 // Enumerated List of CP0 Event Types
115 enum CP0EventType {
116 UpdateCP0
117 };
118
119 // Declare A CP0Event Class for scheduling
120 class CP0Event : public Event
121 {
122 protected:
123 ISA::CP0 *cp0;
124 BaseCPU *cpu;
125 CP0EventType cp0EventType;
126 Fault fault;
127
128 public:
129 /** Constructs a CP0 event. */
130 CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type);
131
132 /** Process this event. */
133 virtual void process();
134
135 /** Returns the description of this event. */
136 const char *description() const;
137
138 /** Schedule This Event */
139 void scheduleEvent(Cycles delay);
140
141 /** Unschedule This Event */
142 void unscheduleEvent();
143 };
144
145 // Schedule a CP0 Update Event
146 void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
147
148 // If any changes have been made, then check the state for changes
149 // and if necessary alert the CPU
150 void updateCPU(BaseCPU *cpu);
151
152 // Keep a List of CPU Events that need to be deallocated
153 std::queue<CP0Event*> cp0EventRemoveList;
154
155 static std::string miscRegNames[NumMiscRegs];
156
157 public:
158
159 int
160 flattenIntIndex(int reg)
161 {
162 return reg;
163 }
164
165 int
166 flattenFloatIndex(int reg)
167 {
168 return reg;
169 }
170
171 void serialize(EventManager *em, std::ostream &os)
172 {}
173 void unserialize(EventManager *em, Checkpoint *cp,
174 const std::string &section)
175 {}
176 };
177}
178
179#endif