isa.cc (7823:dac01f14f20f) isa.cc (8181:f789b9aac5f4)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 72 unchanged lines hidden (view full) ---

81 "TagLo4", "DataLo5", "TagLo6", "DataLo7",
82 "TagHi0", "DataHi1", "TagHi2", "DataHi3",
83 "TagHi4", "DataHi5", "TagHi6", "DataHi7",
84 "ErrorEPC", "", "", "", "", "", "", "",
85 "DESAVE", "", "", "", "", "", "", "",
86 "LLFlag"
87};
88
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 72 unchanged lines hidden (view full) ---

81 "TagLo4", "DataLo5", "TagLo6", "DataLo7",
82 "TagHi0", "DataHi1", "TagHi2", "DataHi3",
83 "TagHi4", "DataHi5", "TagHi6", "DataHi7",
84 "ErrorEPC", "", "", "", "", "", "", "",
85 "DESAVE", "", "", "", "", "", "", "",
86 "LLFlag"
87};
88
89ISA::ISA()
89ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
90{
90{
91 init();
92}
91 numThreads = num_threads;
92 numVpes = num_vpes;
93
93
94void
95ISA::init()
96{
97 miscRegFile.resize(NumMiscRegs);
98 bankType.resize(NumMiscRegs);
99
100 for (int i=0; i < NumMiscRegs; i++) {
101 miscRegFile[i].resize(1);
102 bankType[i] = perProcessor;
103 }
104
105 miscRegFile_WriteMask.resize(NumMiscRegs);
106
107 for (int i = 0; i < NumMiscRegs; i++) {
108 miscRegFile_WriteMask[i].push_back(0);
109 }
94 miscRegFile.resize(NumMiscRegs);
95 bankType.resize(NumMiscRegs);
96
97 for (int i=0; i < NumMiscRegs; i++) {
98 miscRegFile[i].resize(1);
99 bankType[i] = perProcessor;
100 }
101
102 miscRegFile_WriteMask.resize(NumMiscRegs);
103
104 for (int i = 0; i < NumMiscRegs; i++) {
105 miscRegFile_WriteMask[i].push_back(0);
106 }
110 clear(0);
111}
112
107
113void
114ISA::clear(unsigned tid_or_vpn)
115{
116 for(int i = 0; i < NumMiscRegs; i++) {
117 miscRegFile[i][tid_or_vpn] = 0;
118 miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
119 }
120}
121
122void
123ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
124{
125 // Initialize all Per-VPE regs
126 uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
127 MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
128 MISCREG_YQMASK,
129 MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
130 MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
131 MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
132 MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
133 MISCREG_EBASE
134 };
135 uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
136 for (int i = 0; i < num_vpe_regs; i++) {
108 // Initialize all Per-VPE regs
109 uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
110 MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
111 MISCREG_YQMASK,
112 MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
113 MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
114 MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
115 MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
116 MISCREG_EBASE
117 };
118 uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
119 for (int i = 0; i < num_vpe_regs; i++) {
137 if (num_vpes > 1) {
138 miscRegFile[per_vpe_regs[i]].resize(num_vpes);
120 if (numVpes > 1) {
121 miscRegFile[per_vpe_regs[i]].resize(numVpes);
139 }
140 bankType[per_vpe_regs[i]] = perVirtProcessor;
141 }
142
143 // Initialize all Per-TC regs
144 uint32_t per_tc_regs[] = { MISCREG_STATUS,
145 MISCREG_TC_STATUS, MISCREG_TC_BIND,
146 MISCREG_TC_RESTART, MISCREG_TC_HALT,
147 MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
148 MISCREG_TC_SCHEFBACK,
149 MISCREG_DEBUG, MISCREG_LLADDR
150 };
151 uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
152
153 for (int i = 0; i < num_tc_regs; i++) {
122 }
123 bankType[per_vpe_regs[i]] = perVirtProcessor;
124 }
125
126 // Initialize all Per-TC regs
127 uint32_t per_tc_regs[] = { MISCREG_STATUS,
128 MISCREG_TC_STATUS, MISCREG_TC_BIND,
129 MISCREG_TC_RESTART, MISCREG_TC_HALT,
130 MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
131 MISCREG_TC_SCHEFBACK,
132 MISCREG_DEBUG, MISCREG_LLADDR
133 };
134 uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
135
136 for (int i = 0; i < num_tc_regs; i++) {
154 miscRegFile[per_tc_regs[i]].resize(num_threads);
137 miscRegFile[per_tc_regs[i]].resize(numThreads);
155 bankType[per_tc_regs[i]] = perThreadContext;
156 }
157
138 bankType[per_tc_regs[i]] = perThreadContext;
139 }
140
141 clear();
142}
158
143
159 if (num_vpes > 1) {
160 for (int i=1; i < num_vpes; i++) {
161 clear(i);
162 }
163 }
144void
145ISA::clear()
146{
147 for(int i = 0; i < NumMiscRegs; i++) {
148 for (int j = 0; j < miscRegFile[i].size(); j++)
149 miscRegFile[i][j] = 0;
164
150
151 for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
152 miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
153 }
165}
166
154}
155
167//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
156
168void
157void
169ISA::reset(std::string core_name, ThreadID num_threads,
170 unsigned num_vpes, BaseCPU *cpu)
158ISA::configCP()
171{
172 DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
159{
160 DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
173 num_threads, num_vpes);
161 numThreads, numVpes);
174
162
175 MipsISA::CoreSpecific &cp = cpu->coreParams;
163 CoreSpecific cp;
164 panic("CP state must be set before the following code is used");
176
177 // Do Default CP0 initialization HERE
178
179 // Do Initialization for MT cores here (eventually use
180 // core_name parameter to toggle this initialization)
181 // ===================================================
182 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
183

--- 161 unchanged lines hidden (view full) ---

345 MiscReg stat_Mask = 0xFF78FF17;
346 replaceBits(stat_Mask, 0, 32, 0);
347 setRegMask(MISCREG_STATUS, stat_Mask);
348
349
350 // MVPConf0
351 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
352 mvpConf0.tca = 1;
165
166 // Do Default CP0 initialization HERE
167
168 // Do Initialization for MT cores here (eventually use
169 // core_name parameter to toggle this initialization)
170 // ===================================================
171 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
172

--- 161 unchanged lines hidden (view full) ---

334 MiscReg stat_Mask = 0xFF78FF17;
335 replaceBits(stat_Mask, 0, 32, 0);
336 setRegMask(MISCREG_STATUS, stat_Mask);
337
338
339 // MVPConf0
340 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
341 mvpConf0.tca = 1;
353 mvpConf0.pvpe = num_vpes - 1;
354 mvpConf0.ptc = num_threads - 1;
342 mvpConf0.pvpe = numVpes - 1;
343 mvpConf0.ptc = numThreads - 1;
355 setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
356
357 // VPEConf0
358 VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
359 vpeConf0.mvp = 1;
360 setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
361
362 // TCBind
344 setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
345
346 // VPEConf0
347 VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
348 vpeConf0.mvp = 1;
349 setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
350
351 // TCBind
363 for (ThreadID tid = 0; tid < num_threads; tid++) {
352 for (ThreadID tid = 0; tid < numThreads; tid++) {
364 TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
365 tcBind.curTC = tid;
366 setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
367 }
368 // TCHalt
369 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
370 tcHalt.h = 0;
371 setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
372
373 // TCStatus
374 // Set TCStatus Activated to 1 for the initial thread that is running
375 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
376 tcStatus.a = 1;
377 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
378
379 // Set Dynamically Allocatable bit to 1 for all other threads
353 TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
354 tcBind.curTC = tid;
355 setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
356 }
357 // TCHalt
358 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
359 tcHalt.h = 0;
360 setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
361
362 // TCStatus
363 // Set TCStatus Activated to 1 for the initial thread that is running
364 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
365 tcStatus.a = 1;
366 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
367
368 // Set Dynamically Allocatable bit to 1 for all other threads
380 for (ThreadID tid = 1; tid < num_threads; tid++) {
369 for (ThreadID tid = 1; tid < numThreads; tid++) {
381 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
382 tcStatus.da = 1;
383 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
384 }
385
386
387 MiscReg mask = 0x7FFFFFFF;
388

--- 210 unchanged lines hidden --- 		370 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
371 tcStatus.da = 1;
372 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
373 }
374
375
376 MiscReg mask = 0x7FFFFFFF;
377

--- 210 unchanged lines hidden ---