isa.cc (6383:31c067ae3331) isa.cc (6806:45879b0e3240)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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86 "LLFlag"
87};
88
89ISA::ISA()
90{
91 init();
92}
93
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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86 "LLFlag"
87};
88
89ISA::ISA()
90{
91 init();
92}
93
94ISA::ISA(BaseCPU *_cpu)
95{
96 cpu = _cpu;
97 init();
98}
99
100void
101ISA::init()
102{
103 miscRegFile.resize(NumMiscRegs);
104 bankType.resize(NumMiscRegs);
105
106 for (int i=0; i < NumMiscRegs; i++) {
107 miscRegFile[i].resize(1);

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168 }
169 }
170
171}
172
173//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
174void
175ISA::reset(std::string core_name, ThreadID num_threads,
94void
95ISA::init()
96{
97 miscRegFile.resize(NumMiscRegs);
98 bankType.resize(NumMiscRegs);
99
100 for (int i=0; i < NumMiscRegs; i++) {
101 miscRegFile[i].resize(1);

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162 }
163 }
164
165}
166
167//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
168void
169ISA::reset(std::string core_name, ThreadID num_threads,
176 unsigned num_vpes, BaseCPU *_cpu)
170 unsigned num_vpes, BaseCPU *cpu)
177{
178 DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
179 num_threads, num_vpes);
171{
172 DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
173 num_threads, num_vpes);
180 cpu = _cpu;
181
182 MipsISA::CoreSpecific &cp = cpu->coreParams;
183
184 // Do Default CP0 initialization HERE
185
186 // Do Initialization for MT cores here (eventually use
187 // core_name parameter to toggle this initialization)
188 // ===================================================

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494 "[tid:%i]: Setting CP0 Register:%u "
495 "Select:%u (%s) to %#x, with effect.\n",
496 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
497
498 MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
499
500 miscRegFile[misc_reg][reg_sel] = cp0_val;
501
174
175 MipsISA::CoreSpecific &cp = cpu->coreParams;
176
177 // Do Default CP0 initialization HERE
178
179 // Do Initialization for MT cores here (eventually use
180 // core_name parameter to toggle this initialization)
181 // ===================================================

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487 "[tid:%i]: Setting CP0 Register:%u "
488 "Select:%u (%s) to %#x, with effect.\n",
489 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
490
491 MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
492
493 miscRegFile[misc_reg][reg_sel] = cp0_val;
494
502 scheduleCP0Update(1);
495 scheduleCP0Update(tc->getCpuPtr(), 1);
503}
504
505/**
506 * This method doesn't need to adjust the Control Register Offset
507 * since it has already been done in the calling method
508 * (setRegWithEffect)
509*/
510MiscReg

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523 "current val: %lx, written val: %x\n",
524 miscRegFile_WriteMask[misc_reg][reg_sel],
525 ~miscRegFile_WriteMask[misc_reg][reg_sel],
526 val, miscRegFile[misc_reg][reg_sel], retVal);
527 return retVal;
528}
529
530void
496}
497
498/**
499 * This method doesn't need to adjust the Control Register Offset
500 * since it has already been done in the calling method
501 * (setRegWithEffect)
502*/
503MiscReg

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516 "current val: %lx, written val: %x\n",
517 miscRegFile_WriteMask[misc_reg][reg_sel],
518 ~miscRegFile_WriteMask[misc_reg][reg_sel],
519 val, miscRegFile[misc_reg][reg_sel], retVal);
520 return retVal;
521}
522
523void
531ISA::scheduleCP0Update(int delay)
524ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
532{
533 if (!cp0Updated) {
534 cp0Updated = true;
535
536 //schedule UPDATE
537 CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
538 cpu->schedule(cp0_event, curTick + cpu->ticks(delay));
539 }
540}
541
542void
525{
526 if (!cp0Updated) {
527 cp0Updated = true;
528
529 //schedule UPDATE
530 CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
531 cpu->schedule(cp0_event, curTick + cpu->ticks(delay));
532 }
533}
534
535void
543ISA::updateCPU()
536ISA::updateCPU(BaseCPU *cpu)
544{
545 ///////////////////////////////////////////////////////////////////
546 //
547 // EVALUATE CP0 STATE FOR MIPS MT
548 //
549 ///////////////////////////////////////////////////////////////////
550 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
551 ThreadID num_threads = mvpConf0.ptc + 1;

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573{ }
574
575void
576ISA::CP0Event::process()
577{
578 switch (cp0EventType)
579 {
580 case UpdateCP0:
537{
538 ///////////////////////////////////////////////////////////////////
539 //
540 // EVALUATE CP0 STATE FOR MIPS MT
541 //
542 ///////////////////////////////////////////////////////////////////
543 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
544 ThreadID num_threads = mvpConf0.ptc + 1;

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566{ }
567
568void
569ISA::CP0Event::process()
570{
571 switch (cp0EventType)
572 {
573 case UpdateCP0:
581 cp0->updateCPU();
574 cp0->updateCPU(cpu);
582 break;
583 }
584}
585
586const char *
587ISA::CP0Event::description() const
588{
589 return "Coprocessor-0 event";

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576 }
577}
578
579const char *
580ISA::CP0Event::description() const
581{
582 return "Coprocessor-0 event";

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