isa.cc (6378:4a2ff62c3b4f) isa.cc (6383:31c067ae3331)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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124 miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
125 }
126}
127
128void
129ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
130{
131 // Initialize all Per-VPE regs
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 115 unchanged lines hidden (view full) ---

124 miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
125 }
126}
127
128void
129ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
130{
131 // Initialize all Per-VPE regs
132 uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask,
133 VPESchedule, VPEScheFBack, VPEOpt, SRSConf0,
134 SRSConf1, SRSConf2, SRSConf3, SRSConf4,
135 EBase
132 uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
133 MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
134 MISCREG_YQMASK,
135 MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
136 MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
137 MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
138 MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
139 MISCREG_EBASE
136 };
137 uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
138 for (int i = 0; i < num_vpe_regs; i++) {
139 if (num_vpes > 1) {
140 miscRegFile[per_vpe_regs[i]].resize(num_vpes);
141 }
142 bankType[per_vpe_regs[i]] = perVirtProcessor;
143 }
144
145 // Initialize all Per-TC regs
140 };
141 uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
142 for (int i = 0; i < num_vpe_regs; i++) {
143 if (num_vpes > 1) {
144 miscRegFile[per_vpe_regs[i]].resize(num_vpes);
145 }
146 bankType[per_vpe_regs[i]] = perVirtProcessor;
147 }
148
149 // Initialize all Per-TC regs
146 uint32_t per_tc_regs[] = { Status, TCStatus, TCBind, TCRestart, TCHalt,
147 TCContext, TCSchedule, TCScheFBack, Debug,
148 LLAddr
150 uint32_t per_tc_regs[] = { MISCREG_STATUS,
151 MISCREG_TC_STATUS, MISCREG_TC_BIND,
152 MISCREG_TC_RESTART, MISCREG_TC_HALT,
153 MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
154 MISCREG_TC_SCHEFBACK,
155 MISCREG_DEBUG, MISCREG_LLADDR
149 };
150 uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
151
152 for (int i = 0; i < num_tc_regs; i++) {
153 miscRegFile[per_tc_regs[i]].resize(num_threads);
154 bankType[per_tc_regs[i]] = perThreadContext;
155 }
156

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176
177 // Do Default CP0 initialization HERE
178
179 // Do Initialization for MT cores here (eventually use
180 // core_name parameter to toggle this initialization)
181 // ===================================================
182 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
183
156 };
157 uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
158
159 for (int i = 0; i < num_tc_regs; i++) {
160 miscRegFile[per_tc_regs[i]].resize(num_threads);
161 bankType[per_tc_regs[i]] = perThreadContext;
162 }
163

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183
184 // Do Default CP0 initialization HERE
185
186 // Do Initialization for MT cores here (eventually use
187 // core_name parameter to toggle this initialization)
188 // ===================================================
189 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
190
184 PRIdReg procId = readMiscRegNoEffect(PRId);
191 PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
185 procId.coOp = cp.CP0_PRId_CompanyOptions;
186 procId.coId = cp.CP0_PRId_CompanyID;
187 procId.procId = cp.CP0_PRId_ProcessorID;
188 procId.rev = cp.CP0_PRId_Revision;
192 procId.coOp = cp.CP0_PRId_CompanyOptions;
193 procId.coId = cp.CP0_PRId_CompanyID;
194 procId.procId = cp.CP0_PRId_ProcessorID;
195 procId.rev = cp.CP0_PRId_Revision;
189 setMiscRegNoEffect(PRId, procId);
196 setMiscRegNoEffect(MISCREG_PRID, procId);
190
191 // Now, create Write Mask for ProcID register
197
198 // Now, create Write Mask for ProcID register
192 MiscReg ProcID_Mask = 0; // Read-Only register
193 replaceBits(ProcID_Mask, 0, 32, 0);
194 setRegMask(PRId, ProcID_Mask);
199 MiscReg procIDMask = 0; // Read-Only register
200 replaceBits(procIDMask, 0, 32, 0);
201 setRegMask(MISCREG_PRID, procIDMask);
195
196 // Config
202
203 // Config
197 ConfigReg cfg = readMiscRegNoEffect(Config);
204 ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
198 cfg.be = cp.CP0_Config_BE;
199 cfg.at = cp.CP0_Config_AT;
200 cfg.ar = cp.CP0_Config_AR;
201 cfg.mt = cp.CP0_Config_MT;
202 cfg.vi = cp.CP0_Config_VI;
203 cfg.m = 1;
205 cfg.be = cp.CP0_Config_BE;
206 cfg.at = cp.CP0_Config_AT;
207 cfg.ar = cp.CP0_Config_AR;
208 cfg.mt = cp.CP0_Config_MT;
209 cfg.vi = cp.CP0_Config_VI;
210 cfg.m = 1;
204 setMiscRegNoEffect(Config, cfg);
211 setMiscRegNoEffect(MISCREG_CONFIG, cfg);
205 // Now, create Write Mask for Config register
206 MiscReg cfg_Mask = 0x7FFF0007;
207 replaceBits(cfg_Mask, 0, 32, 0);
212 // Now, create Write Mask for Config register
213 MiscReg cfg_Mask = 0x7FFF0007;
214 replaceBits(cfg_Mask, 0, 32, 0);
208 setRegMask(Config, cfg_Mask);
215 setRegMask(MISCREG_CONFIG, cfg_Mask);
209
210 // Config1
216
217 // Config1
211 Config1Reg cfg1 = readMiscRegNoEffect(Config1);
218 Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
212 cfg1.mmuSize = cp.CP0_Config1_MMU;
213 cfg1.is = cp.CP0_Config1_IS;
214 cfg1.il = cp.CP0_Config1_IL;
215 cfg1.ia = cp.CP0_Config1_IA;
216 cfg1.ds = cp.CP0_Config1_DS;
217 cfg1.dl = cp.CP0_Config1_DL;
218 cfg1.da = cp.CP0_Config1_DA;
219 cfg1.fp = cp.CP0_Config1_FP;
220 cfg1.ep = cp.CP0_Config1_EP;
221 cfg1.wr = cp.CP0_Config1_WR;
222 cfg1.md = cp.CP0_Config1_MD;
223 cfg1.c2 = cp.CP0_Config1_C2;
224 cfg1.pc = cp.CP0_Config1_PC;
225 cfg1.m = cp.CP0_Config1_M;
219 cfg1.mmuSize = cp.CP0_Config1_MMU;
220 cfg1.is = cp.CP0_Config1_IS;
221 cfg1.il = cp.CP0_Config1_IL;
222 cfg1.ia = cp.CP0_Config1_IA;
223 cfg1.ds = cp.CP0_Config1_DS;
224 cfg1.dl = cp.CP0_Config1_DL;
225 cfg1.da = cp.CP0_Config1_DA;
226 cfg1.fp = cp.CP0_Config1_FP;
227 cfg1.ep = cp.CP0_Config1_EP;
228 cfg1.wr = cp.CP0_Config1_WR;
229 cfg1.md = cp.CP0_Config1_MD;
230 cfg1.c2 = cp.CP0_Config1_C2;
231 cfg1.pc = cp.CP0_Config1_PC;
232 cfg1.m = cp.CP0_Config1_M;
226 setMiscRegNoEffect(Config1, cfg1);
233 setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
227 // Now, create Write Mask for Config register
228 MiscReg cfg1_Mask = 0; // Read Only Register
229 replaceBits(cfg1_Mask, 0, 32, 0);
234 // Now, create Write Mask for Config register
235 MiscReg cfg1_Mask = 0; // Read Only Register
236 replaceBits(cfg1_Mask, 0, 32, 0);
230 setRegMask(Config1, cfg1_Mask);
237 setRegMask(MISCREG_CONFIG1, cfg1_Mask);
231
232 // Config2
238
239 // Config2
233 Config2Reg cfg2 = readMiscRegNoEffect(Config2);
240 Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
234 cfg2.tu = cp.CP0_Config2_TU;
235 cfg2.ts = cp.CP0_Config2_TS;
236 cfg2.tl = cp.CP0_Config2_TL;
237 cfg2.ta = cp.CP0_Config2_TA;
238 cfg2.su = cp.CP0_Config2_SU;
239 cfg2.ss = cp.CP0_Config2_SS;
240 cfg2.sl = cp.CP0_Config2_SL;
241 cfg2.sa = cp.CP0_Config2_SA;
242 cfg2.m = cp.CP0_Config2_M;
241 cfg2.tu = cp.CP0_Config2_TU;
242 cfg2.ts = cp.CP0_Config2_TS;
243 cfg2.tl = cp.CP0_Config2_TL;
244 cfg2.ta = cp.CP0_Config2_TA;
245 cfg2.su = cp.CP0_Config2_SU;
246 cfg2.ss = cp.CP0_Config2_SS;
247 cfg2.sl = cp.CP0_Config2_SL;
248 cfg2.sa = cp.CP0_Config2_SA;
249 cfg2.m = cp.CP0_Config2_M;
243 setMiscRegNoEffect(Config2, cfg2);
250 setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
244 // Now, create Write Mask for Config register
245 MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
246 replaceBits(cfg2_Mask, 0, 32, 0);
251 // Now, create Write Mask for Config register
252 MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
253 replaceBits(cfg2_Mask, 0, 32, 0);
247 setRegMask(Config2, cfg2_Mask);
254 setRegMask(MISCREG_CONFIG2, cfg2_Mask);
248
249 // Config3
255
256 // Config3
250 Config3Reg cfg3 = readMiscRegNoEffect(Config3);
257 Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
251 cfg3.dspp = cp.CP0_Config3_DSPP;
252 cfg3.lpa = cp.CP0_Config3_LPA;
253 cfg3.veic = cp.CP0_Config3_VEIC;
254 cfg3.vint = cp.CP0_Config3_VInt;
255 cfg3.sp = cp.CP0_Config3_SP;
256 cfg3.mt = cp.CP0_Config3_MT;
257 cfg3.sm = cp.CP0_Config3_SM;
258 cfg3.tl = cp.CP0_Config3_TL;
258 cfg3.dspp = cp.CP0_Config3_DSPP;
259 cfg3.lpa = cp.CP0_Config3_LPA;
260 cfg3.veic = cp.CP0_Config3_VEIC;
261 cfg3.vint = cp.CP0_Config3_VInt;
262 cfg3.sp = cp.CP0_Config3_SP;
263 cfg3.mt = cp.CP0_Config3_MT;
264 cfg3.sm = cp.CP0_Config3_SM;
265 cfg3.tl = cp.CP0_Config3_TL;
259 setMiscRegNoEffect(Config3, cfg3);
266 setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
260 // Now, create Write Mask for Config register
261 MiscReg cfg3_Mask = 0; // Read Only Register
262 replaceBits(cfg3_Mask, 0, 32, 0);
267 // Now, create Write Mask for Config register
268 MiscReg cfg3_Mask = 0; // Read Only Register
269 replaceBits(cfg3_Mask, 0, 32, 0);
263 setRegMask(Config3, cfg3_Mask);
270 setRegMask(MISCREG_CONFIG3, cfg3_Mask);
264
265 // EBase - CPUNum
271
272 // EBase - CPUNum
266 EBaseReg eBase = readMiscRegNoEffect(EBase);
273 EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
267 eBase.cpuNum = cp.CP0_EBase_CPUNum;
268 replaceBits(eBase, 31, 31, 1);
274 eBase.cpuNum = cp.CP0_EBase_CPUNum;
275 replaceBits(eBase, 31, 31, 1);
269 setMiscRegNoEffect(EBase, eBase);
276 setMiscRegNoEffect(MISCREG_EBASE, eBase);
270 // Now, create Write Mask for Config register
271 MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
272 // entire register is read only
273 replaceBits(EB_Mask, 0, 32, 0);
277 // Now, create Write Mask for Config register
278 MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
279 // entire register is read only
280 replaceBits(EB_Mask, 0, 32, 0);
274 setRegMask(EBase, EB_Mask);
281 setRegMask(MISCREG_EBASE, EB_Mask);
275
276 // SRS Control - HSS (Highest Shadow Set)
282
283 // SRS Control - HSS (Highest Shadow Set)
277 SRSCtlReg scsCtl = readMiscRegNoEffect(SRSCtl);
284 SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
278 scsCtl.hss = cp.CP0_SrsCtl_HSS;
285 scsCtl.hss = cp.CP0_SrsCtl_HSS;
279 setMiscRegNoEffect(SRSCtl, scsCtl);
286 setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
280 // Now, create Write Mask for the SRS Ctl register
281 MiscReg SC_Mask = 0x0000F3C0;
282 replaceBits(SC_Mask, 0, 32, 0);
287 // Now, create Write Mask for the SRS Ctl register
288 MiscReg SC_Mask = 0x0000F3C0;
289 replaceBits(SC_Mask, 0, 32, 0);
283 setRegMask(SRSCtl, SC_Mask);
290 setRegMask(MISCREG_SRSCTL, SC_Mask);
284
285 // IntCtl - IPTI, IPPCI
291
292 // IntCtl - IPTI, IPPCI
286 IntCtlReg intCtl = readMiscRegNoEffect(IntCtl);
293 IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
287 intCtl.ipti = cp.CP0_IntCtl_IPTI;
288 intCtl.ippci = cp.CP0_IntCtl_IPPCI;
294 intCtl.ipti = cp.CP0_IntCtl_IPTI;
295 intCtl.ippci = cp.CP0_IntCtl_IPPCI;
289 setMiscRegNoEffect(IntCtl, intCtl);
296 setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
290 // Now, create Write Mask for the IntCtl register
291 MiscReg IC_Mask = 0x000003E0;
292 replaceBits(IC_Mask, 0, 32, 0);
297 // Now, create Write Mask for the IntCtl register
298 MiscReg IC_Mask = 0x000003E0;
299 replaceBits(IC_Mask, 0, 32, 0);
293 setRegMask(IntCtl, IC_Mask);
300 setRegMask(MISCREG_INTCTL, IC_Mask);
294
295 // Watch Hi - M - FIXME (More than 1 Watch register)
301
302 // Watch Hi - M - FIXME (More than 1 Watch register)
296 WatchHiReg watchHi = readMiscRegNoEffect(WatchHi0);
303 WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
297 watchHi.m = cp.CP0_WatchHi_M;
304 watchHi.m = cp.CP0_WatchHi_M;
298 setMiscRegNoEffect(WatchHi0, watchHi);
305 setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
299 // Now, create Write Mask for the IntCtl register
300 MiscReg wh_Mask = 0x7FFF0FFF;
301 replaceBits(wh_Mask, 0, 32, 0);
306 // Now, create Write Mask for the IntCtl register
307 MiscReg wh_Mask = 0x7FFF0FFF;
308 replaceBits(wh_Mask, 0, 32, 0);
302 setRegMask(WatchHi0, wh_Mask);
309 setRegMask(MISCREG_WATCHHI0, wh_Mask);
303
304 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
310
311 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
305 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(PerfCnt0);
312 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
306 perfCntCtl.m = cp.CP0_PerfCtr_M;
307 perfCntCtl.w = cp.CP0_PerfCtr_W;
313 perfCntCtl.m = cp.CP0_PerfCtr_M;
314 perfCntCtl.w = cp.CP0_PerfCtr_W;
308 setMiscRegNoEffect(PerfCnt0, perfCntCtl);
315 setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
309 // Now, create Write Mask for the IntCtl register
310 MiscReg pc_Mask = 0x00007FF;
311 replaceBits(pc_Mask, 0, 32, 0);
316 // Now, create Write Mask for the IntCtl register
317 MiscReg pc_Mask = 0x00007FF;
318 replaceBits(pc_Mask, 0, 32, 0);
312 setRegMask(PerfCnt0, pc_Mask);
319 setRegMask(MISCREG_PERFCNT0, pc_Mask);
313
314 // Random
320
321 // Random
315 setMiscRegNoEffect(CP0_Random, 63);
322 setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
316 // Now, create Write Mask for the IntCtl register
317 MiscReg random_Mask = 0;
318 replaceBits(random_Mask, 0, 32, 0);
323 // Now, create Write Mask for the IntCtl register
324 MiscReg random_Mask = 0;
325 replaceBits(random_Mask, 0, 32, 0);
319 setRegMask(CP0_Random, random_Mask);
326 setRegMask(MISCREG_CP0_RANDOM, random_Mask);
320
321 // PageGrain
327
328 // PageGrain
322 PageGrainReg pageGrain = readMiscRegNoEffect(PageGrain);
329 PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
323 pageGrain.esp = cp.CP0_Config3_SP;
330 pageGrain.esp = cp.CP0_Config3_SP;
324 setMiscRegNoEffect(PageGrain, pageGrain);
331 setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
325 // Now, create Write Mask for the IntCtl register
326 MiscReg pg_Mask = 0x10000000;
327 replaceBits(pg_Mask, 0, 32, 0);
332 // Now, create Write Mask for the IntCtl register
333 MiscReg pg_Mask = 0x10000000;
334 replaceBits(pg_Mask, 0, 32, 0);
328 setRegMask(PageGrain, pg_Mask);
335 setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
329
330 // Status
336
337 // Status
331 StatusReg status = readMiscRegNoEffect(Status);
338 StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
332 // Only CU0 and IE are modified on a reset - everything else needs
333 // to be controlled on a per CPU model basis
334
335 // Enable CP0 on reset
336 // status.cu0 = 1;
337
338 // Enable ERL bit on a reset
339 status.erl = 1;
340 // Enable BEV bit on a reset
341 status.bev = 1;
342
339 // Only CU0 and IE are modified on a reset - everything else needs
340 // to be controlled on a per CPU model basis
341
342 // Enable CP0 on reset
343 // status.cu0 = 1;
344
345 // Enable ERL bit on a reset
346 status.erl = 1;
347 // Enable BEV bit on a reset
348 status.bev = 1;
349
343 setMiscRegNoEffect(Status, status);
350 setMiscRegNoEffect(MISCREG_STATUS, status);
344 // Now, create Write Mask for the Status register
345 MiscReg stat_Mask = 0xFF78FF17;
346 replaceBits(stat_Mask, 0, 32, 0);
351 // Now, create Write Mask for the Status register
352 MiscReg stat_Mask = 0xFF78FF17;
353 replaceBits(stat_Mask, 0, 32, 0);
347 setRegMask(Status, stat_Mask);
354 setRegMask(MISCREG_STATUS, stat_Mask);
348
349
350 // MVPConf0
355
356
357 // MVPConf0
351 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0);
358 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
352 mvpConf0.tca = 1;
353 mvpConf0.pvpe = num_vpes - 1;
354 mvpConf0.ptc = num_threads - 1;
359 mvpConf0.tca = 1;
360 mvpConf0.pvpe = num_vpes - 1;
361 mvpConf0.ptc = num_threads - 1;
355 setMiscRegNoEffect(MVPConf0, mvpConf0);
362 setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
356
357 // VPEConf0
363
364 // VPEConf0
358 VPEConf0Reg vpeConf0 = readMiscRegNoEffect(VPEConf0);
365 VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
359 vpeConf0.mvp = 1;
366 vpeConf0.mvp = 1;
360 setMiscRegNoEffect(VPEConf0, vpeConf0);
367 setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
361
362 // TCBind
363 for (ThreadID tid = 0; tid < num_threads; tid++) {
368
369 // TCBind
370 for (ThreadID tid = 0; tid < num_threads; tid++) {
364 TCBindReg tcBind = readMiscRegNoEffect(TCBind, tid);
371 TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
365 tcBind.curTC = tid;
372 tcBind.curTC = tid;
366 setMiscRegNoEffect(TCBind, tcBind, tid);
373 setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
367 }
368 // TCHalt
374 }
375 // TCHalt
369 TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt);
376 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
370 tcHalt.h = 0;
377 tcHalt.h = 0;
371 setMiscRegNoEffect(TCHalt, tcHalt);
378 setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
372
373 // TCStatus
374 // Set TCStatus Activated to 1 for the initial thread that is running
379
380 // TCStatus
381 // Set TCStatus Activated to 1 for the initial thread that is running
375 TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus);
382 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
376 tcStatus.a = 1;
383 tcStatus.a = 1;
377 setMiscRegNoEffect(TCStatus, tcStatus);
384 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
378
379 // Set Dynamically Allocatable bit to 1 for all other threads
380 for (ThreadID tid = 1; tid < num_threads; tid++) {
385
386 // Set Dynamically Allocatable bit to 1 for all other threads
387 for (ThreadID tid = 1; tid < num_threads; tid++) {
381 tcStatus = readMiscRegNoEffect(TCStatus, tid);
388 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
382 tcStatus.da = 1;
389 tcStatus.da = 1;
383 setMiscRegNoEffect(TCStatus, tcStatus, tid);
390 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
384 }
385
386
391 }
392
393
387 MiscReg Mask = 0x7FFFFFFF;
394 MiscReg mask = 0x7FFFFFFF;
388
389 // Now, create Write Mask for the Index register
395
396 // Now, create Write Mask for the Index register
390 replaceBits(Mask, 0, 32, 0);
391 setRegMask(Index, Mask);
397 replaceBits(mask, 0, 32, 0);
398 setRegMask(MISCREG_INDEX, mask);
392
399
393 Mask = 0x3FFFFFFF;
394 replaceBits(Mask, 0, 32, 0);
395 setRegMask(EntryLo0, Mask);
396 setRegMask(EntryLo1, Mask);
400 mask = 0x3FFFFFFF;
401 replaceBits(mask, 0, 32, 0);
402 setRegMask(MISCREG_ENTRYLO0, mask);
403 setRegMask(MISCREG_ENTRYLO1, mask);
397
404
398 Mask = 0xFF800000;
399 replaceBits(Mask, 0, 32, 0);
400 setRegMask(Context, Mask);
405 mask = 0xFF800000;
406 replaceBits(mask, 0, 32, 0);
407 setRegMask(MISCREG_CONTEXT, mask);
401
408
402 Mask = 0x1FFFF800;
403 replaceBits(Mask, 0, 32, 0);
404 setRegMask(PageMask, Mask);
409 mask = 0x1FFFF800;
410 replaceBits(mask, 0, 32, 0);
411 setRegMask(MISCREG_PAGEMASK, mask);
405
412
406 Mask = 0x0;
407 replaceBits(Mask, 0, 32, 0);
408 setRegMask(BadVAddr, Mask);
409 setRegMask(LLAddr, Mask);
413 mask = 0x0;
414 replaceBits(mask, 0, 32, 0);
415 setRegMask(MISCREG_BADVADDR, mask);
416 setRegMask(MISCREG_LLADDR, mask);
410
417
411 Mask = 0x08C00300;
412 replaceBits(Mask, 0, 32, 0);
413 setRegMask(Cause, Mask);
418 mask = 0x08C00300;
419 replaceBits(mask, 0, 32, 0);
420 setRegMask(MISCREG_CAUSE, mask);
414
415}
416
417inline unsigned
418ISA::getVPENum(ThreadID tid)
419{
421
422}
423
424inline unsigned
425ISA::getVPENum(ThreadID tid)
426{
420 TCBindReg tcBind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
427 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
421 return tcBind.curVPE;
422}
423
424MiscReg
428 return tcBind.curVPE;
429}
430
431MiscReg
425ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid)
432ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
426{
433{
427 int misc_reg = reg_idx - Ctrl_Base_DepTag;
428 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
429 ? tid : getVPENum(tid);
430 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
431 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
432 miscRegFile[misc_reg][reg_sel]);
433 return miscRegFile[misc_reg][reg_sel];
434}
435
436//@TODO: MIPS MT's register view automatically connects
437// Status to TCStatus depending on current thread
438//template <class TC>
439MiscReg
434 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
435 ? tid : getVPENum(tid);
436 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
437 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
438 miscRegFile[misc_reg][reg_sel]);
439 return miscRegFile[misc_reg][reg_sel];
440}
441
442//@TODO: MIPS MT's register view automatically connects
443// Status to TCStatus depending on current thread
444//template <class TC>
445MiscReg
440ISA::readMiscReg(int reg_idx, ThreadContext *tc, ThreadID tid)
446ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
441{
447{
442 int misc_reg = reg_idx - Ctrl_Base_DepTag;
443 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
444 ? tid : getVPENum(tid);
445 DPRINTF(MipsPRA,
446 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
447 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
448 miscRegFile[misc_reg][reg_sel]);
449
450 return miscRegFile[misc_reg][reg_sel];
451}
452
453void
448 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
449 ? tid : getVPENum(tid);
450 DPRINTF(MipsPRA,
451 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
452 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
453 miscRegFile[misc_reg][reg_sel]);
454
455 return miscRegFile[misc_reg][reg_sel];
456}
457
458void
454ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid)
459ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
455{
460{
456 int misc_reg = reg_idx - Ctrl_Base_DepTag;
457 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
458 ? tid : getVPENum(tid);
459 DPRINTF(MipsPRA,
460 "[tid:%i]: Setting (direct set) CP0 Register:%u "
461 "Select:%u (%s) to %#x.\n",
462 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
463
464 miscRegFile[misc_reg][reg_sel] = val;
465}
466
467void
461 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
462 ? tid : getVPENum(tid);
463 DPRINTF(MipsPRA,
464 "[tid:%i]: Setting (direct set) CP0 Register:%u "
465 "Select:%u (%s) to %#x.\n",
466 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
467
468 miscRegFile[misc_reg][reg_sel] = val;
469}
470
471void
468ISA::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid)
472ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
469{
473{
470 // return;
471 int misc_reg = reg_idx - Ctrl_Base_DepTag;
472 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
473 ? tid : getVPENum(tid);
474 DPRINTF(MipsPRA,
475 "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
476 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
477 miscRegFile_WriteMask[misc_reg][reg_sel] = val;
478}
479
480// PROGRAMMER'S NOTES:
481// (1) Some CP0 Registers have fields that cannot
482// be overwritten. Make sure to handle those particular registers
483// with care!
484void
474 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
475 ? tid : getVPENum(tid);
476 DPRINTF(MipsPRA,
477 "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
478 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
479 miscRegFile_WriteMask[misc_reg][reg_sel] = val;
480}
481
482// PROGRAMMER'S NOTES:
483// (1) Some CP0 Registers have fields that cannot
484// be overwritten. Make sure to handle those particular registers
485// with care!
486void
485ISA::setMiscReg(int reg_idx, const MiscReg &val,
487ISA::setMiscReg(int misc_reg, const MiscReg &val,
486 ThreadContext *tc, ThreadID tid)
487{
488 ThreadContext *tc, ThreadID tid)
489{
488 int misc_reg = reg_idx - Ctrl_Base_DepTag;
489 int reg_sel = (bankType[misc_reg] == perThreadContext)
490 ? tid : getVPENum(tid);
491
492 DPRINTF(MipsPRA,
493 "[tid:%i]: Setting CP0 Register:%u "
494 "Select:%u (%s) to %#x, with effect.\n",
495 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
496

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541void
542ISA::updateCPU()
543{
544 ///////////////////////////////////////////////////////////////////
545 //
546 // EVALUATE CP0 STATE FOR MIPS MT
547 //
548 ///////////////////////////////////////////////////////////////////
490 int reg_sel = (bankType[misc_reg] == perThreadContext)
491 ? tid : getVPENum(tid);
492
493 DPRINTF(MipsPRA,
494 "[tid:%i]: Setting CP0 Register:%u "
495 "Select:%u (%s) to %#x, with effect.\n",
496 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
497

--- 44 unchanged lines hidden (view full) ---

542void
543ISA::updateCPU()
544{
545 ///////////////////////////////////////////////////////////////////
546 //
547 // EVALUATE CP0 STATE FOR MIPS MT
548 //
549 ///////////////////////////////////////////////////////////////////
549 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0);
550 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
550 ThreadID num_threads = mvpConf0.ptc + 1;
551
552 for (ThreadID tid = 0; tid < num_threads; tid++) {
551 ThreadID num_threads = mvpConf0.ptc + 1;
552
553 for (ThreadID tid = 0; tid < num_threads; tid++) {
553 TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus, tid);
554 TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt, tid);
554 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
555 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
555
556 //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
557 if (tcHalt.h == 1 || tcStatus.a == 0) {
558 haltThread(cpu->getContext(tid));
559 } else if (tcHalt.h == 0 && tcStatus.a == 1) {
560 restoreThread(cpu->getContext(tid));
561 }
562 }

--- 42 unchanged lines hidden --- 		556
557 //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
558 if (tcHalt.h == 1 || tcStatus.a == 0) {
559 haltThread(cpu->getContext(tid));
560 } else if (tcHalt.h == 0 && tcStatus.a == 1) {
561 restoreThread(cpu->getContext(tid));
562 }
563 }

--- 42 unchanged lines hidden ---