isa.cc (6376:eaf61ef6a8f2) isa.cc (6378:4a2ff62c3b4f)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 433 unchanged lines hidden (view full) ---

442 int misc_reg = reg_idx - Ctrl_Base_DepTag;
443 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
444 ? tid : getVPENum(tid);
445 DPRINTF(MipsPRA,
446 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
447 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
448 miscRegFile[misc_reg][reg_sel]);
449
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 433 unchanged lines hidden (view full) ---

442 int misc_reg = reg_idx - Ctrl_Base_DepTag;
443 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
444 ? tid : getVPENum(tid);
445 DPRINTF(MipsPRA,
446 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
447 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
448 miscRegFile[misc_reg][reg_sel]);
449
450
451 switch (misc_reg)
452 {
453 default:
454 return miscRegFile[misc_reg][reg_sel];
455 }
450 return miscRegFile[misc_reg][reg_sel];
456}
457
458void
459ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid)
460{
461 int misc_reg = reg_idx - Ctrl_Base_DepTag;
462 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
463 ? tid : getVPENum(tid);

--- 17 unchanged lines hidden (view full) ---

481 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
482 miscRegFile_WriteMask[misc_reg][reg_sel] = val;
483}
484
485// PROGRAMMER'S NOTES:
486// (1) Some CP0 Registers have fields that cannot
487// be overwritten. Make sure to handle those particular registers
488// with care!
451}
452
453void
454ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid)
455{
456 int misc_reg = reg_idx - Ctrl_Base_DepTag;
457 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
458 ? tid : getVPENum(tid);

--- 17 unchanged lines hidden (view full) ---

476 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
477 miscRegFile_WriteMask[misc_reg][reg_sel] = val;
478}
479
480// PROGRAMMER'S NOTES:
481// (1) Some CP0 Registers have fields that cannot
482// be overwritten. Make sure to handle those particular registers
483// with care!
489//template <class TC>
490void
491ISA::setMiscReg(int reg_idx, const MiscReg &val,
492 ThreadContext *tc, ThreadID tid)
493{
494 int misc_reg = reg_idx - Ctrl_Base_DepTag;
495 int reg_sel = (bankType[misc_reg] == perThreadContext)
496 ? tid : getVPENum(tid);
497

--- 12 unchanged lines hidden (view full) ---

510/**
511 * This method doesn't need to adjust the Control Register Offset
512 * since it has already been done in the calling method
513 * (setRegWithEffect)
514*/
515MiscReg
516ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
517{
484void
485ISA::setMiscReg(int reg_idx, const MiscReg &val,
486 ThreadContext *tc, ThreadID tid)
487{
488 int misc_reg = reg_idx - Ctrl_Base_DepTag;
489 int reg_sel = (bankType[misc_reg] == perThreadContext)
490 ? tid : getVPENum(tid);
491

--- 12 unchanged lines hidden (view full) ---

504/**
505 * This method doesn't need to adjust the Control Register Offset
506 * since it has already been done in the calling method
507 * (setRegWithEffect)
508*/
509MiscReg
510ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
511{
518 MiscReg retVal = val;
512 MiscReg retVal = val;
519
513
520 // Mask off read-only regions
521 retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
522 MiscReg curVal = miscRegFile[misc_reg][reg_sel];
523 // Mask off current alue with inverse mask (clear writeable bits)
524 curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
525 retVal |= curVal; // Combine the two
526 DPRINTF(MipsPRA,
527 "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
528 "current val: %lx, written val: %x\n",
529 miscRegFile_WriteMask[misc_reg][reg_sel],
530 ~miscRegFile_WriteMask[misc_reg][reg_sel],
531 val, miscRegFile[misc_reg][reg_sel], retVal);
532 return retVal;
514 // Mask off read-only regions
515 retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
516 MiscReg curVal = miscRegFile[misc_reg][reg_sel];
517 // Mask off current alue with inverse mask (clear writeable bits)
518 curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
519 retVal |= curVal; // Combine the two
520 DPRINTF(MipsPRA,
521 "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
522 "current val: %lx, written val: %x\n",
523 miscRegFile_WriteMask[misc_reg][reg_sel],
524 ~miscRegFile_WriteMask[misc_reg][reg_sel],
525 val, miscRegFile[misc_reg][reg_sel], retVal);
526 return retVal;
533}
534
535void
536ISA::scheduleCP0Update(int delay)
537{
538 if (!cp0Updated) {
539 cp0Updated = true;
540

--- 40 unchanged lines hidden (view full) ---

581ISA::CP0Event::process()
582{
583 switch (cp0EventType)
584 {
585 case UpdateCP0:
586 cp0->updateCPU();
587 break;
588 }
527}
528
529void
530ISA::scheduleCP0Update(int delay)
531{
532 if (!cp0Updated) {
533 cp0Updated = true;
534

--- 40 unchanged lines hidden (view full) ---

575ISA::CP0Event::process()
576{
577 switch (cp0EventType)
578 {
579 case UpdateCP0:
580 cp0->updateCPU();
581 break;
582 }
589
590 //cp0EventRemoveList.push(this);
591}
592
593const char *
594ISA::CP0Event::description() const
595{
596 return "Coprocessor-0 event";
597}
598

--- 14 unchanged lines hidden --- 		583}
584
585const char *
586ISA::CP0Event::description() const
587{
588 return "Coprocessor-0 event";
589}
590

--- 14 unchanged lines hidden ---