isa.cc (6334:285b9886fee2) isa.cc (6376:eaf61ef6a8f2)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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105
106 for (int i=0; i < NumMiscRegs; i++) {
107 miscRegFile[i].resize(1);
108 bankType[i] = perProcessor;
109 }
110
111 miscRegFile_WriteMask.resize(NumMiscRegs);
112
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 96 unchanged lines hidden (view full) ---

105
106 for (int i=0; i < NumMiscRegs; i++) {
107 miscRegFile[i].resize(1);
108 bankType[i] = perProcessor;
109 }
110
111 miscRegFile_WriteMask.resize(NumMiscRegs);
112
113 for (int i=0; i < NumMiscRegs; i++) {
114 miscRegFile_WriteMask[i].push_back(0);
113 for (int i = 0; i < NumMiscRegs; i++) {
114 miscRegFile_WriteMask[i].push_back(0);
115 }
116 clear(0);
117}
118
119void
120ISA::clear(unsigned tid_or_vpn)
121{
122 for(int i = 0; i < NumMiscRegs; i++) {

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176
177 // Do Default CP0 initialization HERE
178
179 // Do Initialization for MT cores here (eventually use
180 // core_name parameter to toggle this initialization)
181 // ===================================================
182 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
183
115 }
116 clear(0);
117}
118
119void
120ISA::clear(unsigned tid_or_vpn)
121{
122 for(int i = 0; i < NumMiscRegs; i++) {

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176
177 // Do Default CP0 initialization HERE
178
179 // Do Initialization for MT cores here (eventually use
180 // core_name parameter to toggle this initialization)
181 // ===================================================
182 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
183
184 MiscReg ProcID = readMiscRegNoEffect(PRId);
185 replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,cp.CP0_PRId_CompanyOptions);
186 replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,cp.CP0_PRId_CompanyID);
187 replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,cp.CP0_PRId_ProcessorID);
188 replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,cp.CP0_PRId_Revision);
189 setMiscRegNoEffect(PRId,ProcID);
184 PRIdReg procId = readMiscRegNoEffect(PRId);
185 procId.coOp = cp.CP0_PRId_CompanyOptions;
186 procId.coId = cp.CP0_PRId_CompanyID;
187 procId.procId = cp.CP0_PRId_ProcessorID;
188 procId.rev = cp.CP0_PRId_Revision;
189 setMiscRegNoEffect(PRId, procId);
190
190 // Now, create Write Mask for ProcID register
191 MiscReg ProcID_Mask = 0; // Read-Only register
191 // Now, create Write Mask for ProcID register
192 MiscReg ProcID_Mask = 0; // Read-Only register
192 replaceBits(ProcID_Mask,0,32,0);
193 setRegMask(PRId,ProcID_Mask);
193 replaceBits(ProcID_Mask, 0, 32, 0);
194 setRegMask(PRId, ProcID_Mask);
194
195 // Config
195
196 // Config
196 MiscReg cfg = readMiscRegNoEffect(Config);
197 replaceBits(cfg, Config_BE_HI, Config_BE_LO, cp.CP0_Config_BE);
198 replaceBits(cfg, Config_AT_HI, Config_AT_LO, cp.CP0_Config_AT);
199 replaceBits(cfg, Config_AR_HI, Config_AR_LO, cp.CP0_Config_AR);
200 replaceBits(cfg, Config_MT_HI, Config_MT_LO, cp.CP0_Config_MT);
201 replaceBits(cfg, Config_VI_HI, Config_VI_LO, cp.CP0_Config_VI);
202 replaceBits(cfg, Config_M, 1);
197 ConfigReg cfg = readMiscRegNoEffect(Config);
198 cfg.be = cp.CP0_Config_BE;
199 cfg.at = cp.CP0_Config_AT;
200 cfg.ar = cp.CP0_Config_AR;
201 cfg.mt = cp.CP0_Config_MT;
202 cfg.vi = cp.CP0_Config_VI;
203 cfg.m = 1;
203 setMiscRegNoEffect(Config, cfg);
204 // Now, create Write Mask for Config register
205 MiscReg cfg_Mask = 0x7FFF0007;
204 setMiscRegNoEffect(Config, cfg);
205 // Now, create Write Mask for Config register
206 MiscReg cfg_Mask = 0x7FFF0007;
206 replaceBits(cfg_Mask,0,32,0);
207 setRegMask(Config,cfg_Mask);
207 replaceBits(cfg_Mask, 0, 32, 0);
208 setRegMask(Config, cfg_Mask);
208
209 // Config1
209
210 // Config1
210 MiscReg cfg1 = readMiscRegNoEffect(Config1);
211 replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO,
212 cp.CP0_Config1_MMU);
213 replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS);
214 replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, cp.CP0_Config1_IL);
215 replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, cp.CP0_Config1_IA);
216 replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, cp.CP0_Config1_DS);
217 replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, cp.CP0_Config1_DL);
218 replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, cp.CP0_Config1_DA);
219 replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, cp.CP0_Config1_FP);
220 replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, cp.CP0_Config1_EP);
221 replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, cp.CP0_Config1_WR);
222 replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, cp.CP0_Config1_MD);
223 replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, cp.CP0_Config1_C2);
224 replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, cp.CP0_Config1_PC);
225 replaceBits(cfg1, Config1_M, cp.CP0_Config1_M);
211 Config1Reg cfg1 = readMiscRegNoEffect(Config1);
212 cfg1.mmuSize = cp.CP0_Config1_MMU;
213 cfg1.is = cp.CP0_Config1_IS;
214 cfg1.il = cp.CP0_Config1_IL;
215 cfg1.ia = cp.CP0_Config1_IA;
216 cfg1.ds = cp.CP0_Config1_DS;
217 cfg1.dl = cp.CP0_Config1_DL;
218 cfg1.da = cp.CP0_Config1_DA;
219 cfg1.fp = cp.CP0_Config1_FP;
220 cfg1.ep = cp.CP0_Config1_EP;
221 cfg1.wr = cp.CP0_Config1_WR;
222 cfg1.md = cp.CP0_Config1_MD;
223 cfg1.c2 = cp.CP0_Config1_C2;
224 cfg1.pc = cp.CP0_Config1_PC;
225 cfg1.m = cp.CP0_Config1_M;
226 setMiscRegNoEffect(Config1, cfg1);
227 // Now, create Write Mask for Config register
228 MiscReg cfg1_Mask = 0; // Read Only Register
226 setMiscRegNoEffect(Config1, cfg1);
227 // Now, create Write Mask for Config register
228 MiscReg cfg1_Mask = 0; // Read Only Register
229 replaceBits(cfg1_Mask,0,32,0);
230 setRegMask(Config1,cfg1_Mask);
229 replaceBits(cfg1_Mask, 0, 32, 0);
230 setRegMask(Config1, cfg1_Mask);
231
232 // Config2
231
232 // Config2
233 MiscReg cfg2 = readMiscRegNoEffect(Config2);
234 replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, cp.CP0_Config2_TU);
235 replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, cp.CP0_Config2_TS);
236 replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, cp.CP0_Config2_TL);
237 replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, cp.CP0_Config2_TA);
238 replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, cp.CP0_Config2_SU);
239 replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, cp.CP0_Config2_SS);
240 replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, cp.CP0_Config2_SL);
241 replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, cp.CP0_Config2_SA);
242 replaceBits(cfg2, Config2_M, cp.CP0_Config2_M);
233 Config2Reg cfg2 = readMiscRegNoEffect(Config2);
234 cfg2.tu = cp.CP0_Config2_TU;
235 cfg2.ts = cp.CP0_Config2_TS;
236 cfg2.tl = cp.CP0_Config2_TL;
237 cfg2.ta = cp.CP0_Config2_TA;
238 cfg2.su = cp.CP0_Config2_SU;
239 cfg2.ss = cp.CP0_Config2_SS;
240 cfg2.sl = cp.CP0_Config2_SL;
241 cfg2.sa = cp.CP0_Config2_SA;
242 cfg2.m = cp.CP0_Config2_M;
243 setMiscRegNoEffect(Config2, cfg2);
244 // Now, create Write Mask for Config register
245 MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
243 setMiscRegNoEffect(Config2, cfg2);
244 // Now, create Write Mask for Config register
245 MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
246 replaceBits(cfg2_Mask,0,32,0);
247 setRegMask(Config2,cfg2_Mask);
246 replaceBits(cfg2_Mask, 0, 32, 0);
247 setRegMask(Config2, cfg2_Mask);
248
249 // Config3
248
249 // Config3
250 MiscReg cfg3 = readMiscRegNoEffect(Config3);
251 replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, cp.CP0_Config3_DSPP);
252 replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, cp.CP0_Config3_LPA);
253 replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, cp.CP0_Config3_VEIC);
254 replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, cp.CP0_Config3_VInt);
255 replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, cp.CP0_Config3_SP);
256 replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, cp.CP0_Config3_MT);
257 replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, cp.CP0_Config3_SM);
258 replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, cp.CP0_Config3_TL);
250 Config3Reg cfg3 = readMiscRegNoEffect(Config3);
251 cfg3.dspp = cp.CP0_Config3_DSPP;
252 cfg3.lpa = cp.CP0_Config3_LPA;
253 cfg3.veic = cp.CP0_Config3_VEIC;
254 cfg3.vint = cp.CP0_Config3_VInt;
255 cfg3.sp = cp.CP0_Config3_SP;
256 cfg3.mt = cp.CP0_Config3_MT;
257 cfg3.sm = cp.CP0_Config3_SM;
258 cfg3.tl = cp.CP0_Config3_TL;
259 setMiscRegNoEffect(Config3, cfg3);
260 // Now, create Write Mask for Config register
261 MiscReg cfg3_Mask = 0; // Read Only Register
259 setMiscRegNoEffect(Config3, cfg3);
260 // Now, create Write Mask for Config register
261 MiscReg cfg3_Mask = 0; // Read Only Register
262 replaceBits(cfg3_Mask,0,32,0);
263 setRegMask(Config3,cfg3_Mask);
262 replaceBits(cfg3_Mask, 0, 32, 0);
263 setRegMask(Config3, cfg3_Mask);
264
265 // EBase - CPUNum
264
265 // EBase - CPUNum
266 MiscReg EB = readMiscRegNoEffect(EBase);
267 replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, cp.CP0_EBase_CPUNum);
268 replaceBits(EB, 31, 31, 1);
269 setMiscRegNoEffect(EBase, EB);
266 EBaseReg eBase = readMiscRegNoEffect(EBase);
267 eBase.cpuNum = cp.CP0_EBase_CPUNum;
268 replaceBits(eBase, 31, 31, 1);
269 setMiscRegNoEffect(EBase, eBase);
270 // Now, create Write Mask for Config register
271 MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
272 // entire register is read only
270 // Now, create Write Mask for Config register
271 MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
272 // entire register is read only
273 replaceBits(EB_Mask,0,32,0);
274 setRegMask(EBase,EB_Mask);
273 replaceBits(EB_Mask, 0, 32, 0);
274 setRegMask(EBase, EB_Mask);
275
276 // SRS Control - HSS (Highest Shadow Set)
275
276 // SRS Control - HSS (Highest Shadow Set)
277 MiscReg SC = readMiscRegNoEffect(SRSCtl);
278 replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,cp.CP0_SrsCtl_HSS);
279 setMiscRegNoEffect(SRSCtl, SC);
277 SRSCtlReg scsCtl = readMiscRegNoEffect(SRSCtl);
278 scsCtl.hss = cp.CP0_SrsCtl_HSS;
279 setMiscRegNoEffect(SRSCtl, scsCtl);
280 // Now, create Write Mask for the SRS Ctl register
281 MiscReg SC_Mask = 0x0000F3C0;
280 // Now, create Write Mask for the SRS Ctl register
281 MiscReg SC_Mask = 0x0000F3C0;
282 replaceBits(SC_Mask,0,32,0);
283 setRegMask(SRSCtl,SC_Mask);
282 replaceBits(SC_Mask, 0, 32, 0);
283 setRegMask(SRSCtl, SC_Mask);
284
285 // IntCtl - IPTI, IPPCI
284
285 // IntCtl - IPTI, IPPCI
286 MiscReg IC = readMiscRegNoEffect(IntCtl);
287 replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,cp.CP0_IntCtl_IPTI);
288 replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,cp.CP0_IntCtl_IPPCI);
289 setMiscRegNoEffect(IntCtl, IC);
286 IntCtlReg intCtl = readMiscRegNoEffect(IntCtl);
287 intCtl.ipti = cp.CP0_IntCtl_IPTI;
288 intCtl.ippci = cp.CP0_IntCtl_IPPCI;
289 setMiscRegNoEffect(IntCtl, intCtl);
290 // Now, create Write Mask for the IntCtl register
291 MiscReg IC_Mask = 0x000003E0;
290 // Now, create Write Mask for the IntCtl register
291 MiscReg IC_Mask = 0x000003E0;
292 replaceBits(IC_Mask,0,32,0);
293 setRegMask(IntCtl,IC_Mask);
292 replaceBits(IC_Mask, 0, 32, 0);
293 setRegMask(IntCtl, IC_Mask);
294
295 // Watch Hi - M - FIXME (More than 1 Watch register)
294
295 // Watch Hi - M - FIXME (More than 1 Watch register)
296 MiscReg WHi = readMiscRegNoEffect(WatchHi0);
297 replaceBits(WHi, WatchHi_M, cp.CP0_WatchHi_M);
298 setMiscRegNoEffect(WatchHi0, WHi);
296 WatchHiReg watchHi = readMiscRegNoEffect(WatchHi0);
297 watchHi.m = cp.CP0_WatchHi_M;
298 setMiscRegNoEffect(WatchHi0, watchHi);
299 // Now, create Write Mask for the IntCtl register
300 MiscReg wh_Mask = 0x7FFF0FFF;
299 // Now, create Write Mask for the IntCtl register
300 MiscReg wh_Mask = 0x7FFF0FFF;
301 replaceBits(wh_Mask,0,32,0);
302 setRegMask(WatchHi0,wh_Mask);
301 replaceBits(wh_Mask, 0, 32, 0);
302 setRegMask(WatchHi0, wh_Mask);
303
304 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
303
304 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
305 MiscReg PCtr = readMiscRegNoEffect(PerfCnt0);
306 replaceBits(PCtr, PerfCntCtl_M, cp.CP0_PerfCtr_M);
307 replaceBits(PCtr, PerfCntCtl_W, cp.CP0_PerfCtr_W);
308 setMiscRegNoEffect(PerfCnt0, PCtr);
305 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(PerfCnt0);
306 perfCntCtl.m = cp.CP0_PerfCtr_M;
307 perfCntCtl.w = cp.CP0_PerfCtr_W;
308 setMiscRegNoEffect(PerfCnt0, perfCntCtl);
309 // Now, create Write Mask for the IntCtl register
310 MiscReg pc_Mask = 0x00007FF;
309 // Now, create Write Mask for the IntCtl register
310 MiscReg pc_Mask = 0x00007FF;
311 replaceBits(pc_Mask,0,32,0);
312 setRegMask(PerfCnt0,pc_Mask);
311 replaceBits(pc_Mask, 0, 32, 0);
312 setRegMask(PerfCnt0, pc_Mask);
313
314 // Random
313
314 // Random
315 MiscReg random = readMiscRegNoEffect(CP0_Random);
316 random = 63;
317 setMiscRegNoEffect(CP0_Random, random);
315 setMiscRegNoEffect(CP0_Random, 63);
318 // Now, create Write Mask for the IntCtl register
319 MiscReg random_Mask = 0;
316 // Now, create Write Mask for the IntCtl register
317 MiscReg random_Mask = 0;
320 replaceBits(random_Mask,0,32,0);
321 setRegMask(CP0_Random,random_Mask);
318 replaceBits(random_Mask, 0, 32, 0);
319 setRegMask(CP0_Random, random_Mask);
322
323 // PageGrain
320
321 // PageGrain
324 MiscReg pagegrain = readMiscRegNoEffect(PageGrain);
325 replaceBits(pagegrain,PageGrain_ESP,cp.CP0_Config3_SP);
326 setMiscRegNoEffect(PageGrain, pagegrain);
322 PageGrainReg pageGrain = readMiscRegNoEffect(PageGrain);
323 pageGrain.esp = cp.CP0_Config3_SP;
324 setMiscRegNoEffect(PageGrain, pageGrain);
327 // Now, create Write Mask for the IntCtl register
328 MiscReg pg_Mask = 0x10000000;
325 // Now, create Write Mask for the IntCtl register
326 MiscReg pg_Mask = 0x10000000;
329 replaceBits(pg_Mask,0,32,0);
330 setRegMask(PageGrain,pg_Mask);
327 replaceBits(pg_Mask, 0, 32, 0);
328 setRegMask(PageGrain, pg_Mask);
331
332 // Status
329
330 // Status
333 MiscReg stat = readMiscRegNoEffect(Status);
331 StatusReg status = readMiscRegNoEffect(Status);
334 // Only CU0 and IE are modified on a reset - everything else needs
335 // to be controlled on a per CPU model basis
336
337 // Enable CP0 on reset
332 // Only CU0 and IE are modified on a reset - everything else needs
333 // to be controlled on a per CPU model basis
334
335 // Enable CP0 on reset
338 // replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1);
336 // status.cu0 = 1;
339
340 // Enable ERL bit on a reset
337
338 // Enable ERL bit on a reset
341 replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1);
342
339 status.erl = 1;
343 // Enable BEV bit on a reset
340 // Enable BEV bit on a reset
344 replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1);
341 status.bev = 1;
345
342
346 setMiscRegNoEffect(Status, stat);
343 setMiscRegNoEffect(Status, status);
347 // Now, create Write Mask for the Status register
348 MiscReg stat_Mask = 0xFF78FF17;
344 // Now, create Write Mask for the Status register
345 MiscReg stat_Mask = 0xFF78FF17;
349 replaceBits(stat_Mask,0,32,0);
350 setRegMask(Status,stat_Mask);
346 replaceBits(stat_Mask, 0, 32, 0);
347 setRegMask(Status, stat_Mask);
351
352
353 // MVPConf0
348
349
350 // MVPConf0
354 MiscReg mvp_conf0 = readMiscRegNoEffect(MVPConf0);
355 replaceBits(mvp_conf0, MVPC0_TCA, 1);
356 replaceBits(mvp_conf0, MVPC0_PVPE_HI, MVPC0_PVPE_LO, num_vpes - 1);
357 replaceBits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO, num_threads - 1);
358 setMiscRegNoEffect(MVPConf0, mvp_conf0);
351 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0);
352 mvpConf0.tca = 1;
353 mvpConf0.pvpe = num_vpes - 1;
354 mvpConf0.ptc = num_threads - 1;
355 setMiscRegNoEffect(MVPConf0, mvpConf0);
359
360 // VPEConf0
356
357 // VPEConf0
361 MiscReg vpe_conf0 = readMiscRegNoEffect(VPEConf0);
362 replaceBits(vpe_conf0, VPEC0_MVP, 1);
363 setMiscRegNoEffect(VPEConf0, vpe_conf0);
358 VPEConf0Reg vpeConf0 = readMiscRegNoEffect(VPEConf0);
359 vpeConf0.mvp = 1;
360 setMiscRegNoEffect(VPEConf0, vpeConf0);
364
365 // TCBind
366 for (ThreadID tid = 0; tid < num_threads; tid++) {
361
362 // TCBind
363 for (ThreadID tid = 0; tid < num_threads; tid++) {
367 MiscReg tc_bind = readMiscRegNoEffect(TCBind, tid);
368 replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid);
369 setMiscRegNoEffect(TCBind, tc_bind, tid);
364 TCBindReg tcBind = readMiscRegNoEffect(TCBind, tid);
365 tcBind.curTC = tid;
366 setMiscRegNoEffect(TCBind, tcBind, tid);
370 }
371 // TCHalt
367 }
368 // TCHalt
372 MiscReg tc_halt = readMiscRegNoEffect(TCHalt);
373 replaceBits(tc_halt, TCH_H, 0);
374 setMiscRegNoEffect(TCHalt, tc_halt);
375 /*for (ThreadID tid = 1; tid < num_threads; tid++) {
376 // Set TCHalt Halt bit to 1 for all other threads
377 tc_halt = readMiscRegNoEffect(TCHalt, tid);
378 replaceBits(tc_halt, TCH_H, 1);
379 setReg(TCHalt, tc_halt, tid);
380 }*/
369 TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt);
370 tcHalt.h = 0;
371 setMiscRegNoEffect(TCHalt, tcHalt);
381
382 // TCStatus
383 // Set TCStatus Activated to 1 for the initial thread that is running
372
373 // TCStatus
374 // Set TCStatus Activated to 1 for the initial thread that is running
384 MiscReg tc_status = readMiscRegNoEffect(TCStatus);
385 replaceBits(tc_status, TCS_A, 1);
386 setMiscRegNoEffect(TCStatus, tc_status);
375 TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus);
376 tcStatus.a = 1;
377 setMiscRegNoEffect(TCStatus, tcStatus);
387
388 // Set Dynamically Allocatable bit to 1 for all other threads
389 for (ThreadID tid = 1; tid < num_threads; tid++) {
378
379 // Set Dynamically Allocatable bit to 1 for all other threads
380 for (ThreadID tid = 1; tid < num_threads; tid++) {
390 tc_status = readMiscRegNoEffect(TCStatus, tid);
391 replaceBits(tc_status, TCSTATUS_DA, 1);
392 setMiscRegNoEffect(TCStatus, tc_status, tid);
381 tcStatus = readMiscRegNoEffect(TCStatus, tid);
382 tcStatus.da = 1;
383 setMiscRegNoEffect(TCStatus, tcStatus, tid);
393 }
394
395
396 MiscReg Mask = 0x7FFFFFFF;
397
398 // Now, create Write Mask for the Index register
384 }
385
386
387 MiscReg Mask = 0x7FFFFFFF;
388
389 // Now, create Write Mask for the Index register
399 replaceBits(Mask,0,32,0);
400 setRegMask(Index,Mask);
390 replaceBits(Mask, 0, 32, 0);
391 setRegMask(Index, Mask);
401
402 Mask = 0x3FFFFFFF;
392
393 Mask = 0x3FFFFFFF;
403 replaceBits(Mask,0,32,0);
404 setRegMask(EntryLo0,Mask);
405 setRegMask(EntryLo1,Mask);
394 replaceBits(Mask, 0, 32, 0);
395 setRegMask(EntryLo0, Mask);
396 setRegMask(EntryLo1, Mask);
406
407 Mask = 0xFF800000;
397
398 Mask = 0xFF800000;
408 replaceBits(Mask,0,32,0);
409 setRegMask(Context,Mask);
399 replaceBits(Mask, 0, 32, 0);
400 setRegMask(Context, Mask);
410
411 Mask = 0x1FFFF800;
401
402 Mask = 0x1FFFF800;
412 replaceBits(Mask,0,32,0);
413 setRegMask(PageMask,Mask);
403 replaceBits(Mask, 0, 32, 0);
404 setRegMask(PageMask, Mask);
414
415 Mask = 0x0;
405
406 Mask = 0x0;
416 replaceBits(Mask,0,32,0);
417 setRegMask(BadVAddr,Mask);
418 setRegMask(LLAddr,Mask);
407 replaceBits(Mask, 0, 32, 0);
408 setRegMask(BadVAddr, Mask);
409 setRegMask(LLAddr, Mask);
419
420 Mask = 0x08C00300;
410
411 Mask = 0x08C00300;
421 replaceBits(Mask,0,32,0);
422 setRegMask(Cause,Mask);
412 replaceBits(Mask, 0, 32, 0);
413 setRegMask(Cause, Mask);
423
424}
425
426inline unsigned
427ISA::getVPENum(ThreadID tid)
428{
414
415}
416
417inline unsigned
418ISA::getVPENum(ThreadID tid)
419{
429 unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
430 return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
420 TCBindReg tcBind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
421 return tcBind.curVPE;
431}
432
433MiscReg
434ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid)
435{
436 int misc_reg = reg_idx - Ctrl_Base_DepTag;
437 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
438 ? tid : getVPENum(tid);

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556void
557ISA::updateCPU()
558{
559 ///////////////////////////////////////////////////////////////////
560 //
561 // EVALUATE CP0 STATE FOR MIPS MT
562 //
563 ///////////////////////////////////////////////////////////////////
422}
423
424MiscReg
425ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid)
426{
427 int misc_reg = reg_idx - Ctrl_Base_DepTag;
428 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
429 ? tid : getVPENum(tid);

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547void
548ISA::updateCPU()
549{
550 ///////////////////////////////////////////////////////////////////
551 //
552 // EVALUATE CP0 STATE FOR MIPS MT
553 //
554 ///////////////////////////////////////////////////////////////////
564 unsigned mvp_conf0 = readMiscRegNoEffect(MVPConf0);
565 ThreadID num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
555 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0);
556 ThreadID num_threads = mvpConf0.ptc + 1;
566
567 for (ThreadID tid = 0; tid < num_threads; tid++) {
557
558 for (ThreadID tid = 0; tid < num_threads; tid++) {
568 MiscReg tc_status = readMiscRegNoEffect(TCStatus, tid);
569 MiscReg tc_halt = readMiscRegNoEffect(TCHalt, tid);
559 TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus, tid);
560 TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt, tid);
570
571 //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
561
562 //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
572 if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) {
563 if (tcHalt.h == 1 || tcStatus.a == 0) {
573 haltThread(cpu->getContext(tid));
564 haltThread(cpu->getContext(tid));
574 } else if (bits(tc_halt, TCH_H) == 0 && bits(tc_status, TCS_A) == 1) {
565 } else if (tcHalt.h == 0 && tcStatus.a == 1) {
575 restoreThread(cpu->getContext(tid));
576 }
577 }
578
566 restoreThread(cpu->getContext(tid));
567 }
568 }
569
579 num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
570 num_threads = mvpConf0.ptc + 1;
580
581 // Toggle update flag after we finished updating
582 cp0Updated = false;
583}
584
585ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
586 : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
587{ }

--- 34 unchanged lines hidden --- 		571
572 // Toggle update flag after we finished updating
573 cp0Updated = false;
574}
575
576ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
577 : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
578{ }

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