isa.cc (13582:989577bf6abc) isa.cc (13615:5cc9363f5ab7)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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180 PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
181 procId.coOp = cp.CP0_PRId_CompanyOptions;
182 procId.coId = cp.CP0_PRId_CompanyID;
183 procId.procId = cp.CP0_PRId_ProcessorID;
184 procId.rev = cp.CP0_PRId_Revision;
185 setMiscRegNoEffect(MISCREG_PRID, procId);
186
187 // Now, create Write Mask for ProcID register
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 171 unchanged lines hidden (view full) ---

180 PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
181 procId.coOp = cp.CP0_PRId_CompanyOptions;
182 procId.coId = cp.CP0_PRId_CompanyID;
183 procId.procId = cp.CP0_PRId_ProcessorID;
184 procId.rev = cp.CP0_PRId_Revision;
185 setMiscRegNoEffect(MISCREG_PRID, procId);
186
187 // Now, create Write Mask for ProcID register
188 MiscReg procIDMask = 0; // Read-Only register
188 RegVal procIDMask = 0; // Read-Only register
189 replaceBits(procIDMask, 0, 32, 0);
190 setRegMask(MISCREG_PRID, procIDMask);
191
192 // Config
193 ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
194 cfg.be = cp.CP0_Config_BE;
195 cfg.at = cp.CP0_Config_AT;
196 cfg.ar = cp.CP0_Config_AR;
197 cfg.mt = cp.CP0_Config_MT;
198 cfg.vi = cp.CP0_Config_VI;
199 cfg.m = 1;
200 setMiscRegNoEffect(MISCREG_CONFIG, cfg);
201 // Now, create Write Mask for Config register
189 replaceBits(procIDMask, 0, 32, 0);
190 setRegMask(MISCREG_PRID, procIDMask);
191
192 // Config
193 ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
194 cfg.be = cp.CP0_Config_BE;
195 cfg.at = cp.CP0_Config_AT;
196 cfg.ar = cp.CP0_Config_AR;
197 cfg.mt = cp.CP0_Config_MT;
198 cfg.vi = cp.CP0_Config_VI;
199 cfg.m = 1;
200 setMiscRegNoEffect(MISCREG_CONFIG, cfg);
201 // Now, create Write Mask for Config register
202 MiscReg cfg_Mask = 0x7FFF0007;
202 RegVal cfg_Mask = 0x7FFF0007;
203 replaceBits(cfg_Mask, 0, 32, 0);
204 setRegMask(MISCREG_CONFIG, cfg_Mask);
205
206 // Config1
207 Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
208 cfg1.mmuSize = cp.CP0_Config1_MMU;
209 cfg1.is = cp.CP0_Config1_IS;
210 cfg1.il = cp.CP0_Config1_IL;

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216 cfg1.ep = cp.CP0_Config1_EP;
217 cfg1.wr = cp.CP0_Config1_WR;
218 cfg1.md = cp.CP0_Config1_MD;
219 cfg1.c2 = cp.CP0_Config1_C2;
220 cfg1.pc = cp.CP0_Config1_PC;
221 cfg1.m = cp.CP0_Config1_M;
222 setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
223 // Now, create Write Mask for Config register
203 replaceBits(cfg_Mask, 0, 32, 0);
204 setRegMask(MISCREG_CONFIG, cfg_Mask);
205
206 // Config1
207 Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
208 cfg1.mmuSize = cp.CP0_Config1_MMU;
209 cfg1.is = cp.CP0_Config1_IS;
210 cfg1.il = cp.CP0_Config1_IL;

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216 cfg1.ep = cp.CP0_Config1_EP;
217 cfg1.wr = cp.CP0_Config1_WR;
218 cfg1.md = cp.CP0_Config1_MD;
219 cfg1.c2 = cp.CP0_Config1_C2;
220 cfg1.pc = cp.CP0_Config1_PC;
221 cfg1.m = cp.CP0_Config1_M;
222 setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
223 // Now, create Write Mask for Config register
224 MiscReg cfg1_Mask = 0; // Read Only Register
224 RegVal cfg1_Mask = 0; // Read Only Register
225 replaceBits(cfg1_Mask, 0, 32, 0);
226 setRegMask(MISCREG_CONFIG1, cfg1_Mask);
227
228 // Config2
229 Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
230 cfg2.tu = cp.CP0_Config2_TU;
231 cfg2.ts = cp.CP0_Config2_TS;
232 cfg2.tl = cp.CP0_Config2_TL;
233 cfg2.ta = cp.CP0_Config2_TA;
234 cfg2.su = cp.CP0_Config2_SU;
235 cfg2.ss = cp.CP0_Config2_SS;
236 cfg2.sl = cp.CP0_Config2_SL;
237 cfg2.sa = cp.CP0_Config2_SA;
238 cfg2.m = cp.CP0_Config2_M;
239 setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
240 // Now, create Write Mask for Config register
225 replaceBits(cfg1_Mask, 0, 32, 0);
226 setRegMask(MISCREG_CONFIG1, cfg1_Mask);
227
228 // Config2
229 Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
230 cfg2.tu = cp.CP0_Config2_TU;
231 cfg2.ts = cp.CP0_Config2_TS;
232 cfg2.tl = cp.CP0_Config2_TL;
233 cfg2.ta = cp.CP0_Config2_TA;
234 cfg2.su = cp.CP0_Config2_SU;
235 cfg2.ss = cp.CP0_Config2_SS;
236 cfg2.sl = cp.CP0_Config2_SL;
237 cfg2.sa = cp.CP0_Config2_SA;
238 cfg2.m = cp.CP0_Config2_M;
239 setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
240 // Now, create Write Mask for Config register
241 MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
241 RegVal cfg2_Mask = 0x7000F000; // Read Only Register
242 replaceBits(cfg2_Mask, 0, 32, 0);
243 setRegMask(MISCREG_CONFIG2, cfg2_Mask);
244
245 // Config3
246 Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
247 cfg3.dspp = cp.CP0_Config3_DSPP;
248 cfg3.lpa = cp.CP0_Config3_LPA;
249 cfg3.veic = cp.CP0_Config3_VEIC;
250 cfg3.vint = cp.CP0_Config3_VInt;
251 cfg3.sp = cp.CP0_Config3_SP;
252 cfg3.mt = cp.CP0_Config3_MT;
253 cfg3.sm = cp.CP0_Config3_SM;
254 cfg3.tl = cp.CP0_Config3_TL;
255 setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
256 // Now, create Write Mask for Config register
242 replaceBits(cfg2_Mask, 0, 32, 0);
243 setRegMask(MISCREG_CONFIG2, cfg2_Mask);
244
245 // Config3
246 Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
247 cfg3.dspp = cp.CP0_Config3_DSPP;
248 cfg3.lpa = cp.CP0_Config3_LPA;
249 cfg3.veic = cp.CP0_Config3_VEIC;
250 cfg3.vint = cp.CP0_Config3_VInt;
251 cfg3.sp = cp.CP0_Config3_SP;
252 cfg3.mt = cp.CP0_Config3_MT;
253 cfg3.sm = cp.CP0_Config3_SM;
254 cfg3.tl = cp.CP0_Config3_TL;
255 setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
256 // Now, create Write Mask for Config register
257 MiscReg cfg3_Mask = 0; // Read Only Register
257 RegVal cfg3_Mask = 0; // Read Only Register
258 replaceBits(cfg3_Mask, 0, 32, 0);
259 setRegMask(MISCREG_CONFIG3, cfg3_Mask);
260
261 // EBase - CPUNum
262 EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
263 eBase.cpuNum = cp.CP0_EBase_CPUNum;
264 replaceBits(eBase, 31, 31, 1);
265 setMiscRegNoEffect(MISCREG_EBASE, eBase);
266 // Now, create Write Mask for Config register
258 replaceBits(cfg3_Mask, 0, 32, 0);
259 setRegMask(MISCREG_CONFIG3, cfg3_Mask);
260
261 // EBase - CPUNum
262 EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
263 eBase.cpuNum = cp.CP0_EBase_CPUNum;
264 replaceBits(eBase, 31, 31, 1);
265 setMiscRegNoEffect(MISCREG_EBASE, eBase);
266 // Now, create Write Mask for Config register
267 MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
267 RegVal EB_Mask = 0x3FFFF000;// Except Exception Base, the
268 // entire register is read only
269 replaceBits(EB_Mask, 0, 32, 0);
270 setRegMask(MISCREG_EBASE, EB_Mask);
271
272 // SRS Control - HSS (Highest Shadow Set)
273 SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
274 scsCtl.hss = cp.CP0_SrsCtl_HSS;
275 setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
276 // Now, create Write Mask for the SRS Ctl register
268 // entire register is read only
269 replaceBits(EB_Mask, 0, 32, 0);
270 setRegMask(MISCREG_EBASE, EB_Mask);
271
272 // SRS Control - HSS (Highest Shadow Set)
273 SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
274 scsCtl.hss = cp.CP0_SrsCtl_HSS;
275 setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
276 // Now, create Write Mask for the SRS Ctl register
277 MiscReg SC_Mask = 0x0000F3C0;
277 RegVal SC_Mask = 0x0000F3C0;
278 replaceBits(SC_Mask, 0, 32, 0);
279 setRegMask(MISCREG_SRSCTL, SC_Mask);
280
281 // IntCtl - IPTI, IPPCI
282 IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
283 intCtl.ipti = cp.CP0_IntCtl_IPTI;
284 intCtl.ippci = cp.CP0_IntCtl_IPPCI;
285 setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
286 // Now, create Write Mask for the IntCtl register
278 replaceBits(SC_Mask, 0, 32, 0);
279 setRegMask(MISCREG_SRSCTL, SC_Mask);
280
281 // IntCtl - IPTI, IPPCI
282 IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
283 intCtl.ipti = cp.CP0_IntCtl_IPTI;
284 intCtl.ippci = cp.CP0_IntCtl_IPPCI;
285 setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
286 // Now, create Write Mask for the IntCtl register
287 MiscReg IC_Mask = 0x000003E0;
287 RegVal IC_Mask = 0x000003E0;
288 replaceBits(IC_Mask, 0, 32, 0);
289 setRegMask(MISCREG_INTCTL, IC_Mask);
290
291 // Watch Hi - M - FIXME (More than 1 Watch register)
292 WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
293 watchHi.m = cp.CP0_WatchHi_M;
294 setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
295 // Now, create Write Mask for the IntCtl register
288 replaceBits(IC_Mask, 0, 32, 0);
289 setRegMask(MISCREG_INTCTL, IC_Mask);
290
291 // Watch Hi - M - FIXME (More than 1 Watch register)
292 WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
293 watchHi.m = cp.CP0_WatchHi_M;
294 setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
295 // Now, create Write Mask for the IntCtl register
296 MiscReg wh_Mask = 0x7FFF0FFF;
296 RegVal wh_Mask = 0x7FFF0FFF;
297 replaceBits(wh_Mask, 0, 32, 0);
298 setRegMask(MISCREG_WATCHHI0, wh_Mask);
299
300 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
301 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
302 perfCntCtl.m = cp.CP0_PerfCtr_M;
303 perfCntCtl.w = cp.CP0_PerfCtr_W;
304 setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
305 // Now, create Write Mask for the IntCtl register
297 replaceBits(wh_Mask, 0, 32, 0);
298 setRegMask(MISCREG_WATCHHI0, wh_Mask);
299
300 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
301 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
302 perfCntCtl.m = cp.CP0_PerfCtr_M;
303 perfCntCtl.w = cp.CP0_PerfCtr_W;
304 setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
305 // Now, create Write Mask for the IntCtl register
306 MiscReg pc_Mask = 0x00007FF;
306 RegVal pc_Mask = 0x00007FF;
307 replaceBits(pc_Mask, 0, 32, 0);
308 setRegMask(MISCREG_PERFCNT0, pc_Mask);
309
310 // Random
311 setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
312 // Now, create Write Mask for the IntCtl register
307 replaceBits(pc_Mask, 0, 32, 0);
308 setRegMask(MISCREG_PERFCNT0, pc_Mask);
309
310 // Random
311 setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
312 // Now, create Write Mask for the IntCtl register
313 MiscReg random_Mask = 0;
313 RegVal random_Mask = 0;
314 replaceBits(random_Mask, 0, 32, 0);
315 setRegMask(MISCREG_CP0_RANDOM, random_Mask);
316
317 // PageGrain
318 PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
319 pageGrain.esp = cp.CP0_Config3_SP;
320 setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
321 // Now, create Write Mask for the IntCtl register
314 replaceBits(random_Mask, 0, 32, 0);
315 setRegMask(MISCREG_CP0_RANDOM, random_Mask);
316
317 // PageGrain
318 PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
319 pageGrain.esp = cp.CP0_Config3_SP;
320 setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
321 // Now, create Write Mask for the IntCtl register
322 MiscReg pg_Mask = 0x10000000;
322 RegVal pg_Mask = 0x10000000;
323 replaceBits(pg_Mask, 0, 32, 0);
324 setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
325
326 // Status
327 StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
328 // Only CU0 and IE are modified on a reset - everything else needs
329 // to be controlled on a per CPU model basis
330
331 // Enable CP0 on reset
332 // status.cu0 = 1;
333
334 // Enable ERL bit on a reset
335 status.erl = 1;
336 // Enable BEV bit on a reset
337 status.bev = 1;
338
339 setMiscRegNoEffect(MISCREG_STATUS, status);
340 // Now, create Write Mask for the Status register
323 replaceBits(pg_Mask, 0, 32, 0);
324 setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
325
326 // Status
327 StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
328 // Only CU0 and IE are modified on a reset - everything else needs
329 // to be controlled on a per CPU model basis
330
331 // Enable CP0 on reset
332 // status.cu0 = 1;
333
334 // Enable ERL bit on a reset
335 status.erl = 1;
336 // Enable BEV bit on a reset
337 status.bev = 1;
338
339 setMiscRegNoEffect(MISCREG_STATUS, status);
340 // Now, create Write Mask for the Status register
341 MiscReg stat_Mask = 0xFF78FF17;
341 RegVal stat_Mask = 0xFF78FF17;
342 replaceBits(stat_Mask, 0, 32, 0);
343 setRegMask(MISCREG_STATUS, stat_Mask);
344
345
346 // MVPConf0
347 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
348 mvpConf0.tca = 1;
349 mvpConf0.pvpe = numVpes - 1;

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375 // Set Dynamically Allocatable bit to 1 for all other threads
376 for (ThreadID tid = 1; tid < numThreads; tid++) {
377 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
378 tcStatus.da = 1;
379 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
380 }
381
382
342 replaceBits(stat_Mask, 0, 32, 0);
343 setRegMask(MISCREG_STATUS, stat_Mask);
344
345
346 // MVPConf0
347 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
348 mvpConf0.tca = 1;
349 mvpConf0.pvpe = numVpes - 1;

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375 // Set Dynamically Allocatable bit to 1 for all other threads
376 for (ThreadID tid = 1; tid < numThreads; tid++) {
377 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
378 tcStatus.da = 1;
379 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
380 }
381
382
383 MiscReg mask = 0x7FFFFFFF;
383 RegVal mask = 0x7FFFFFFF;
384
385 // Now, create Write Mask for the Index register
386 replaceBits(mask, 0, 32, 0);
387 setRegMask(MISCREG_INDEX, mask);
388
389 mask = 0x3FFFFFFF;
390 replaceBits(mask, 0, 32, 0);
391 setRegMask(MISCREG_ENTRYLO0, mask);

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412
413inline unsigned
414ISA::getVPENum(ThreadID tid) const
415{
416 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
417 return tcBind.curVPE;
418}
419
384
385 // Now, create Write Mask for the Index register
386 replaceBits(mask, 0, 32, 0);
387 setRegMask(MISCREG_INDEX, mask);
388
389 mask = 0x3FFFFFFF;
390 replaceBits(mask, 0, 32, 0);
391 setRegMask(MISCREG_ENTRYLO0, mask);

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412
413inline unsigned
414ISA::getVPENum(ThreadID tid) const
415{
416 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
417 return tcBind.curVPE;
418}
419
420MiscReg
420RegVal
421ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
422{
423 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
424 ? tid : getVPENum(tid);
425 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
426 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
427 miscRegFile[misc_reg][reg_sel]);
428 return miscRegFile[misc_reg][reg_sel];
429}
430
431//@TODO: MIPS MT's register view automatically connects
432// Status to TCStatus depending on current thread
433//template <class TC>
421ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
422{
423 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
424 ? tid : getVPENum(tid);
425 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
426 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
427 miscRegFile[misc_reg][reg_sel]);
428 return miscRegFile[misc_reg][reg_sel];
429}
430
431//@TODO: MIPS MT's register view automatically connects
432// Status to TCStatus depending on current thread
433//template <class TC>
434MiscReg
434RegVal
435ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
436{
437 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
438 ? tid : getVPENum(tid);
439 DPRINTF(MipsPRA,
440 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
441 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
442 miscRegFile[misc_reg][reg_sel]);
443
444 return miscRegFile[misc_reg][reg_sel];
445}
446
447void
435ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
436{
437 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
438 ? tid : getVPENum(tid);
439 DPRINTF(MipsPRA,
440 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
441 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
442 miscRegFile[misc_reg][reg_sel]);
443
444 return miscRegFile[misc_reg][reg_sel];
445}
446
447void
448ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
448ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
449{
450 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
451 ? tid : getVPENum(tid);
452 DPRINTF(MipsPRA,
453 "[tid:%i]: Setting (direct set) CP0 Register:%u "
454 "Select:%u (%s) to %#x.\n",
455 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
456
457 miscRegFile[misc_reg][reg_sel] = val;
458}
459
460void
449{
450 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
451 ? tid : getVPENum(tid);
452 DPRINTF(MipsPRA,
453 "[tid:%i]: Setting (direct set) CP0 Register:%u "
454 "Select:%u (%s) to %#x.\n",
455 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
456
457 miscRegFile[misc_reg][reg_sel] = val;
458}
459
460void
461ISA::setRegMask(int misc_reg, MiscReg val, ThreadID tid)
461ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid)
462{
463 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
464 ? tid : getVPENum(tid);
465 DPRINTF(MipsPRA,
466 "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
467 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
468 miscRegFile_WriteMask[misc_reg][reg_sel] = val;
469}
470
471// PROGRAMMER'S NOTES:
472// (1) Some CP0 Registers have fields that cannot
473// be overwritten. Make sure to handle those particular registers
474// with care!
475void
462{
463 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
464 ? tid : getVPENum(tid);
465 DPRINTF(MipsPRA,
466 "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
467 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
468 miscRegFile_WriteMask[misc_reg][reg_sel] = val;
469}
470
471// PROGRAMMER'S NOTES:
472// (1) Some CP0 Registers have fields that cannot
473// be overwritten. Make sure to handle those particular registers
474// with care!
475void
476ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
476ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
477{
478 int reg_sel = (bankType[misc_reg] == perThreadContext)
479 ? tid : getVPENum(tid);
480
481 DPRINTF(MipsPRA,
482 "[tid:%i]: Setting CP0 Register:%u "
483 "Select:%u (%s) to %#x, with effect.\n",
484 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
485
477{
478 int reg_sel = (bankType[misc_reg] == perThreadContext)
479 ? tid : getVPENum(tid);
480
481 DPRINTF(MipsPRA,
482 "[tid:%i]: Setting CP0 Register:%u "
483 "Select:%u (%s) to %#x, with effect.\n",
484 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
485
486 MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
486 RegVal cp0_val = filterCP0Write(misc_reg, reg_sel, val);
487
488 miscRegFile[misc_reg][reg_sel] = cp0_val;
489
490 scheduleCP0Update(tc->getCpuPtr(), Cycles(1));
491}
492
493/**
494 * This method doesn't need to adjust the Control Register Offset
495 * since it has already been done in the calling method
496 * (setRegWithEffect)
497*/
487
488 miscRegFile[misc_reg][reg_sel] = cp0_val;
489
490 scheduleCP0Update(tc->getCpuPtr(), Cycles(1));
491}
492
493/**
494 * This method doesn't need to adjust the Control Register Offset
495 * since it has already been done in the calling method
496 * (setRegWithEffect)
497*/
498MiscReg
499ISA::filterCP0Write(int misc_reg, int reg_sel, MiscReg val)
498RegVal
499ISA::filterCP0Write(int misc_reg, int reg_sel, RegVal val)
500{
500{
501 MiscReg retVal = val;
501 RegVal retVal = val;
502
503 // Mask off read-only regions
504 retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
502
503 // Mask off read-only regions
504 retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
505 MiscReg curVal = miscRegFile[misc_reg][reg_sel];
505 RegVal curVal = miscRegFile[misc_reg][reg_sel];
506 // Mask off current alue with inverse mask (clear writeable bits)
507 curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
508 retVal |= curVal; // Combine the two
509 DPRINTF(MipsPRA,
510 "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
511 "current val: %lx, written val: %x\n",
512 miscRegFile_WriteMask[misc_reg][reg_sel],
513 ~miscRegFile_WriteMask[misc_reg][reg_sel],

--- 65 unchanged lines hidden --- 		506 // Mask off current alue with inverse mask (clear writeable bits)
507 curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
508 retVal |= curVal; // Combine the two
509 DPRINTF(MipsPRA,
510 "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
511 "current val: %lx, written val: %x\n",
512 miscRegFile_WriteMask[misc_reg][reg_sel],
513 ~miscRegFile_WriteMask[misc_reg][reg_sel],

--- 65 unchanged lines hidden ---