isa.cc (10033:21c14a2b2117) isa.cc (10698:829adc48e175)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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405
406 mask = 0x08C00300;
407 replaceBits(mask, 0, 32, 0);
408 setRegMask(MISCREG_CAUSE, mask);
409
410}
411
412inline unsigned
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 396 unchanged lines hidden (view full) ---

405
406 mask = 0x08C00300;
407 replaceBits(mask, 0, 32, 0);
408 setRegMask(MISCREG_CAUSE, mask);
409
410}
411
412inline unsigned
413ISA::getVPENum(ThreadID tid)
413ISA::getVPENum(ThreadID tid) const
414{
415 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
416 return tcBind.curVPE;
417}
418
419MiscReg
414{
415 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
416 return tcBind.curVPE;
417}
418
419MiscReg
420ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
420ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
421{
422 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
423 ? tid : getVPENum(tid);
424 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
425 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
426 miscRegFile[misc_reg][reg_sel]);
427 return miscRegFile[misc_reg][reg_sel];
428}

--- 171 unchanged lines hidden --- 		421{
422 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
423 ? tid : getVPENum(tid);
424 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
425 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
426 miscRegFile[misc_reg][reg_sel]);
427 return miscRegFile[misc_reg][reg_sel];
428}

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