1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 436 unchanged lines hidden (view full) --- 445} 446 447void 448ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) 449{ 450 unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 451 ? tid : getVPENum(tid); 452 DPRINTF(MipsPRA, |
453 "[tid:%i] Setting (direct set) CP0 Register:%u " |
454 "Select:%u (%s) to %#x.\n", 455 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 456 457 miscRegFile[misc_reg][reg_sel] = val; 458} 459 460void 461ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid) 462{ 463 unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 464 ? tid : getVPENum(tid); 465 DPRINTF(MipsPRA, |
466 "[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n", |
467 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 468 miscRegFile_WriteMask[misc_reg][reg_sel] = val; 469} 470 471// PROGRAMMER'S NOTES: 472// (1) Some CP0 Registers have fields that cannot 473// be overwritten. Make sure to handle those particular registers 474// with care! 475void 476ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) 477{ 478 int reg_sel = (bankType[misc_reg] == perThreadContext) 479 ? tid : getVPENum(tid); 480 481 DPRINTF(MipsPRA, |
482 "[tid:%i] Setting CP0 Register:%u " |
483 "Select:%u (%s) to %#x, with effect.\n", 484 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 485 486 RegVal cp0_val = filterCP0Write(misc_reg, reg_sel, val); 487 488 miscRegFile[misc_reg][reg_sel] = cp0_val; 489 490 scheduleCP0Update(tc->getCpuPtr(), Cycles(1)); --- 88 unchanged lines hidden --- |