38
39namespace MipsISA
40{
41
42std::string
43ISA::miscRegNames[NumMiscRegs] =
44{
45 "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
46 "Random", "VPEControl", "VPEConf0", "VPEConf1",
47 "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
48 "EntryLo0", "TCStatus", "TCBind", "TCRestart",
49 "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
50 "EntryLo1", "", "", "", "", "", "", "",
51 "Context", "ContextConfig", "", "", "", "", "", "",
52 "PageMask", "PageGrain", "", "", "", "", "", "",
53 "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
54 "SRSConf3", "SRSConf4", "", "",
55 "HWREna", "", "", "", "", "", "", "",
56 "BadVAddr", "", "", "", "", "", "", "",
57 "Count", "", "", "", "", "", "", "",
58 "EntryHi", "", "", "", "", "", "", "",
59 "Compare", "", "", "", "", "", "", "",
60 "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
61 "Cause", "", "", "", "", "", "", "",
62 "EPC", "", "", "", "", "", "", "",
63 "PRId", "EBase", "", "", "", "", "", "",
64 "Config", "Config1", "Config2", "Config3", "", "", "", "",
65 "LLAddr", "", "", "", "", "", "", "",
66 "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
67 "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
68 "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
69 "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
70 "XCContext64", "", "", "", "", "", "", "",
71 "", "", "", "", "", "", "", "",
72 "", "", "", "", "", "", "", "",
73 "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
74 "TraceBPC", "", "", "",
75 "DEPC", "", "", "", "", "", "", "",
76 "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
77 "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
78 "ErrCtl", "", "", "", "", "", "", "",
79 "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
80 "TagLo0", "DataLo1", "TagLo2", "DataLo3",
81 "TagLo4", "DataLo5", "TagLo6", "DataLo7",
82 "TagHi0", "DataHi1", "TagHi2", "DataHi3",
83 "TagHi4", "DataHi5", "TagHi6", "DataHi7",
84 "ErrorEPC", "", "", "", "", "", "", "",
85 "DESAVE", "", "", "", "", "", "", "",
86 "LLFlag"
87};
88
89ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
90{
91 numThreads = num_threads;
92 numVpes = num_vpes;
93
94 miscRegFile.resize(NumMiscRegs);
95 bankType.resize(NumMiscRegs);
96
97 for (int i=0; i < NumMiscRegs; i++) {
98 miscRegFile[i].resize(1);
99 bankType[i] = perProcessor;
100 }
101
102 miscRegFile_WriteMask.resize(NumMiscRegs);
103
104 for (int i = 0; i < NumMiscRegs; i++) {
105 miscRegFile_WriteMask[i].push_back(0);
106 }
107
108 // Initialize all Per-VPE regs
109 uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
110 MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
111 MISCREG_YQMASK,
112 MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
113 MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
114 MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
115 MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
116 MISCREG_EBASE
117 };
118 uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
119 for (int i = 0; i < num_vpe_regs; i++) {
120 if (numVpes > 1) {
121 miscRegFile[per_vpe_regs[i]].resize(numVpes);
122 }
123 bankType[per_vpe_regs[i]] = perVirtProcessor;
124 }
125
126 // Initialize all Per-TC regs
127 uint32_t per_tc_regs[] = { MISCREG_STATUS,
128 MISCREG_TC_STATUS, MISCREG_TC_BIND,
129 MISCREG_TC_RESTART, MISCREG_TC_HALT,
130 MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
131 MISCREG_TC_SCHEFBACK,
132 MISCREG_DEBUG, MISCREG_LLADDR
133 };
134 uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
135
136 for (int i = 0; i < num_tc_regs; i++) {
137 miscRegFile[per_tc_regs[i]].resize(numThreads);
138 bankType[per_tc_regs[i]] = perThreadContext;
139 }
140
141 clear();
142}
143
144void
145ISA::clear()
146{
147 for(int i = 0; i < NumMiscRegs; i++) {
148 for (int j = 0; j < miscRegFile[i].size(); j++)
149 miscRegFile[i][j] = 0;
150
151 for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
152 miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
153 }
154}
155
156
157void
158ISA::configCP()
159{
160 DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
161 numThreads, numVpes);
162
163 CoreSpecific cp;
164 panic("CP state must be set before the following code is used");
165
166 // Do Default CP0 initialization HERE
167
168 // Do Initialization for MT cores here (eventually use
169 // core_name parameter to toggle this initialization)
170 // ===================================================
171 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
172
173 PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
174 procId.coOp = cp.CP0_PRId_CompanyOptions;
175 procId.coId = cp.CP0_PRId_CompanyID;
176 procId.procId = cp.CP0_PRId_ProcessorID;
177 procId.rev = cp.CP0_PRId_Revision;
178 setMiscRegNoEffect(MISCREG_PRID, procId);
179
180 // Now, create Write Mask for ProcID register
181 MiscReg procIDMask = 0; // Read-Only register
182 replaceBits(procIDMask, 0, 32, 0);
183 setRegMask(MISCREG_PRID, procIDMask);
184
185 // Config
186 ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
187 cfg.be = cp.CP0_Config_BE;
188 cfg.at = cp.CP0_Config_AT;
189 cfg.ar = cp.CP0_Config_AR;
190 cfg.mt = cp.CP0_Config_MT;
191 cfg.vi = cp.CP0_Config_VI;
192 cfg.m = 1;
193 setMiscRegNoEffect(MISCREG_CONFIG, cfg);
194 // Now, create Write Mask for Config register
195 MiscReg cfg_Mask = 0x7FFF0007;
196 replaceBits(cfg_Mask, 0, 32, 0);
197 setRegMask(MISCREG_CONFIG, cfg_Mask);
198
199 // Config1
200 Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
201 cfg1.mmuSize = cp.CP0_Config1_MMU;
202 cfg1.is = cp.CP0_Config1_IS;
203 cfg1.il = cp.CP0_Config1_IL;
204 cfg1.ia = cp.CP0_Config1_IA;
205 cfg1.ds = cp.CP0_Config1_DS;
206 cfg1.dl = cp.CP0_Config1_DL;
207 cfg1.da = cp.CP0_Config1_DA;
208 cfg1.fp = cp.CP0_Config1_FP;
209 cfg1.ep = cp.CP0_Config1_EP;
210 cfg1.wr = cp.CP0_Config1_WR;
211 cfg1.md = cp.CP0_Config1_MD;
212 cfg1.c2 = cp.CP0_Config1_C2;
213 cfg1.pc = cp.CP0_Config1_PC;
214 cfg1.m = cp.CP0_Config1_M;
215 setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
216 // Now, create Write Mask for Config register
217 MiscReg cfg1_Mask = 0; // Read Only Register
218 replaceBits(cfg1_Mask, 0, 32, 0);
219 setRegMask(MISCREG_CONFIG1, cfg1_Mask);
220
221 // Config2
222 Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
223 cfg2.tu = cp.CP0_Config2_TU;
224 cfg2.ts = cp.CP0_Config2_TS;
225 cfg2.tl = cp.CP0_Config2_TL;
226 cfg2.ta = cp.CP0_Config2_TA;
227 cfg2.su = cp.CP0_Config2_SU;
228 cfg2.ss = cp.CP0_Config2_SS;
229 cfg2.sl = cp.CP0_Config2_SL;
230 cfg2.sa = cp.CP0_Config2_SA;
231 cfg2.m = cp.CP0_Config2_M;
232 setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
233 // Now, create Write Mask for Config register
234 MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
235 replaceBits(cfg2_Mask, 0, 32, 0);
236 setRegMask(MISCREG_CONFIG2, cfg2_Mask);
237
238 // Config3
239 Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
240 cfg3.dspp = cp.CP0_Config3_DSPP;
241 cfg3.lpa = cp.CP0_Config3_LPA;
242 cfg3.veic = cp.CP0_Config3_VEIC;
243 cfg3.vint = cp.CP0_Config3_VInt;
244 cfg3.sp = cp.CP0_Config3_SP;
245 cfg3.mt = cp.CP0_Config3_MT;
246 cfg3.sm = cp.CP0_Config3_SM;
247 cfg3.tl = cp.CP0_Config3_TL;
248 setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
249 // Now, create Write Mask for Config register
250 MiscReg cfg3_Mask = 0; // Read Only Register
251 replaceBits(cfg3_Mask, 0, 32, 0);
252 setRegMask(MISCREG_CONFIG3, cfg3_Mask);
253
254 // EBase - CPUNum
255 EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
256 eBase.cpuNum = cp.CP0_EBase_CPUNum;
257 replaceBits(eBase, 31, 31, 1);
258 setMiscRegNoEffect(MISCREG_EBASE, eBase);
259 // Now, create Write Mask for Config register
260 MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
261 // entire register is read only
262 replaceBits(EB_Mask, 0, 32, 0);
263 setRegMask(MISCREG_EBASE, EB_Mask);
264
265 // SRS Control - HSS (Highest Shadow Set)
266 SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
267 scsCtl.hss = cp.CP0_SrsCtl_HSS;
268 setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
269 // Now, create Write Mask for the SRS Ctl register
270 MiscReg SC_Mask = 0x0000F3C0;
271 replaceBits(SC_Mask, 0, 32, 0);
272 setRegMask(MISCREG_SRSCTL, SC_Mask);
273
274 // IntCtl - IPTI, IPPCI
275 IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
276 intCtl.ipti = cp.CP0_IntCtl_IPTI;
277 intCtl.ippci = cp.CP0_IntCtl_IPPCI;
278 setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
279 // Now, create Write Mask for the IntCtl register
280 MiscReg IC_Mask = 0x000003E0;
281 replaceBits(IC_Mask, 0, 32, 0);
282 setRegMask(MISCREG_INTCTL, IC_Mask);
283
284 // Watch Hi - M - FIXME (More than 1 Watch register)
285 WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
286 watchHi.m = cp.CP0_WatchHi_M;
287 setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
288 // Now, create Write Mask for the IntCtl register
289 MiscReg wh_Mask = 0x7FFF0FFF;
290 replaceBits(wh_Mask, 0, 32, 0);
291 setRegMask(MISCREG_WATCHHI0, wh_Mask);
292
293 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
294 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
295 perfCntCtl.m = cp.CP0_PerfCtr_M;
296 perfCntCtl.w = cp.CP0_PerfCtr_W;
297 setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
298 // Now, create Write Mask for the IntCtl register
299 MiscReg pc_Mask = 0x00007FF;
300 replaceBits(pc_Mask, 0, 32, 0);
301 setRegMask(MISCREG_PERFCNT0, pc_Mask);
302
303 // Random
304 setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
305 // Now, create Write Mask for the IntCtl register
306 MiscReg random_Mask = 0;
307 replaceBits(random_Mask, 0, 32, 0);
308 setRegMask(MISCREG_CP0_RANDOM, random_Mask);
309
310 // PageGrain
311 PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
312 pageGrain.esp = cp.CP0_Config3_SP;
313 setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
314 // Now, create Write Mask for the IntCtl register
315 MiscReg pg_Mask = 0x10000000;
316 replaceBits(pg_Mask, 0, 32, 0);
317 setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
318
319 // Status
320 StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
321 // Only CU0 and IE are modified on a reset - everything else needs
322 // to be controlled on a per CPU model basis
323
324 // Enable CP0 on reset
325 // status.cu0 = 1;
326
327 // Enable ERL bit on a reset
328 status.erl = 1;
329 // Enable BEV bit on a reset
330 status.bev = 1;
331
332 setMiscRegNoEffect(MISCREG_STATUS, status);
333 // Now, create Write Mask for the Status register
334 MiscReg stat_Mask = 0xFF78FF17;
335 replaceBits(stat_Mask, 0, 32, 0);
336 setRegMask(MISCREG_STATUS, stat_Mask);
337
338
339 // MVPConf0
340 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
341 mvpConf0.tca = 1;
342 mvpConf0.pvpe = numVpes - 1;
343 mvpConf0.ptc = numThreads - 1;
344 setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
345
346 // VPEConf0
347 VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
348 vpeConf0.mvp = 1;
349 setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
350
351 // TCBind
352 for (ThreadID tid = 0; tid < numThreads; tid++) {
353 TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
354 tcBind.curTC = tid;
355 setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
356 }
357 // TCHalt
358 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
359 tcHalt.h = 0;
360 setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
361
362 // TCStatus
363 // Set TCStatus Activated to 1 for the initial thread that is running
364 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
365 tcStatus.a = 1;
366 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
367
368 // Set Dynamically Allocatable bit to 1 for all other threads
369 for (ThreadID tid = 1; tid < numThreads; tid++) {
370 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
371 tcStatus.da = 1;
372 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
373 }
374
375
376 MiscReg mask = 0x7FFFFFFF;
377
378 // Now, create Write Mask for the Index register
379 replaceBits(mask, 0, 32, 0);
380 setRegMask(MISCREG_INDEX, mask);
381
382 mask = 0x3FFFFFFF;
383 replaceBits(mask, 0, 32, 0);
384 setRegMask(MISCREG_ENTRYLO0, mask);
385 setRegMask(MISCREG_ENTRYLO1, mask);
386
387 mask = 0xFF800000;
388 replaceBits(mask, 0, 32, 0);
389 setRegMask(MISCREG_CONTEXT, mask);
390
391 mask = 0x1FFFF800;
392 replaceBits(mask, 0, 32, 0);
393 setRegMask(MISCREG_PAGEMASK, mask);
394
395 mask = 0x0;
396 replaceBits(mask, 0, 32, 0);
397 setRegMask(MISCREG_BADVADDR, mask);
398 setRegMask(MISCREG_LLADDR, mask);
399
400 mask = 0x08C00300;
401 replaceBits(mask, 0, 32, 0);
402 setRegMask(MISCREG_CAUSE, mask);
403
404}
405
406inline unsigned
407ISA::getVPENum(ThreadID tid)
408{
409 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
410 return tcBind.curVPE;
411}
412
413MiscReg
414ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
415{
416 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
417 ? tid : getVPENum(tid);
418 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
419 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
420 miscRegFile[misc_reg][reg_sel]);
421 return miscRegFile[misc_reg][reg_sel];
422}
423
424//@TODO: MIPS MT's register view automatically connects
425// Status to TCStatus depending on current thread
426//template <class TC>
427MiscReg
428ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
429{
430 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
431 ? tid : getVPENum(tid);
432 DPRINTF(MipsPRA,
433 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
434 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
435 miscRegFile[misc_reg][reg_sel]);
436
437 return miscRegFile[misc_reg][reg_sel];
438}
439
440void
441ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
442{
443 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
444 ? tid : getVPENum(tid);
445 DPRINTF(MipsPRA,
446 "[tid:%i]: Setting (direct set) CP0 Register:%u "
447 "Select:%u (%s) to %#x.\n",
448 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
449
450 miscRegFile[misc_reg][reg_sel] = val;
451}
452
453void
454ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
455{
456 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
457 ? tid : getVPENum(tid);
458 DPRINTF(MipsPRA,
459 "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
460 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
461 miscRegFile_WriteMask[misc_reg][reg_sel] = val;
462}
463
464// PROGRAMMER'S NOTES:
465// (1) Some CP0 Registers have fields that cannot
466// be overwritten. Make sure to handle those particular registers
467// with care!
468void
469ISA::setMiscReg(int misc_reg, const MiscReg &val,
470 ThreadContext *tc, ThreadID tid)
471{
472 int reg_sel = (bankType[misc_reg] == perThreadContext)
473 ? tid : getVPENum(tid);
474
475 DPRINTF(MipsPRA,
476 "[tid:%i]: Setting CP0 Register:%u "
477 "Select:%u (%s) to %#x, with effect.\n",
478 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
479
480 MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
481
482 miscRegFile[misc_reg][reg_sel] = cp0_val;
483
484 scheduleCP0Update(tc->getCpuPtr(), 1);
485}
486
487/**
488 * This method doesn't need to adjust the Control Register Offset
489 * since it has already been done in the calling method
490 * (setRegWithEffect)
491*/
492MiscReg
493ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
494{
495 MiscReg retVal = val;
496
497 // Mask off read-only regions
498 retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
499 MiscReg curVal = miscRegFile[misc_reg][reg_sel];
500 // Mask off current alue with inverse mask (clear writeable bits)
501 curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
502 retVal |= curVal; // Combine the two
503 DPRINTF(MipsPRA,
504 "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
505 "current val: %lx, written val: %x\n",
506 miscRegFile_WriteMask[misc_reg][reg_sel],
507 ~miscRegFile_WriteMask[misc_reg][reg_sel],
508 val, miscRegFile[misc_reg][reg_sel], retVal);
509 return retVal;
510}
511
512void
513ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
514{
515 if (!cp0Updated) {
516 cp0Updated = true;
517
518 //schedule UPDATE
519 CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
520 cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
521 }
522}
523
524void
525ISA::updateCPU(BaseCPU *cpu)
526{
527 ///////////////////////////////////////////////////////////////////
528 //
529 // EVALUATE CP0 STATE FOR MIPS MT
530 //
531 ///////////////////////////////////////////////////////////////////
532 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
533 ThreadID num_threads = mvpConf0.ptc + 1;
534
535 for (ThreadID tid = 0; tid < num_threads; tid++) {
536 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
537 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
538
539 //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
540 if (tcHalt.h == 1 || tcStatus.a == 0) {
541 haltThread(cpu->getContext(tid));
542 } else if (tcHalt.h == 0 && tcStatus.a == 1) {
543 restoreThread(cpu->getContext(tid));
544 }
545 }
546
547 num_threads = mvpConf0.ptc + 1;
548
549 // Toggle update flag after we finished updating
550 cp0Updated = false;
551}
552
553ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
554 : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
555{ }
556
557void
558ISA::CP0Event::process()
559{
560 switch (cp0EventType)
561 {
562 case UpdateCP0:
563 cp0->updateCPU(cpu);
564 break;
565 }
566}
567
568const char *
569ISA::CP0Event::description() const
570{
571 return "Coprocessor-0 event";
572}
573
574void
575ISA::CP0Event::scheduleEvent(int delay)
576{
577 cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
578}
579
580void
581ISA::CP0Event::unscheduleEvent()
582{
583 if (scheduled())
584 squash();
585}
586
587}
| 39
40namespace MipsISA
41{
42
43std::string
44ISA::miscRegNames[NumMiscRegs] =
45{
46 "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
47 "Random", "VPEControl", "VPEConf0", "VPEConf1",
48 "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
49 "EntryLo0", "TCStatus", "TCBind", "TCRestart",
50 "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
51 "EntryLo1", "", "", "", "", "", "", "",
52 "Context", "ContextConfig", "", "", "", "", "", "",
53 "PageMask", "PageGrain", "", "", "", "", "", "",
54 "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
55 "SRSConf3", "SRSConf4", "", "",
56 "HWREna", "", "", "", "", "", "", "",
57 "BadVAddr", "", "", "", "", "", "", "",
58 "Count", "", "", "", "", "", "", "",
59 "EntryHi", "", "", "", "", "", "", "",
60 "Compare", "", "", "", "", "", "", "",
61 "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
62 "Cause", "", "", "", "", "", "", "",
63 "EPC", "", "", "", "", "", "", "",
64 "PRId", "EBase", "", "", "", "", "", "",
65 "Config", "Config1", "Config2", "Config3", "", "", "", "",
66 "LLAddr", "", "", "", "", "", "", "",
67 "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
68 "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
69 "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
70 "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
71 "XCContext64", "", "", "", "", "", "", "",
72 "", "", "", "", "", "", "", "",
73 "", "", "", "", "", "", "", "",
74 "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
75 "TraceBPC", "", "", "",
76 "DEPC", "", "", "", "", "", "", "",
77 "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
78 "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
79 "ErrCtl", "", "", "", "", "", "", "",
80 "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
81 "TagLo0", "DataLo1", "TagLo2", "DataLo3",
82 "TagLo4", "DataLo5", "TagLo6", "DataLo7",
83 "TagHi0", "DataHi1", "TagHi2", "DataHi3",
84 "TagHi4", "DataHi5", "TagHi6", "DataHi7",
85 "ErrorEPC", "", "", "", "", "", "", "",
86 "DESAVE", "", "", "", "", "", "", "",
87 "LLFlag"
88};
89
90ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
91{
92 numThreads = num_threads;
93 numVpes = num_vpes;
94
95 miscRegFile.resize(NumMiscRegs);
96 bankType.resize(NumMiscRegs);
97
98 for (int i=0; i < NumMiscRegs; i++) {
99 miscRegFile[i].resize(1);
100 bankType[i] = perProcessor;
101 }
102
103 miscRegFile_WriteMask.resize(NumMiscRegs);
104
105 for (int i = 0; i < NumMiscRegs; i++) {
106 miscRegFile_WriteMask[i].push_back(0);
107 }
108
109 // Initialize all Per-VPE regs
110 uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
111 MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
112 MISCREG_YQMASK,
113 MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
114 MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
115 MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
116 MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
117 MISCREG_EBASE
118 };
119 uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
120 for (int i = 0; i < num_vpe_regs; i++) {
121 if (numVpes > 1) {
122 miscRegFile[per_vpe_regs[i]].resize(numVpes);
123 }
124 bankType[per_vpe_regs[i]] = perVirtProcessor;
125 }
126
127 // Initialize all Per-TC regs
128 uint32_t per_tc_regs[] = { MISCREG_STATUS,
129 MISCREG_TC_STATUS, MISCREG_TC_BIND,
130 MISCREG_TC_RESTART, MISCREG_TC_HALT,
131 MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
132 MISCREG_TC_SCHEFBACK,
133 MISCREG_DEBUG, MISCREG_LLADDR
134 };
135 uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
136
137 for (int i = 0; i < num_tc_regs; i++) {
138 miscRegFile[per_tc_regs[i]].resize(numThreads);
139 bankType[per_tc_regs[i]] = perThreadContext;
140 }
141
142 clear();
143}
144
145void
146ISA::clear()
147{
148 for(int i = 0; i < NumMiscRegs; i++) {
149 for (int j = 0; j < miscRegFile[i].size(); j++)
150 miscRegFile[i][j] = 0;
151
152 for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
153 miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
154 }
155}
156
157
158void
159ISA::configCP()
160{
161 DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
162 numThreads, numVpes);
163
164 CoreSpecific cp;
165 panic("CP state must be set before the following code is used");
166
167 // Do Default CP0 initialization HERE
168
169 // Do Initialization for MT cores here (eventually use
170 // core_name parameter to toggle this initialization)
171 // ===================================================
172 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
173
174 PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
175 procId.coOp = cp.CP0_PRId_CompanyOptions;
176 procId.coId = cp.CP0_PRId_CompanyID;
177 procId.procId = cp.CP0_PRId_ProcessorID;
178 procId.rev = cp.CP0_PRId_Revision;
179 setMiscRegNoEffect(MISCREG_PRID, procId);
180
181 // Now, create Write Mask for ProcID register
182 MiscReg procIDMask = 0; // Read-Only register
183 replaceBits(procIDMask, 0, 32, 0);
184 setRegMask(MISCREG_PRID, procIDMask);
185
186 // Config
187 ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
188 cfg.be = cp.CP0_Config_BE;
189 cfg.at = cp.CP0_Config_AT;
190 cfg.ar = cp.CP0_Config_AR;
191 cfg.mt = cp.CP0_Config_MT;
192 cfg.vi = cp.CP0_Config_VI;
193 cfg.m = 1;
194 setMiscRegNoEffect(MISCREG_CONFIG, cfg);
195 // Now, create Write Mask for Config register
196 MiscReg cfg_Mask = 0x7FFF0007;
197 replaceBits(cfg_Mask, 0, 32, 0);
198 setRegMask(MISCREG_CONFIG, cfg_Mask);
199
200 // Config1
201 Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
202 cfg1.mmuSize = cp.CP0_Config1_MMU;
203 cfg1.is = cp.CP0_Config1_IS;
204 cfg1.il = cp.CP0_Config1_IL;
205 cfg1.ia = cp.CP0_Config1_IA;
206 cfg1.ds = cp.CP0_Config1_DS;
207 cfg1.dl = cp.CP0_Config1_DL;
208 cfg1.da = cp.CP0_Config1_DA;
209 cfg1.fp = cp.CP0_Config1_FP;
210 cfg1.ep = cp.CP0_Config1_EP;
211 cfg1.wr = cp.CP0_Config1_WR;
212 cfg1.md = cp.CP0_Config1_MD;
213 cfg1.c2 = cp.CP0_Config1_C2;
214 cfg1.pc = cp.CP0_Config1_PC;
215 cfg1.m = cp.CP0_Config1_M;
216 setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
217 // Now, create Write Mask for Config register
218 MiscReg cfg1_Mask = 0; // Read Only Register
219 replaceBits(cfg1_Mask, 0, 32, 0);
220 setRegMask(MISCREG_CONFIG1, cfg1_Mask);
221
222 // Config2
223 Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
224 cfg2.tu = cp.CP0_Config2_TU;
225 cfg2.ts = cp.CP0_Config2_TS;
226 cfg2.tl = cp.CP0_Config2_TL;
227 cfg2.ta = cp.CP0_Config2_TA;
228 cfg2.su = cp.CP0_Config2_SU;
229 cfg2.ss = cp.CP0_Config2_SS;
230 cfg2.sl = cp.CP0_Config2_SL;
231 cfg2.sa = cp.CP0_Config2_SA;
232 cfg2.m = cp.CP0_Config2_M;
233 setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
234 // Now, create Write Mask for Config register
235 MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
236 replaceBits(cfg2_Mask, 0, 32, 0);
237 setRegMask(MISCREG_CONFIG2, cfg2_Mask);
238
239 // Config3
240 Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
241 cfg3.dspp = cp.CP0_Config3_DSPP;
242 cfg3.lpa = cp.CP0_Config3_LPA;
243 cfg3.veic = cp.CP0_Config3_VEIC;
244 cfg3.vint = cp.CP0_Config3_VInt;
245 cfg3.sp = cp.CP0_Config3_SP;
246 cfg3.mt = cp.CP0_Config3_MT;
247 cfg3.sm = cp.CP0_Config3_SM;
248 cfg3.tl = cp.CP0_Config3_TL;
249 setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
250 // Now, create Write Mask for Config register
251 MiscReg cfg3_Mask = 0; // Read Only Register
252 replaceBits(cfg3_Mask, 0, 32, 0);
253 setRegMask(MISCREG_CONFIG3, cfg3_Mask);
254
255 // EBase - CPUNum
256 EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
257 eBase.cpuNum = cp.CP0_EBase_CPUNum;
258 replaceBits(eBase, 31, 31, 1);
259 setMiscRegNoEffect(MISCREG_EBASE, eBase);
260 // Now, create Write Mask for Config register
261 MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
262 // entire register is read only
263 replaceBits(EB_Mask, 0, 32, 0);
264 setRegMask(MISCREG_EBASE, EB_Mask);
265
266 // SRS Control - HSS (Highest Shadow Set)
267 SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
268 scsCtl.hss = cp.CP0_SrsCtl_HSS;
269 setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
270 // Now, create Write Mask for the SRS Ctl register
271 MiscReg SC_Mask = 0x0000F3C0;
272 replaceBits(SC_Mask, 0, 32, 0);
273 setRegMask(MISCREG_SRSCTL, SC_Mask);
274
275 // IntCtl - IPTI, IPPCI
276 IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
277 intCtl.ipti = cp.CP0_IntCtl_IPTI;
278 intCtl.ippci = cp.CP0_IntCtl_IPPCI;
279 setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
280 // Now, create Write Mask for the IntCtl register
281 MiscReg IC_Mask = 0x000003E0;
282 replaceBits(IC_Mask, 0, 32, 0);
283 setRegMask(MISCREG_INTCTL, IC_Mask);
284
285 // Watch Hi - M - FIXME (More than 1 Watch register)
286 WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
287 watchHi.m = cp.CP0_WatchHi_M;
288 setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
289 // Now, create Write Mask for the IntCtl register
290 MiscReg wh_Mask = 0x7FFF0FFF;
291 replaceBits(wh_Mask, 0, 32, 0);
292 setRegMask(MISCREG_WATCHHI0, wh_Mask);
293
294 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
295 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
296 perfCntCtl.m = cp.CP0_PerfCtr_M;
297 perfCntCtl.w = cp.CP0_PerfCtr_W;
298 setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
299 // Now, create Write Mask for the IntCtl register
300 MiscReg pc_Mask = 0x00007FF;
301 replaceBits(pc_Mask, 0, 32, 0);
302 setRegMask(MISCREG_PERFCNT0, pc_Mask);
303
304 // Random
305 setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
306 // Now, create Write Mask for the IntCtl register
307 MiscReg random_Mask = 0;
308 replaceBits(random_Mask, 0, 32, 0);
309 setRegMask(MISCREG_CP0_RANDOM, random_Mask);
310
311 // PageGrain
312 PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
313 pageGrain.esp = cp.CP0_Config3_SP;
314 setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
315 // Now, create Write Mask for the IntCtl register
316 MiscReg pg_Mask = 0x10000000;
317 replaceBits(pg_Mask, 0, 32, 0);
318 setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
319
320 // Status
321 StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
322 // Only CU0 and IE are modified on a reset - everything else needs
323 // to be controlled on a per CPU model basis
324
325 // Enable CP0 on reset
326 // status.cu0 = 1;
327
328 // Enable ERL bit on a reset
329 status.erl = 1;
330 // Enable BEV bit on a reset
331 status.bev = 1;
332
333 setMiscRegNoEffect(MISCREG_STATUS, status);
334 // Now, create Write Mask for the Status register
335 MiscReg stat_Mask = 0xFF78FF17;
336 replaceBits(stat_Mask, 0, 32, 0);
337 setRegMask(MISCREG_STATUS, stat_Mask);
338
339
340 // MVPConf0
341 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
342 mvpConf0.tca = 1;
343 mvpConf0.pvpe = numVpes - 1;
344 mvpConf0.ptc = numThreads - 1;
345 setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
346
347 // VPEConf0
348 VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
349 vpeConf0.mvp = 1;
350 setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
351
352 // TCBind
353 for (ThreadID tid = 0; tid < numThreads; tid++) {
354 TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
355 tcBind.curTC = tid;
356 setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
357 }
358 // TCHalt
359 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
360 tcHalt.h = 0;
361 setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
362
363 // TCStatus
364 // Set TCStatus Activated to 1 for the initial thread that is running
365 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
366 tcStatus.a = 1;
367 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
368
369 // Set Dynamically Allocatable bit to 1 for all other threads
370 for (ThreadID tid = 1; tid < numThreads; tid++) {
371 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
372 tcStatus.da = 1;
373 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
374 }
375
376
377 MiscReg mask = 0x7FFFFFFF;
378
379 // Now, create Write Mask for the Index register
380 replaceBits(mask, 0, 32, 0);
381 setRegMask(MISCREG_INDEX, mask);
382
383 mask = 0x3FFFFFFF;
384 replaceBits(mask, 0, 32, 0);
385 setRegMask(MISCREG_ENTRYLO0, mask);
386 setRegMask(MISCREG_ENTRYLO1, mask);
387
388 mask = 0xFF800000;
389 replaceBits(mask, 0, 32, 0);
390 setRegMask(MISCREG_CONTEXT, mask);
391
392 mask = 0x1FFFF800;
393 replaceBits(mask, 0, 32, 0);
394 setRegMask(MISCREG_PAGEMASK, mask);
395
396 mask = 0x0;
397 replaceBits(mask, 0, 32, 0);
398 setRegMask(MISCREG_BADVADDR, mask);
399 setRegMask(MISCREG_LLADDR, mask);
400
401 mask = 0x08C00300;
402 replaceBits(mask, 0, 32, 0);
403 setRegMask(MISCREG_CAUSE, mask);
404
405}
406
407inline unsigned
408ISA::getVPENum(ThreadID tid)
409{
410 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
411 return tcBind.curVPE;
412}
413
414MiscReg
415ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
416{
417 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
418 ? tid : getVPENum(tid);
419 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
420 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
421 miscRegFile[misc_reg][reg_sel]);
422 return miscRegFile[misc_reg][reg_sel];
423}
424
425//@TODO: MIPS MT's register view automatically connects
426// Status to TCStatus depending on current thread
427//template <class TC>
428MiscReg
429ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
430{
431 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
432 ? tid : getVPENum(tid);
433 DPRINTF(MipsPRA,
434 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
435 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
436 miscRegFile[misc_reg][reg_sel]);
437
438 return miscRegFile[misc_reg][reg_sel];
439}
440
441void
442ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
443{
444 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
445 ? tid : getVPENum(tid);
446 DPRINTF(MipsPRA,
447 "[tid:%i]: Setting (direct set) CP0 Register:%u "
448 "Select:%u (%s) to %#x.\n",
449 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
450
451 miscRegFile[misc_reg][reg_sel] = val;
452}
453
454void
455ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
456{
457 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
458 ? tid : getVPENum(tid);
459 DPRINTF(MipsPRA,
460 "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
461 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
462 miscRegFile_WriteMask[misc_reg][reg_sel] = val;
463}
464
465// PROGRAMMER'S NOTES:
466// (1) Some CP0 Registers have fields that cannot
467// be overwritten. Make sure to handle those particular registers
468// with care!
469void
470ISA::setMiscReg(int misc_reg, const MiscReg &val,
471 ThreadContext *tc, ThreadID tid)
472{
473 int reg_sel = (bankType[misc_reg] == perThreadContext)
474 ? tid : getVPENum(tid);
475
476 DPRINTF(MipsPRA,
477 "[tid:%i]: Setting CP0 Register:%u "
478 "Select:%u (%s) to %#x, with effect.\n",
479 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
480
481 MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
482
483 miscRegFile[misc_reg][reg_sel] = cp0_val;
484
485 scheduleCP0Update(tc->getCpuPtr(), 1);
486}
487
488/**
489 * This method doesn't need to adjust the Control Register Offset
490 * since it has already been done in the calling method
491 * (setRegWithEffect)
492*/
493MiscReg
494ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
495{
496 MiscReg retVal = val;
497
498 // Mask off read-only regions
499 retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
500 MiscReg curVal = miscRegFile[misc_reg][reg_sel];
501 // Mask off current alue with inverse mask (clear writeable bits)
502 curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
503 retVal |= curVal; // Combine the two
504 DPRINTF(MipsPRA,
505 "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
506 "current val: %lx, written val: %x\n",
507 miscRegFile_WriteMask[misc_reg][reg_sel],
508 ~miscRegFile_WriteMask[misc_reg][reg_sel],
509 val, miscRegFile[misc_reg][reg_sel], retVal);
510 return retVal;
511}
512
513void
514ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
515{
516 if (!cp0Updated) {
517 cp0Updated = true;
518
519 //schedule UPDATE
520 CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
521 cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
522 }
523}
524
525void
526ISA::updateCPU(BaseCPU *cpu)
527{
528 ///////////////////////////////////////////////////////////////////
529 //
530 // EVALUATE CP0 STATE FOR MIPS MT
531 //
532 ///////////////////////////////////////////////////////////////////
533 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
534 ThreadID num_threads = mvpConf0.ptc + 1;
535
536 for (ThreadID tid = 0; tid < num_threads; tid++) {
537 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
538 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
539
540 //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
541 if (tcHalt.h == 1 || tcStatus.a == 0) {
542 haltThread(cpu->getContext(tid));
543 } else if (tcHalt.h == 0 && tcStatus.a == 1) {
544 restoreThread(cpu->getContext(tid));
545 }
546 }
547
548 num_threads = mvpConf0.ptc + 1;
549
550 // Toggle update flag after we finished updating
551 cp0Updated = false;
552}
553
554ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
555 : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
556{ }
557
558void
559ISA::CP0Event::process()
560{
561 switch (cp0EventType)
562 {
563 case UpdateCP0:
564 cp0->updateCPU(cpu);
565 break;
566 }
567}
568
569const char *
570ISA::CP0Event::description() const
571{
572 return "Coprocessor-0 event";
573}
574
575void
576ISA::CP0Event::scheduleEvent(int delay)
577{
578 cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
579}
580
581void
582ISA::CP0Event::unscheduleEvent()
583{
584 if (scheduled())
585 squash();
586}
587
588}
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