1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/mips/isa.hh"
32
33#include "arch/mips/mt.hh"
34#include "arch/mips/mt_constants.hh"
35#include "arch/mips/pra_constants.hh"
36#include "base/bitfield.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"
40#include "params/MipsISA.hh"
41
42namespace MipsISA
43{
44
45std::string
46ISA::miscRegNames[NumMiscRegs] =
47{
48 "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
49 "Random", "VPEControl", "VPEConf0", "VPEConf1",
50 "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
51 "EntryLo0", "TCStatus", "TCBind", "TCRestart",
52 "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
53 "EntryLo1", "", "", "", "", "", "", "",
54 "Context", "ContextConfig", "", "", "", "", "", "",
55 "PageMask", "PageGrain", "", "", "", "", "", "",
56 "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
57 "SRSConf3", "SRSConf4", "", "",
58 "HWREna", "", "", "", "", "", "", "",
59 "BadVAddr", "", "", "", "", "", "", "",
60 "Count", "", "", "", "", "", "", "",
61 "EntryHi", "", "", "", "", "", "", "",
62 "Compare", "", "", "", "", "", "", "",
63 "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
64 "Cause", "", "", "", "", "", "", "",
65 "EPC", "", "", "", "", "", "", "",
66 "PRId", "EBase", "", "", "", "", "", "",
67 "Config", "Config1", "Config2", "Config3", "", "", "", "",
68 "LLAddr", "", "", "", "", "", "", "",
69 "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
70 "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
71 "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
72 "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
73 "XCContext64", "", "", "", "", "", "", "",
74 "", "", "", "", "", "", "", "",
75 "", "", "", "", "", "", "", "",
76 "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
77 "TraceBPC", "", "", "",
78 "DEPC", "", "", "", "", "", "", "",
79 "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
80 "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
81 "ErrCtl", "", "", "", "", "", "", "",
82 "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
83 "TagLo0", "DataLo1", "TagLo2", "DataLo3",
84 "TagLo4", "DataLo5", "TagLo6", "DataLo7",
85 "TagHi0", "DataHi1", "TagHi2", "DataHi3",
86 "TagHi4", "DataHi5", "TagHi6", "DataHi7",
87 "ErrorEPC", "", "", "", "", "", "", "",
88 "DESAVE", "", "", "", "", "", "", "",
89 "LLFlag"
90};
91
92ISA::ISA(Params *p)
93 : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
94{
95 miscRegFile.resize(NumMiscRegs);
96 bankType.resize(NumMiscRegs);
97
98 for (int i=0; i < NumMiscRegs; i++) {
99 miscRegFile[i].resize(1);
100 bankType[i] = perProcessor;
101 }
102
103 miscRegFile_WriteMask.resize(NumMiscRegs);
104
105 for (int i = 0; i < NumMiscRegs; i++) {
106 miscRegFile_WriteMask[i].push_back(0);
107 }
108
109 // Initialize all Per-VPE regs
110 uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
111 MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
112 MISCREG_YQMASK,
113 MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
114 MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
115 MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
116 MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
117 MISCREG_EBASE
118 };
119 uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
120 for (int i = 0; i < num_vpe_regs; i++) {
121 if (numVpes > 1) {
122 miscRegFile[per_vpe_regs[i]].resize(numVpes);
123 }
124 bankType[per_vpe_regs[i]] = perVirtProcessor;
125 }
126
127 // Initialize all Per-TC regs
128 uint32_t per_tc_regs[] = { MISCREG_STATUS,
129 MISCREG_TC_STATUS, MISCREG_TC_BIND,
130 MISCREG_TC_RESTART, MISCREG_TC_HALT,
131 MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
132 MISCREG_TC_SCHEFBACK,
133 MISCREG_DEBUG, MISCREG_LLADDR
134 };
135 uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
136
137 for (int i = 0; i < num_tc_regs; i++) {
138 miscRegFile[per_tc_regs[i]].resize(numThreads);
139 bankType[per_tc_regs[i]] = perThreadContext;
140 }
141
142 clear();
143}
144
145const MipsISAParams *
146ISA::params() const
147{
148 return dynamic_cast<const Params *>(_params);
149}
150
151void
152ISA::clear()
153{
154 for (int i = 0; i < NumMiscRegs; i++) {
155 for (int j = 0; j < miscRegFile[i].size(); j++)
156 miscRegFile[i][j] = 0;
157
158 for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
159 miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
160 }
161}
162
163
164void
165ISA::configCP()
166{
167 DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
168 numThreads, numVpes);
169
170 CoreSpecific cp;
171 panic("CP state must be set before the following code is used");
172
173 // Do Default CP0 initialization HERE
174
175 // Do Initialization for MT cores here (eventually use
176 // core_name parameter to toggle this initialization)
177 // ===================================================
178 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
179
180 PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
181 procId.coOp = cp.CP0_PRId_CompanyOptions;
182 procId.coId = cp.CP0_PRId_CompanyID;
183 procId.procId = cp.CP0_PRId_ProcessorID;
184 procId.rev = cp.CP0_PRId_Revision;
185 setMiscRegNoEffect(MISCREG_PRID, procId);
186
187 // Now, create Write Mask for ProcID register
188 RegVal procIDMask = 0; // Read-Only register
189 replaceBits(procIDMask, 0, 32, 0);
190 setRegMask(MISCREG_PRID, procIDMask);
191
192 // Config
193 ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
194 cfg.be = cp.CP0_Config_BE;
195 cfg.at = cp.CP0_Config_AT;
196 cfg.ar = cp.CP0_Config_AR;
197 cfg.mt = cp.CP0_Config_MT;
198 cfg.vi = cp.CP0_Config_VI;
199 cfg.m = 1;
200 setMiscRegNoEffect(MISCREG_CONFIG, cfg);
201 // Now, create Write Mask for Config register
202 RegVal cfg_Mask = 0x7FFF0007;
203 replaceBits(cfg_Mask, 0, 32, 0);
204 setRegMask(MISCREG_CONFIG, cfg_Mask);
205
206 // Config1
207 Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
208 cfg1.mmuSize = cp.CP0_Config1_MMU;
209 cfg1.is = cp.CP0_Config1_IS;
210 cfg1.il = cp.CP0_Config1_IL;
211 cfg1.ia = cp.CP0_Config1_IA;
212 cfg1.ds = cp.CP0_Config1_DS;
213 cfg1.dl = cp.CP0_Config1_DL;
214 cfg1.da = cp.CP0_Config1_DA;
215 cfg1.fp = cp.CP0_Config1_FP;
216 cfg1.ep = cp.CP0_Config1_EP;
217 cfg1.wr = cp.CP0_Config1_WR;
218 cfg1.md = cp.CP0_Config1_MD;
219 cfg1.c2 = cp.CP0_Config1_C2;
220 cfg1.pc = cp.CP0_Config1_PC;
221 cfg1.m = cp.CP0_Config1_M;
222 setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
223 // Now, create Write Mask for Config register
224 RegVal cfg1_Mask = 0; // Read Only Register
225 replaceBits(cfg1_Mask, 0, 32, 0);
226 setRegMask(MISCREG_CONFIG1, cfg1_Mask);
227
228 // Config2
229 Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
230 cfg2.tu = cp.CP0_Config2_TU;
231 cfg2.ts = cp.CP0_Config2_TS;
232 cfg2.tl = cp.CP0_Config2_TL;
233 cfg2.ta = cp.CP0_Config2_TA;
234 cfg2.su = cp.CP0_Config2_SU;
235 cfg2.ss = cp.CP0_Config2_SS;
236 cfg2.sl = cp.CP0_Config2_SL;
237 cfg2.sa = cp.CP0_Config2_SA;
238 cfg2.m = cp.CP0_Config2_M;
239 setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
240 // Now, create Write Mask for Config register
241 RegVal cfg2_Mask = 0x7000F000; // Read Only Register
242 replaceBits(cfg2_Mask, 0, 32, 0);
243 setRegMask(MISCREG_CONFIG2, cfg2_Mask);
244
245 // Config3
246 Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
247 cfg3.dspp = cp.CP0_Config3_DSPP;
248 cfg3.lpa = cp.CP0_Config3_LPA;
249 cfg3.veic = cp.CP0_Config3_VEIC;
250 cfg3.vint = cp.CP0_Config3_VInt;
251 cfg3.sp = cp.CP0_Config3_SP;
252 cfg3.mt = cp.CP0_Config3_MT;
253 cfg3.sm = cp.CP0_Config3_SM;
254 cfg3.tl = cp.CP0_Config3_TL;
255 setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
256 // Now, create Write Mask for Config register
257 RegVal cfg3_Mask = 0; // Read Only Register
258 replaceBits(cfg3_Mask, 0, 32, 0);
259 setRegMask(MISCREG_CONFIG3, cfg3_Mask);
260
261 // EBase - CPUNum
262 EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
263 eBase.cpuNum = cp.CP0_EBase_CPUNum;
264 replaceBits(eBase, 31, 31, 1);
265 setMiscRegNoEffect(MISCREG_EBASE, eBase);
266 // Now, create Write Mask for Config register
267 RegVal EB_Mask = 0x3FFFF000;// Except Exception Base, the
268 // entire register is read only
269 replaceBits(EB_Mask, 0, 32, 0);
270 setRegMask(MISCREG_EBASE, EB_Mask);
271
272 // SRS Control - HSS (Highest Shadow Set)
273 SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
274 scsCtl.hss = cp.CP0_SrsCtl_HSS;
275 setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
276 // Now, create Write Mask for the SRS Ctl register
277 RegVal SC_Mask = 0x0000F3C0;
278 replaceBits(SC_Mask, 0, 32, 0);
279 setRegMask(MISCREG_SRSCTL, SC_Mask);
280
281 // IntCtl - IPTI, IPPCI
282 IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
283 intCtl.ipti = cp.CP0_IntCtl_IPTI;
284 intCtl.ippci = cp.CP0_IntCtl_IPPCI;
285 setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
286 // Now, create Write Mask for the IntCtl register
287 RegVal IC_Mask = 0x000003E0;
288 replaceBits(IC_Mask, 0, 32, 0);
289 setRegMask(MISCREG_INTCTL, IC_Mask);
290
291 // Watch Hi - M - FIXME (More than 1 Watch register)
292 WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
293 watchHi.m = cp.CP0_WatchHi_M;
294 setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
295 // Now, create Write Mask for the IntCtl register
296 RegVal wh_Mask = 0x7FFF0FFF;
297 replaceBits(wh_Mask, 0, 32, 0);
298 setRegMask(MISCREG_WATCHHI0, wh_Mask);
299
300 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
301 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
302 perfCntCtl.m = cp.CP0_PerfCtr_M;
303 perfCntCtl.w = cp.CP0_PerfCtr_W;
304 setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
305 // Now, create Write Mask for the IntCtl register
306 RegVal pc_Mask = 0x00007FF;
307 replaceBits(pc_Mask, 0, 32, 0);
308 setRegMask(MISCREG_PERFCNT0, pc_Mask);
309
310 // Random
311 setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
312 // Now, create Write Mask for the IntCtl register
313 RegVal random_Mask = 0;
314 replaceBits(random_Mask, 0, 32, 0);
315 setRegMask(MISCREG_CP0_RANDOM, random_Mask);
316
317 // PageGrain
318 PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
319 pageGrain.esp = cp.CP0_Config3_SP;
320 setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
321 // Now, create Write Mask for the IntCtl register
322 RegVal pg_Mask = 0x10000000;
323 replaceBits(pg_Mask, 0, 32, 0);
324 setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
325
326 // Status
327 StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
328 // Only CU0 and IE are modified on a reset - everything else needs
329 // to be controlled on a per CPU model basis
330
331 // Enable CP0 on reset
332 // status.cu0 = 1;
333
334 // Enable ERL bit on a reset
335 status.erl = 1;
336 // Enable BEV bit on a reset
337 status.bev = 1;
338
339 setMiscRegNoEffect(MISCREG_STATUS, status);
340 // Now, create Write Mask for the Status register
341 RegVal stat_Mask = 0xFF78FF17;
342 replaceBits(stat_Mask, 0, 32, 0);
343 setRegMask(MISCREG_STATUS, stat_Mask);
344
345
346 // MVPConf0
347 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
348 mvpConf0.tca = 1;
349 mvpConf0.pvpe = numVpes - 1;
350 mvpConf0.ptc = numThreads - 1;
351 setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
352
353 // VPEConf0
354 VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
355 vpeConf0.mvp = 1;
356 setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
357
358 // TCBind
359 for (ThreadID tid = 0; tid < numThreads; tid++) {
360 TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
361 tcBind.curTC = tid;
362 setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
363 }
364 // TCHalt
365 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
366 tcHalt.h = 0;
367 setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
368
369 // TCStatus
370 // Set TCStatus Activated to 1 for the initial thread that is running
371 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
372 tcStatus.a = 1;
373 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
374
375 // Set Dynamically Allocatable bit to 1 for all other threads
376 for (ThreadID tid = 1; tid < numThreads; tid++) {
377 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
378 tcStatus.da = 1;
379 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
380 }
381
382
383 RegVal mask = 0x7FFFFFFF;
384
385 // Now, create Write Mask for the Index register
386 replaceBits(mask, 0, 32, 0);
387 setRegMask(MISCREG_INDEX, mask);
388
389 mask = 0x3FFFFFFF;
390 replaceBits(mask, 0, 32, 0);
391 setRegMask(MISCREG_ENTRYLO0, mask);
392 setRegMask(MISCREG_ENTRYLO1, mask);
393
394 mask = 0xFF800000;
395 replaceBits(mask, 0, 32, 0);
396 setRegMask(MISCREG_CONTEXT, mask);
397
398 mask = 0x1FFFF800;
399 replaceBits(mask, 0, 32, 0);
400 setRegMask(MISCREG_PAGEMASK, mask);
401
402 mask = 0x0;
403 replaceBits(mask, 0, 32, 0);
404 setRegMask(MISCREG_BADVADDR, mask);
405 setRegMask(MISCREG_LLADDR, mask);
406
407 mask = 0x08C00300;
408 replaceBits(mask, 0, 32, 0);
409 setRegMask(MISCREG_CAUSE, mask);
410
411}
412
413inline unsigned
414ISA::getVPENum(ThreadID tid) const
415{
416 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
417 return tcBind.curVPE;
418}
419
420RegVal
421ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
422{
423 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
424 ? tid : getVPENum(tid);
425 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
426 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
427 miscRegFile[misc_reg][reg_sel]);
428 return miscRegFile[misc_reg][reg_sel];
429}
430
431//@TODO: MIPS MT's register view automatically connects
432// Status to TCStatus depending on current thread
433//template <class TC>
434RegVal
435ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
436{
437 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
438 ? tid : getVPENum(tid);
439 DPRINTF(MipsPRA,
440 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
441 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
442 miscRegFile[misc_reg][reg_sel]);
443
444 return miscRegFile[misc_reg][reg_sel];
445}
446
447void
448ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
449{
450 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
451 ? tid : getVPENum(tid);
452 DPRINTF(MipsPRA,
| 1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/mips/isa.hh"
32
33#include "arch/mips/mt.hh"
34#include "arch/mips/mt_constants.hh"
35#include "arch/mips/pra_constants.hh"
36#include "base/bitfield.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"
40#include "params/MipsISA.hh"
41
42namespace MipsISA
43{
44
45std::string
46ISA::miscRegNames[NumMiscRegs] =
47{
48 "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
49 "Random", "VPEControl", "VPEConf0", "VPEConf1",
50 "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
51 "EntryLo0", "TCStatus", "TCBind", "TCRestart",
52 "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
53 "EntryLo1", "", "", "", "", "", "", "",
54 "Context", "ContextConfig", "", "", "", "", "", "",
55 "PageMask", "PageGrain", "", "", "", "", "", "",
56 "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
57 "SRSConf3", "SRSConf4", "", "",
58 "HWREna", "", "", "", "", "", "", "",
59 "BadVAddr", "", "", "", "", "", "", "",
60 "Count", "", "", "", "", "", "", "",
61 "EntryHi", "", "", "", "", "", "", "",
62 "Compare", "", "", "", "", "", "", "",
63 "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
64 "Cause", "", "", "", "", "", "", "",
65 "EPC", "", "", "", "", "", "", "",
66 "PRId", "EBase", "", "", "", "", "", "",
67 "Config", "Config1", "Config2", "Config3", "", "", "", "",
68 "LLAddr", "", "", "", "", "", "", "",
69 "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
70 "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
71 "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
72 "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
73 "XCContext64", "", "", "", "", "", "", "",
74 "", "", "", "", "", "", "", "",
75 "", "", "", "", "", "", "", "",
76 "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
77 "TraceBPC", "", "", "",
78 "DEPC", "", "", "", "", "", "", "",
79 "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
80 "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
81 "ErrCtl", "", "", "", "", "", "", "",
82 "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
83 "TagLo0", "DataLo1", "TagLo2", "DataLo3",
84 "TagLo4", "DataLo5", "TagLo6", "DataLo7",
85 "TagHi0", "DataHi1", "TagHi2", "DataHi3",
86 "TagHi4", "DataHi5", "TagHi6", "DataHi7",
87 "ErrorEPC", "", "", "", "", "", "", "",
88 "DESAVE", "", "", "", "", "", "", "",
89 "LLFlag"
90};
91
92ISA::ISA(Params *p)
93 : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
94{
95 miscRegFile.resize(NumMiscRegs);
96 bankType.resize(NumMiscRegs);
97
98 for (int i=0; i < NumMiscRegs; i++) {
99 miscRegFile[i].resize(1);
100 bankType[i] = perProcessor;
101 }
102
103 miscRegFile_WriteMask.resize(NumMiscRegs);
104
105 for (int i = 0; i < NumMiscRegs; i++) {
106 miscRegFile_WriteMask[i].push_back(0);
107 }
108
109 // Initialize all Per-VPE regs
110 uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
111 MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
112 MISCREG_YQMASK,
113 MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
114 MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
115 MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
116 MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
117 MISCREG_EBASE
118 };
119 uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
120 for (int i = 0; i < num_vpe_regs; i++) {
121 if (numVpes > 1) {
122 miscRegFile[per_vpe_regs[i]].resize(numVpes);
123 }
124 bankType[per_vpe_regs[i]] = perVirtProcessor;
125 }
126
127 // Initialize all Per-TC regs
128 uint32_t per_tc_regs[] = { MISCREG_STATUS,
129 MISCREG_TC_STATUS, MISCREG_TC_BIND,
130 MISCREG_TC_RESTART, MISCREG_TC_HALT,
131 MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
132 MISCREG_TC_SCHEFBACK,
133 MISCREG_DEBUG, MISCREG_LLADDR
134 };
135 uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
136
137 for (int i = 0; i < num_tc_regs; i++) {
138 miscRegFile[per_tc_regs[i]].resize(numThreads);
139 bankType[per_tc_regs[i]] = perThreadContext;
140 }
141
142 clear();
143}
144
145const MipsISAParams *
146ISA::params() const
147{
148 return dynamic_cast<const Params *>(_params);
149}
150
151void
152ISA::clear()
153{
154 for (int i = 0; i < NumMiscRegs; i++) {
155 for (int j = 0; j < miscRegFile[i].size(); j++)
156 miscRegFile[i][j] = 0;
157
158 for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
159 miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
160 }
161}
162
163
164void
165ISA::configCP()
166{
167 DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
168 numThreads, numVpes);
169
170 CoreSpecific cp;
171 panic("CP state must be set before the following code is used");
172
173 // Do Default CP0 initialization HERE
174
175 // Do Initialization for MT cores here (eventually use
176 // core_name parameter to toggle this initialization)
177 // ===================================================
178 DPRINTF(MipsPRA, "Initializing CP0 State.... ");
179
180 PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
181 procId.coOp = cp.CP0_PRId_CompanyOptions;
182 procId.coId = cp.CP0_PRId_CompanyID;
183 procId.procId = cp.CP0_PRId_ProcessorID;
184 procId.rev = cp.CP0_PRId_Revision;
185 setMiscRegNoEffect(MISCREG_PRID, procId);
186
187 // Now, create Write Mask for ProcID register
188 RegVal procIDMask = 0; // Read-Only register
189 replaceBits(procIDMask, 0, 32, 0);
190 setRegMask(MISCREG_PRID, procIDMask);
191
192 // Config
193 ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
194 cfg.be = cp.CP0_Config_BE;
195 cfg.at = cp.CP0_Config_AT;
196 cfg.ar = cp.CP0_Config_AR;
197 cfg.mt = cp.CP0_Config_MT;
198 cfg.vi = cp.CP0_Config_VI;
199 cfg.m = 1;
200 setMiscRegNoEffect(MISCREG_CONFIG, cfg);
201 // Now, create Write Mask for Config register
202 RegVal cfg_Mask = 0x7FFF0007;
203 replaceBits(cfg_Mask, 0, 32, 0);
204 setRegMask(MISCREG_CONFIG, cfg_Mask);
205
206 // Config1
207 Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
208 cfg1.mmuSize = cp.CP0_Config1_MMU;
209 cfg1.is = cp.CP0_Config1_IS;
210 cfg1.il = cp.CP0_Config1_IL;
211 cfg1.ia = cp.CP0_Config1_IA;
212 cfg1.ds = cp.CP0_Config1_DS;
213 cfg1.dl = cp.CP0_Config1_DL;
214 cfg1.da = cp.CP0_Config1_DA;
215 cfg1.fp = cp.CP0_Config1_FP;
216 cfg1.ep = cp.CP0_Config1_EP;
217 cfg1.wr = cp.CP0_Config1_WR;
218 cfg1.md = cp.CP0_Config1_MD;
219 cfg1.c2 = cp.CP0_Config1_C2;
220 cfg1.pc = cp.CP0_Config1_PC;
221 cfg1.m = cp.CP0_Config1_M;
222 setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
223 // Now, create Write Mask for Config register
224 RegVal cfg1_Mask = 0; // Read Only Register
225 replaceBits(cfg1_Mask, 0, 32, 0);
226 setRegMask(MISCREG_CONFIG1, cfg1_Mask);
227
228 // Config2
229 Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
230 cfg2.tu = cp.CP0_Config2_TU;
231 cfg2.ts = cp.CP0_Config2_TS;
232 cfg2.tl = cp.CP0_Config2_TL;
233 cfg2.ta = cp.CP0_Config2_TA;
234 cfg2.su = cp.CP0_Config2_SU;
235 cfg2.ss = cp.CP0_Config2_SS;
236 cfg2.sl = cp.CP0_Config2_SL;
237 cfg2.sa = cp.CP0_Config2_SA;
238 cfg2.m = cp.CP0_Config2_M;
239 setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
240 // Now, create Write Mask for Config register
241 RegVal cfg2_Mask = 0x7000F000; // Read Only Register
242 replaceBits(cfg2_Mask, 0, 32, 0);
243 setRegMask(MISCREG_CONFIG2, cfg2_Mask);
244
245 // Config3
246 Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
247 cfg3.dspp = cp.CP0_Config3_DSPP;
248 cfg3.lpa = cp.CP0_Config3_LPA;
249 cfg3.veic = cp.CP0_Config3_VEIC;
250 cfg3.vint = cp.CP0_Config3_VInt;
251 cfg3.sp = cp.CP0_Config3_SP;
252 cfg3.mt = cp.CP0_Config3_MT;
253 cfg3.sm = cp.CP0_Config3_SM;
254 cfg3.tl = cp.CP0_Config3_TL;
255 setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
256 // Now, create Write Mask for Config register
257 RegVal cfg3_Mask = 0; // Read Only Register
258 replaceBits(cfg3_Mask, 0, 32, 0);
259 setRegMask(MISCREG_CONFIG3, cfg3_Mask);
260
261 // EBase - CPUNum
262 EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
263 eBase.cpuNum = cp.CP0_EBase_CPUNum;
264 replaceBits(eBase, 31, 31, 1);
265 setMiscRegNoEffect(MISCREG_EBASE, eBase);
266 // Now, create Write Mask for Config register
267 RegVal EB_Mask = 0x3FFFF000;// Except Exception Base, the
268 // entire register is read only
269 replaceBits(EB_Mask, 0, 32, 0);
270 setRegMask(MISCREG_EBASE, EB_Mask);
271
272 // SRS Control - HSS (Highest Shadow Set)
273 SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
274 scsCtl.hss = cp.CP0_SrsCtl_HSS;
275 setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
276 // Now, create Write Mask for the SRS Ctl register
277 RegVal SC_Mask = 0x0000F3C0;
278 replaceBits(SC_Mask, 0, 32, 0);
279 setRegMask(MISCREG_SRSCTL, SC_Mask);
280
281 // IntCtl - IPTI, IPPCI
282 IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
283 intCtl.ipti = cp.CP0_IntCtl_IPTI;
284 intCtl.ippci = cp.CP0_IntCtl_IPPCI;
285 setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
286 // Now, create Write Mask for the IntCtl register
287 RegVal IC_Mask = 0x000003E0;
288 replaceBits(IC_Mask, 0, 32, 0);
289 setRegMask(MISCREG_INTCTL, IC_Mask);
290
291 // Watch Hi - M - FIXME (More than 1 Watch register)
292 WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
293 watchHi.m = cp.CP0_WatchHi_M;
294 setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
295 // Now, create Write Mask for the IntCtl register
296 RegVal wh_Mask = 0x7FFF0FFF;
297 replaceBits(wh_Mask, 0, 32, 0);
298 setRegMask(MISCREG_WATCHHI0, wh_Mask);
299
300 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
301 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
302 perfCntCtl.m = cp.CP0_PerfCtr_M;
303 perfCntCtl.w = cp.CP0_PerfCtr_W;
304 setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
305 // Now, create Write Mask for the IntCtl register
306 RegVal pc_Mask = 0x00007FF;
307 replaceBits(pc_Mask, 0, 32, 0);
308 setRegMask(MISCREG_PERFCNT0, pc_Mask);
309
310 // Random
311 setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
312 // Now, create Write Mask for the IntCtl register
313 RegVal random_Mask = 0;
314 replaceBits(random_Mask, 0, 32, 0);
315 setRegMask(MISCREG_CP0_RANDOM, random_Mask);
316
317 // PageGrain
318 PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
319 pageGrain.esp = cp.CP0_Config3_SP;
320 setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
321 // Now, create Write Mask for the IntCtl register
322 RegVal pg_Mask = 0x10000000;
323 replaceBits(pg_Mask, 0, 32, 0);
324 setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
325
326 // Status
327 StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
328 // Only CU0 and IE are modified on a reset - everything else needs
329 // to be controlled on a per CPU model basis
330
331 // Enable CP0 on reset
332 // status.cu0 = 1;
333
334 // Enable ERL bit on a reset
335 status.erl = 1;
336 // Enable BEV bit on a reset
337 status.bev = 1;
338
339 setMiscRegNoEffect(MISCREG_STATUS, status);
340 // Now, create Write Mask for the Status register
341 RegVal stat_Mask = 0xFF78FF17;
342 replaceBits(stat_Mask, 0, 32, 0);
343 setRegMask(MISCREG_STATUS, stat_Mask);
344
345
346 // MVPConf0
347 MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
348 mvpConf0.tca = 1;
349 mvpConf0.pvpe = numVpes - 1;
350 mvpConf0.ptc = numThreads - 1;
351 setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
352
353 // VPEConf0
354 VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
355 vpeConf0.mvp = 1;
356 setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
357
358 // TCBind
359 for (ThreadID tid = 0; tid < numThreads; tid++) {
360 TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
361 tcBind.curTC = tid;
362 setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
363 }
364 // TCHalt
365 TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
366 tcHalt.h = 0;
367 setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
368
369 // TCStatus
370 // Set TCStatus Activated to 1 for the initial thread that is running
371 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
372 tcStatus.a = 1;
373 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
374
375 // Set Dynamically Allocatable bit to 1 for all other threads
376 for (ThreadID tid = 1; tid < numThreads; tid++) {
377 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
378 tcStatus.da = 1;
379 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
380 }
381
382
383 RegVal mask = 0x7FFFFFFF;
384
385 // Now, create Write Mask for the Index register
386 replaceBits(mask, 0, 32, 0);
387 setRegMask(MISCREG_INDEX, mask);
388
389 mask = 0x3FFFFFFF;
390 replaceBits(mask, 0, 32, 0);
391 setRegMask(MISCREG_ENTRYLO0, mask);
392 setRegMask(MISCREG_ENTRYLO1, mask);
393
394 mask = 0xFF800000;
395 replaceBits(mask, 0, 32, 0);
396 setRegMask(MISCREG_CONTEXT, mask);
397
398 mask = 0x1FFFF800;
399 replaceBits(mask, 0, 32, 0);
400 setRegMask(MISCREG_PAGEMASK, mask);
401
402 mask = 0x0;
403 replaceBits(mask, 0, 32, 0);
404 setRegMask(MISCREG_BADVADDR, mask);
405 setRegMask(MISCREG_LLADDR, mask);
406
407 mask = 0x08C00300;
408 replaceBits(mask, 0, 32, 0);
409 setRegMask(MISCREG_CAUSE, mask);
410
411}
412
413inline unsigned
414ISA::getVPENum(ThreadID tid) const
415{
416 TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
417 return tcBind.curVPE;
418}
419
420RegVal
421ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
422{
423 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
424 ? tid : getVPENum(tid);
425 DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
426 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
427 miscRegFile[misc_reg][reg_sel]);
428 return miscRegFile[misc_reg][reg_sel];
429}
430
431//@TODO: MIPS MT's register view automatically connects
432// Status to TCStatus depending on current thread
433//template <class TC>
434RegVal
435ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
436{
437 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
438 ? tid : getVPENum(tid);
439 DPRINTF(MipsPRA,
440 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
441 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
442 miscRegFile[misc_reg][reg_sel]);
443
444 return miscRegFile[misc_reg][reg_sel];
445}
446
447void
448ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
449{
450 unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
451 ? tid : getVPENum(tid);
452 DPRINTF(MipsPRA,
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