isa.cc (11793:ef606668d247) | isa.cc (12124:6edbfe40f4e8) |
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1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 509 unchanged lines hidden (view full) --- 518 519void 520ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) 521{ 522 if (!cp0Updated) { 523 cp0Updated = true; 524 525 //schedule UPDATE | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 509 unchanged lines hidden (view full) --- 518 519void 520ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) 521{ 522 if (!cp0Updated) { 523 cp0Updated = true; 524 525 //schedule UPDATE |
526 CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); | 526 auto cp0_event = new EventFunctionWrapper( 527 [this, cpu]{ processCP0Event(cpu, UpdateCP0); }, 528 "Coprocessor-0 event", true, Event::CPU_Tick_Pri); |
527 cpu->schedule(cp0_event, cpu->clockEdge(delay)); 528 } 529} 530 531void 532ISA::updateCPU(BaseCPU *cpu) 533{ 534 /////////////////////////////////////////////////////////////////// --- 17 unchanged lines hidden (view full) --- 552 } 553 554 num_threads = mvpConf0.ptc + 1; 555 556 // Toggle update flag after we finished updating 557 cp0Updated = false; 558} 559 | 529 cpu->schedule(cp0_event, cpu->clockEdge(delay)); 530 } 531} 532 533void 534ISA::updateCPU(BaseCPU *cpu) 535{ 536 /////////////////////////////////////////////////////////////////// --- 17 unchanged lines hidden (view full) --- 554 } 555 556 num_threads = mvpConf0.ptc + 1; 557 558 // Toggle update flag after we finished updating 559 cp0Updated = false; 560} 561 |
560ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) 561 : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) 562{ } 563 | |
564void | 562void |
565ISA::CP0Event::process() | 563ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType) |
566{ 567 switch (cp0EventType) 568 { 569 case UpdateCP0: | 564{ 565 switch (cp0EventType) 566 { 567 case UpdateCP0: |
570 cp0->updateCPU(cpu); | 568 updateCPU(cpu); |
571 break; 572 } 573} 574 | 569 break; 570 } 571} 572 |
575const char * 576ISA::CP0Event::description() const 577{ 578 return "Coprocessor-0 event"; | |
579} 580 | 573} 574 |
581void 582ISA::CP0Event::scheduleEvent(Cycles delay) 583{ 584 cpu->reschedule(this, cpu->clockEdge(delay), true); 585} 586 587void 588ISA::CP0Event::unscheduleEvent() 589{ 590 if (scheduled()) 591 squash(); 592} 593 594} 595 | |
596MipsISA::ISA * 597MipsISAParams::create() 598{ 599 return new MipsISA::ISA(this); 600} | 575MipsISA::ISA * 576MipsISAParams::create() 577{ 578 return new MipsISA::ISA(this); 579} |