1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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518
519void
520ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay)
521{
522 if (!cp0Updated) {
523 cp0Updated = true;
524
525 //schedule UPDATE
526 auto cp0_event = new EventFunctionWrapper(
527 [this, cpu]{ processCP0Event(cpu, UpdateCP0); },
528 "Coprocessor-0 event", true, Event::CPU_Tick_Pri);
529 cpu->schedule(cp0_event, cpu->clockEdge(delay));
530 }
531}
532
533void
534ISA::updateCPU(BaseCPU *cpu)
535{
536 ///////////////////////////////////////////////////////////////////

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554 }
555
556 num_threads = mvpConf0.ptc + 1;
557
558 // Toggle update flag after we finished updating
559 cp0Updated = false;
560}
561
562void
563ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType)
564{
565 switch (cp0EventType)
566 {
567 case UpdateCP0:
568 updateCPU(cpu);
569 break;
570 }
571}
572
573}
574
575MipsISA::ISA *
576MipsISAParams::create()
577{
578 return new MipsISA::ISA(this);
579}