interrupts.hh (5704:98224505352a) | interrupts.hh (6378:4a2ff62c3b4f) |
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1/* 2 * Copyright (c) 2007 MIPS Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Rick Strong 29 */ 30 31#ifndef __ARCH_MIPS_INTERRUPT_HH__ 32#define __ARCH_MIPS_INTERRUPT_HH__ 33 | 1/* 2 * Copyright (c) 2007 MIPS Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Rick Strong 29 */ 30 31#ifndef __ARCH_MIPS_INTERRUPT_HH__ 32#define __ARCH_MIPS_INTERRUPT_HH__ 33 |
34 | |
35#include "arch/mips/faults.hh" 36#include "base/compiler.hh" 37 | 34#include "arch/mips/faults.hh" 35#include "base/compiler.hh" 36 |
38 39 | |
40namespace MipsISA 41{ | 37namespace MipsISA 38{ |
39 |
|
42class Interrupts 43{ | 40class Interrupts 41{ |
44 /* 45 protected: 46 uint8_t intstatus; 47 bool oncputimerintr; 48 public: 49 Interrupts() 50 { 51 intstatus = 0; 52 newInfoSet = false; 53 oncputimerintr = false; 54 55 } 56 // post(int int_num, int index) is responsible 57 // for posting an interrupt. It sets a bit 58 // in intstatus corresponding to Cause IP*. The 59 // MIPS register Cause is updated by updateIntrInfo 60 // which is called by checkInterrupts 61 // 62 void post(int int_num, int index); 63 // clear(int int_num, int index) is responsible 64 // for clearing an interrupt. It clear a bit 65 // in intstatus corresponding to Cause IP*. The 66 // MIPS register Cause is updated by updateIntrInfo 67 // which is called by checkInterrupts 68 // 69 void clear(int int_num, int index); 70 // clearAll() is responsible 71 // for clearing all interrupts. It clears all bits 72 // in intstatus corresponding to Cause IP*. The 73 // MIPS register Cause is updated by updateIntrInfo 74 // which is called by checkInterrupts 75 // 76 void clearAll(); 77 78 // getInterrupt(ThreadContext * tc) checks if an interrupt 79 // should be returned. It ands the interrupt mask and 80 // and interrupt pending bits to see if one exists. It 81 // also makes sure interrupts are enabled (IE) and 82 // that ERL and ERX are not set 83 // 84 Fault getInterrupt(ThreadContext * tc); 85 86 // updateIntrInfo(ThreadContext *tc) const syncs the 87 // MIPS cause register with the instatus variable. instatus 88 // is essentially a copy of the MIPS cause[IP7:IP0] 89 // 90 void updateIntrInfo(ThreadContext *tc) const; 91 void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const; 92 bool onCpuTimerInterrupt(ThreadContext *tc) const; 93 94 bool checkInterrupts(ThreadContext *tc) const { 95 //return (intstatus != 0) && !(tc->readPC() & 0x3); 96 if (oncputimerintr == false){ 97 updateIntrInfo(tc); 98 return ((intstatus != 0) || onCpuTimerInterrupt(tc)); 99 } 100 else 101 return true; 102 103 } 104 */ 105 106 107 protected: 108 //uint8_t intstatus; 109 //bool oncputimerintr; | |
110 public: 111 Interrupts() 112 { | 42 public: 43 Interrupts() 44 { |
113 //intstatus = 0; | |
114 newInfoSet = false; | 45 newInfoSet = false; |
115 //oncputimerintr = false; 116 | |
117 } | 46 } |
47 |
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118 // post(int int_num, int index) is responsible 119 // for posting an interrupt. It sets a bit 120 // in intstatus corresponding to Cause IP*. The 121 // MIPS register Cause is updated by updateIntrInfo 122 // which is called by checkInterrupts 123 // | 48 // post(int int_num, int index) is responsible 49 // for posting an interrupt. It sets a bit 50 // in intstatus corresponding to Cause IP*. The 51 // MIPS register Cause is updated by updateIntrInfo 52 // which is called by checkInterrupts 53 // |
124 void post(int int_num, ThreadContext* tc); | 54 void post(int int_num, ThreadContext *tc); |
125 void post(int int_num, int index); 126 127 // clear(int int_num, int index) is responsible 128 // for clearing an interrupt. It clear a bit 129 // in intstatus corresponding to Cause IP*. The 130 // MIPS register Cause is updated by updateIntrInfo 131 // which is called by checkInterrupts 132 // 133 void clear(int int_num, ThreadContext* tc); 134 void clear(int int_num, int index); 135 136 // clearAll() is responsible 137 // for clearing all interrupts. It clears all bits 138 // in intstatus corresponding to Cause IP*. The 139 // MIPS register Cause is updated by updateIntrInfo 140 // which is called by checkInterrupts 141 // | 55 void post(int int_num, int index); 56 57 // clear(int int_num, int index) is responsible 58 // for clearing an interrupt. It clear a bit 59 // in intstatus corresponding to Cause IP*. The 60 // MIPS register Cause is updated by updateIntrInfo 61 // which is called by checkInterrupts 62 // 63 void clear(int int_num, ThreadContext* tc); 64 void clear(int int_num, int index); 65 66 // clearAll() is responsible 67 // for clearing all interrupts. It clears all bits 68 // in intstatus corresponding to Cause IP*. The 69 // MIPS register Cause is updated by updateIntrInfo 70 // which is called by checkInterrupts 71 // |
142 void clearAll(ThreadContext* tc); | 72 void clearAll(ThreadContext *tc); |
143 void clearAll(); 144 145 // getInterrupt(ThreadContext * tc) checks if an interrupt 146 // should be returned. It ands the interrupt mask and 147 // and interrupt pending bits to see if one exists. It 148 // also makes sure interrupts are enabled (IE) and 149 // that ERL and ERX are not set 150 // | 73 void clearAll(); 74 75 // getInterrupt(ThreadContext * tc) checks if an interrupt 76 // should be returned. It ands the interrupt mask and 77 // and interrupt pending bits to see if one exists. It 78 // also makes sure interrupts are enabled (IE) and 79 // that ERL and ERX are not set 80 // |
151 Fault getInterrupt(ThreadContext * tc); | 81 Fault getInterrupt(ThreadContext *tc); |
152 153 // updateIntrInfo(ThreadContext *tc) const syncs the 154 // MIPS cause register with the instatus variable. instatus 155 // is essentially a copy of the MIPS cause[IP7:IP0] 156 // 157 void updateIntrInfo(ThreadContext *tc) const; 158 bool interruptsPending(ThreadContext *tc) const; 159 bool onCpuTimerInterrupt(ThreadContext *tc) const; 160 161 bool 162 checkInterrupts(ThreadContext *tc) const 163 { 164 return interruptsPending(tc); 165 } 166 167 | 82 83 // updateIntrInfo(ThreadContext *tc) const syncs the 84 // MIPS cause register with the instatus variable. instatus 85 // is essentially a copy of the MIPS cause[IP7:IP0] 86 // 87 void updateIntrInfo(ThreadContext *tc) const; 88 bool interruptsPending(ThreadContext *tc) const; 89 bool onCpuTimerInterrupt(ThreadContext *tc) const; 90 91 bool 92 checkInterrupts(ThreadContext *tc) const 93 { 94 return interruptsPending(tc); 95 } 96 97 |
168 void serialize(std::ostream &os) | 98 void 99 serialize(std::ostream &os) |
169 { 170 fatal("Serialization of Interrupts Unimplemented for MIPS"); | 100 { 101 fatal("Serialization of Interrupts Unimplemented for MIPS"); |
171 //SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 172 //SERIALIZE_SCALAR(intstatus); | |
173 } 174 | 102 } 103 |
175 void unserialize(Checkpoint *cp, const std::string §ion) | 104 void 105 unserialize(Checkpoint *cp, const std::string §ion) |
176 { 177 fatal("Unserialization of Interrupts Unimplemented for MIPS"); | 106 { 107 fatal("Unserialization of Interrupts Unimplemented for MIPS"); |
178 //UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 179 //UNSERIALIZE_SCALAR(intstatus); | |
180 } 181 | 108 } 109 |
182 183 | |
184 private: 185 bool newInfoSet; 186 int newIpl; 187 int newSummary; | 110 private: 111 bool newInfoSet; 112 int newIpl; 113 int newSummary; |
188 | |
189}; 190 191} 192 193#endif 194 | 114}; 115 116} 117 118#endif 119 |