interrupts.hh (5646:0a488a147fb8) interrupts.hh (5704:98224505352a)
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52 newInfoSet = false;
53 oncputimerintr = false;
54
55 }
56 // post(int int_num, int index) is responsible
57 // for posting an interrupt. It sets a bit
58 // in intstatus corresponding to Cause IP*. The
59 // MIPS register Cause is updated by updateIntrInfo
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 43 unchanged lines hidden (view full) ---

52 newInfoSet = false;
53 oncputimerintr = false;
54
55 }
56 // post(int int_num, int index) is responsible
57 // for posting an interrupt. It sets a bit
58 // in intstatus corresponding to Cause IP*. The
59 // MIPS register Cause is updated by updateIntrInfo
60 // which is called by check_interrupts
60 // which is called by checkInterrupts
61 //
62 void post(int int_num, int index);
63 // clear(int int_num, int index) is responsible
64 // for clearing an interrupt. It clear a bit
65 // in intstatus corresponding to Cause IP*. The
66 // MIPS register Cause is updated by updateIntrInfo
61 //
62 void post(int int_num, int index);
63 // clear(int int_num, int index) is responsible
64 // for clearing an interrupt. It clear a bit
65 // in intstatus corresponding to Cause IP*. The
66 // MIPS register Cause is updated by updateIntrInfo
67 // which is called by check_interrupts
67 // which is called by checkInterrupts
68 //
69 void clear(int int_num, int index);
68 //
69 void clear(int int_num, int index);
70 // clear_all() is responsible
70 // clearAll() is responsible
71 // for clearing all interrupts. It clears all bits
72 // in intstatus corresponding to Cause IP*. The
73 // MIPS register Cause is updated by updateIntrInfo
71 // for clearing all interrupts. It clears all bits
72 // in intstatus corresponding to Cause IP*. The
73 // MIPS register Cause is updated by updateIntrInfo
74 // which is called by check_interrupts
74 // which is called by checkInterrupts
75 //
75 //
76 void clear_all();
76 void clearAll();
77
78 // getInterrupt(ThreadContext * tc) checks if an interrupt
79 // should be returned. It ands the interrupt mask and
80 // and interrupt pending bits to see if one exists. It
81 // also makes sure interrupts are enabled (IE) and
82 // that ERL and ERX are not set
83 //
84 Fault getInterrupt(ThreadContext * tc);
85
86 // updateIntrInfo(ThreadContext *tc) const syncs the
87 // MIPS cause register with the instatus variable. instatus
88 // is essentially a copy of the MIPS cause[IP7:IP0]
89 //
90 void updateIntrInfo(ThreadContext *tc) const;
91 void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
92 bool onCpuTimerInterrupt(ThreadContext *tc) const;
93
77
78 // getInterrupt(ThreadContext * tc) checks if an interrupt
79 // should be returned. It ands the interrupt mask and
80 // and interrupt pending bits to see if one exists. It
81 // also makes sure interrupts are enabled (IE) and
82 // that ERL and ERX are not set
83 //
84 Fault getInterrupt(ThreadContext * tc);
85
86 // updateIntrInfo(ThreadContext *tc) const syncs the
87 // MIPS cause register with the instatus variable. instatus
88 // is essentially a copy of the MIPS cause[IP7:IP0]
89 //
90 void updateIntrInfo(ThreadContext *tc) const;
91 void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
92 bool onCpuTimerInterrupt(ThreadContext *tc) const;
93
94 bool check_interrupts(ThreadContext * tc) const{
94 bool checkInterrupts(ThreadContext *tc) const {
95 //return (intstatus != 0) && !(tc->readPC() & 0x3);
96 if (oncputimerintr == false){
97 updateIntrInfo(tc);
98 return ((intstatus != 0) || onCpuTimerInterrupt(tc));
99 }
100 else
101 return true;
102

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114 newInfoSet = false;
115 //oncputimerintr = false;
116
117 }
118 // post(int int_num, int index) is responsible
119 // for posting an interrupt. It sets a bit
120 // in intstatus corresponding to Cause IP*. The
121 // MIPS register Cause is updated by updateIntrInfo
95 //return (intstatus != 0) && !(tc->readPC() & 0x3);
96 if (oncputimerintr == false){
97 updateIntrInfo(tc);
98 return ((intstatus != 0) || onCpuTimerInterrupt(tc));
99 }
100 else
101 return true;
102

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114 newInfoSet = false;
115 //oncputimerintr = false;
116
117 }
118 // post(int int_num, int index) is responsible
119 // for posting an interrupt. It sets a bit
120 // in intstatus corresponding to Cause IP*. The
121 // MIPS register Cause is updated by updateIntrInfo
122 // which is called by check_interrupts
122 // which is called by checkInterrupts
123 //
124 void post(int int_num, ThreadContext* tc);
125 void post(int int_num, int index);
126
127 // clear(int int_num, int index) is responsible
128 // for clearing an interrupt. It clear a bit
129 // in intstatus corresponding to Cause IP*. The
130 // MIPS register Cause is updated by updateIntrInfo
123 //
124 void post(int int_num, ThreadContext* tc);
125 void post(int int_num, int index);
126
127 // clear(int int_num, int index) is responsible
128 // for clearing an interrupt. It clear a bit
129 // in intstatus corresponding to Cause IP*. The
130 // MIPS register Cause is updated by updateIntrInfo
131 // which is called by check_interrupts
131 // which is called by checkInterrupts
132 //
133 void clear(int int_num, ThreadContext* tc);
134 void clear(int int_num, int index);
135
132 //
133 void clear(int int_num, ThreadContext* tc);
134 void clear(int int_num, int index);
135
136 // clear_all() is responsible
136 // clearAll() is responsible
137 // for clearing all interrupts. It clears all bits
138 // in intstatus corresponding to Cause IP*. The
139 // MIPS register Cause is updated by updateIntrInfo
137 // for clearing all interrupts. It clears all bits
138 // in intstatus corresponding to Cause IP*. The
139 // MIPS register Cause is updated by updateIntrInfo
140 // which is called by check_interrupts
140 // which is called by checkInterrupts
141 //
141 //
142 void clear_all(ThreadContext* tc);
143 void clear_all();
142 void clearAll(ThreadContext* tc);
143 void clearAll();
144
145 // getInterrupt(ThreadContext * tc) checks if an interrupt
146 // should be returned. It ands the interrupt mask and
147 // and interrupt pending bits to see if one exists. It
148 // also makes sure interrupts are enabled (IE) and
149 // that ERL and ERX are not set
150 //
151 Fault getInterrupt(ThreadContext * tc);
152
153 // updateIntrInfo(ThreadContext *tc) const syncs the
154 // MIPS cause register with the instatus variable. instatus
155 // is essentially a copy of the MIPS cause[IP7:IP0]
156 //
157 void updateIntrInfo(ThreadContext *tc) const;
158 bool interruptsPending(ThreadContext *tc) const;
159 bool onCpuTimerInterrupt(ThreadContext *tc) const;
160
144
145 // getInterrupt(ThreadContext * tc) checks if an interrupt
146 // should be returned. It ands the interrupt mask and
147 // and interrupt pending bits to see if one exists. It
148 // also makes sure interrupts are enabled (IE) and
149 // that ERL and ERX are not set
150 //
151 Fault getInterrupt(ThreadContext * tc);
152
153 // updateIntrInfo(ThreadContext *tc) const syncs the
154 // MIPS cause register with the instatus variable. instatus
155 // is essentially a copy of the MIPS cause[IP7:IP0]
156 //
157 void updateIntrInfo(ThreadContext *tc) const;
158 bool interruptsPending(ThreadContext *tc) const;
159 bool onCpuTimerInterrupt(ThreadContext *tc) const;
160
161 bool check_interrupts(ThreadContext * tc) const{
161 bool
162 checkInterrupts(ThreadContext *tc) const
163 {
162 return interruptsPending(tc);
163 }
164
165
166 void serialize(std::ostream &os)
167 {
168 fatal("Serialization of Interrupts Unimplemented for MIPS");
169 //SERIALIZE_ARRAY(interrupts, NumInterruptLevels);

--- 23 unchanged lines hidden --- 		164 return interruptsPending(tc);
165 }
166
167
168 void serialize(std::ostream &os)
169 {
170 fatal("Serialization of Interrupts Unimplemented for MIPS");
171 //SERIALIZE_ARRAY(interrupts, NumInterruptLevels);

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