interrupts.hh (5254:c555f8b07345) interrupts.hh (5646:0a488a147fb8)
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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86 // updateIntrInfo(ThreadContext *tc) const syncs the
87 // MIPS cause register with the instatus variable. instatus
88 // is essentially a copy of the MIPS cause[IP7:IP0]
89 //
90 void updateIntrInfo(ThreadContext *tc) const;
91 void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
92 bool onCpuTimerInterrupt(ThreadContext *tc) const;
93
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 77 unchanged lines hidden (view full) ---

86 // updateIntrInfo(ThreadContext *tc) const syncs the
87 // MIPS cause register with the instatus variable. instatus
88 // is essentially a copy of the MIPS cause[IP7:IP0]
89 //
90 void updateIntrInfo(ThreadContext *tc) const;
91 void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
92 bool onCpuTimerInterrupt(ThreadContext *tc) const;
93
94 uint64_t get_vec(int int_num);
95
96 bool check_interrupts(ThreadContext * tc) const{
97 //return (intstatus != 0) && !(tc->readPC() & 0x3);
98 if (oncputimerintr == false){
99 updateIntrInfo(tc);
100 return ((intstatus != 0) || onCpuTimerInterrupt(tc));
101 }
102 else
103 return true;

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155 // updateIntrInfo(ThreadContext *tc) const syncs the
156 // MIPS cause register with the instatus variable. instatus
157 // is essentially a copy of the MIPS cause[IP7:IP0]
158 //
159 void updateIntrInfo(ThreadContext *tc) const;
160 bool interruptsPending(ThreadContext *tc) const;
161 bool onCpuTimerInterrupt(ThreadContext *tc) const;
162
94 bool check_interrupts(ThreadContext * tc) const{
95 //return (intstatus != 0) && !(tc->readPC() & 0x3);
96 if (oncputimerintr == false){
97 updateIntrInfo(tc);
98 return ((intstatus != 0) || onCpuTimerInterrupt(tc));
99 }
100 else
101 return true;

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153 // updateIntrInfo(ThreadContext *tc) const syncs the
154 // MIPS cause register with the instatus variable. instatus
155 // is essentially a copy of the MIPS cause[IP7:IP0]
156 //
157 void updateIntrInfo(ThreadContext *tc) const;
158 bool interruptsPending(ThreadContext *tc) const;
159 bool onCpuTimerInterrupt(ThreadContext *tc) const;
160
163 uint64_t get_vec(int int_num);
164
165 bool check_interrupts(ThreadContext * tc) const{
166 return interruptsPending(tc);
167 }
168
169
170 void serialize(std::ostream &os)
171 {
172 fatal("Serialization of Interrupts Unimplemented for MIPS");

--- 24 unchanged lines hidden --- 		161 bool check_interrupts(ThreadContext * tc) const{
162 return interruptsPending(tc);
163 }
164
165
166 void serialize(std::ostream &os)
167 {
168 fatal("Serialization of Interrupts Unimplemented for MIPS");

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