interrupts.cc (8745:575cab0db076) interrupts.cc (10474:799c8ee4ecba)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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118 if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
119 // Software interrupts & hardware interrupts are handled in software.
120 // So if any interrupt that isn't masked is detected, jump to interrupt
121 // handler
122 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
123 if (status.im && cause.ip) {
124 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
125 (unsigned)status.im, (unsigned)cause.ip);
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 109 unchanged lines hidden (view full) ---

118 if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
119 // Software interrupts & hardware interrupts are handled in software.
120 // So if any interrupt that isn't masked is detected, jump to interrupt
121 // handler
122 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
123 if (status.im && cause.ip) {
124 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
125 (unsigned)status.im, (unsigned)cause.ip);
126 return new InterruptFault;
126 return std::make_shared<InterruptFault>();
127 }
128 }
129
130 return NoFault;
131}
132
133bool
134Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const

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127 }
128 }
129
130 return NoFault;
131}
132
133bool
134Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const

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