interrupts.cc (6379:75d4aaf7dd54) | interrupts.cc (6383:31c067ae3331) |
---|---|
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 28 unchanged lines hidden (view full) --- 37#include "base/trace.hh" 38#include "cpu/thread_context.hh" 39 40namespace MipsISA 41{ 42 43static inline uint8_t 44getCauseIP(ThreadContext *tc) { | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 28 unchanged lines hidden (view full) --- 37#include "base/trace.hh" 38#include "cpu/thread_context.hh" 39 40namespace MipsISA 41{ 42 43static inline uint8_t 44getCauseIP(ThreadContext *tc) { |
45 CauseReg cause = tc->readMiscRegNoEffect(Cause); | 45 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); |
46 return cause.ip; 47} 48 49static inline void 50setCauseIP(ThreadContext *tc, uint8_t val) { | 46 return cause.ip; 47} 48 49static inline void 50setCauseIP(ThreadContext *tc, uint8_t val) { |
51 CauseReg cause = tc->readMiscRegNoEffect(Cause); | 51 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); |
52 cause.ip = val; | 52 cause.ip = val; |
53 tc->setMiscRegNoEffect(Cause, cause); | 53 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); |
54} 55 56void 57Interrupts::post(int int_num, ThreadContext* tc) 58{ 59 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num); 60 if (int_num < 0 || int_num >= NumInterruptLevels) 61 panic("int_num out of bounds\n"); --- 44 unchanged lines hidden (view full) --- 106 107 108Fault 109Interrupts::getInterrupt(ThreadContext * tc) 110{ 111 DPRINTF(Interrupt, "Interrupts getInterrupt\n"); 112 113 //Check if there are any outstanding interrupts | 54} 55 56void 57Interrupts::post(int int_num, ThreadContext* tc) 58{ 59 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num); 60 if (int_num < 0 || int_num >= NumInterruptLevels) 61 panic("int_num out of bounds\n"); --- 44 unchanged lines hidden (view full) --- 106 107 108Fault 109Interrupts::getInterrupt(ThreadContext * tc) 110{ 111 DPRINTF(Interrupt, "Interrupts getInterrupt\n"); 112 113 //Check if there are any outstanding interrupts |
114 StatusReg status = tc->readMiscRegNoEffect(Status); | 114 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); |
115 // Interrupts must be enabled, error level must be 0 or interrupts 116 // inhibited, and exception level must be 0 or interrupts inhibited 117 if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) { 118 // Software interrupts & hardware interrupts are handled in software. 119 // So if any interrupt that isn't masked is detected, jump to interrupt 120 // handler | 115 // Interrupts must be enabled, error level must be 0 or interrupts 116 // inhibited, and exception level must be 0 or interrupts inhibited 117 if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) { 118 // Software interrupts & hardware interrupts are handled in software. 119 // So if any interrupt that isn't masked is detected, jump to interrupt 120 // handler |
121 CauseReg cause = tc->readMiscRegNoEffect(Cause); | 121 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); |
122 if (status.im && cause.ip) { 123 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n", 124 (unsigned)status.im, (unsigned)cause.ip); 125 return new InterruptFault; 126 } 127 } 128 129 return NoFault; 130} 131 132bool 133Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const 134{ | 122 if (status.im && cause.ip) { 123 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n", 124 (unsigned)status.im, (unsigned)cause.ip); 125 return new InterruptFault; 126 } 127 } 128 129 return NoFault; 130} 131 132bool 133Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const 134{ |
135 MiscReg compare = tc->readMiscRegNoEffect(Compare); 136 MiscReg count = tc->readMiscRegNoEffect(Count); | 135 MiscReg compare = tc->readMiscRegNoEffect(MISCREG_COMPARE); 136 MiscReg count = tc->readMiscRegNoEffect(MISCREG_COUNT); |
137 if (compare == count && count != 0) 138 return true; 139 return false; 140} 141 142void 143Interrupts::updateIntrInfo(ThreadContext *tc) const 144{ 145 //Nothing needs to be done. 146} 147 148bool 149Interrupts::interruptsPending(ThreadContext *tc) const 150{ 151 //if there is a on cpu timer interrupt (i.e. Compare == Count) 152 //update CauseIP before proceeding to interrupt 153 if (onCpuTimerInterrupt(tc)) { 154 DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n"); 155 //determine timer interrupt IP # | 137 if (compare == count && count != 0) 138 return true; 139 return false; 140} 141 142void 143Interrupts::updateIntrInfo(ThreadContext *tc) const 144{ 145 //Nothing needs to be done. 146} 147 148bool 149Interrupts::interruptsPending(ThreadContext *tc) const 150{ 151 //if there is a on cpu timer interrupt (i.e. Compare == Count) 152 //update CauseIP before proceeding to interrupt 153 if (onCpuTimerInterrupt(tc)) { 154 DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n"); 155 //determine timer interrupt IP # |
156 IntCtlReg intCtl = tc->readMiscRegNoEffect(IntCtl); | 156 IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL); |
157 uint8_t intStatus = getCauseIP(tc); 158 intStatus |= 1 << intCtl.ipti; 159 setCauseIP(tc, intStatus); 160 } 161 162 return (getCauseIP(tc) != 0); 163 164} 165 166} 167 168MipsISA::Interrupts * 169MipsInterruptsParams::create() 170{ 171 return new MipsISA::Interrupts(this); 172} | 157 uint8_t intStatus = getCauseIP(tc); 158 intStatus |= 1 << intCtl.ipti; 159 setCauseIP(tc, intStatus); 160 } 161 162 return (getCauseIP(tc) != 0); 163 164} 165 166} 167 168MipsISA::Interrupts * 169MipsInterruptsParams::create() 170{ 171 return new MipsISA::Interrupts(this); 172} |