interrupts.cc (6378:4a2ff62c3b4f) interrupts.cc (6379:75d4aaf7dd54)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 * Kevin Lim
31 * Korey Sewell
32 */
33
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 * Kevin Lim
31 * Korey Sewell
32 */
33
34#include "arch/mips/pra_constants.hh"
34#include "arch/mips/interrupts.hh"
35#include "arch/mips/isa_traits.hh"
35#include "arch/mips/isa_traits.hh"
36#include "arch/mips/pra_constants.hh"
37#include "base/trace.hh"
36#include "cpu/thread_context.hh"
38#include "cpu/thread_context.hh"
37#include "arch/mips/interrupts.hh"
38
39namespace MipsISA
40{
41
42static inline uint8_t
43getCauseIP(ThreadContext *tc) {
39
40namespace MipsISA
41{
42
43static inline uint8_t
44getCauseIP(ThreadContext *tc) {
44 MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
45 return bits(cause, Cause_IP7, Cause_IP0);
45 CauseReg cause = tc->readMiscRegNoEffect(Cause);
46 return cause.ip;
46}
47
48static inline void
47}
48
49static inline void
49setCauseIP_(ThreadContext *tc, uint8_t val) {
50 MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
51 replaceBits(cause, Cause_IP7, Cause_IP0, val);
52 tc->setMiscRegNoEffect(MipsISA::Cause, cause);
50setCauseIP(ThreadContext *tc, uint8_t val) {
51 CauseReg cause = tc->readMiscRegNoEffect(Cause);
52 cause.ip = val;
53 tc->setMiscRegNoEffect(Cause, cause);
53}
54
55void
56Interrupts::post(int int_num, ThreadContext* tc)
57{
58 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
59 if (int_num < 0 || int_num >= NumInterruptLevels)
60 panic("int_num out of bounds\n");

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105
106
107Fault
108Interrupts::getInterrupt(ThreadContext * tc)
109{
110 DPRINTF(Interrupt, "Interrupts getInterrupt\n");
111
112 //Check if there are any outstanding interrupts
54}
55
56void
57Interrupts::post(int int_num, ThreadContext* tc)
58{
59 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
60 if (int_num < 0 || int_num >= NumInterruptLevels)
61 panic("int_num out of bounds\n");

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106
107
108Fault
109Interrupts::getInterrupt(ThreadContext * tc)
110{
111 DPRINTF(Interrupt, "Interrupts getInterrupt\n");
112
113 //Check if there are any outstanding interrupts
113 MiscReg status = tc->readMiscRegNoEffect(MipsISA::Status);
114 StatusReg status = tc->readMiscRegNoEffect(Status);
114 // Interrupts must be enabled, error level must be 0 or interrupts
115 // inhibited, and exception level must be 0 or interrupts inhibited
115 // Interrupts must be enabled, error level must be 0 or interrupts
116 // inhibited, and exception level must be 0 or interrupts inhibited
116 if (bits(status, Status_IE_LO) == 1 &&
117 bits(status, Status_ERL_HI, Status_ERL_LO) == 0 &&
118 bits(status, Status_EXL_HI, Status_EXL_LO) == 0) {
117 if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
119 // Software interrupts & hardware interrupts are handled in software.
120 // So if any interrupt that isn't masked is detected, jump to interrupt
121 // handler
118 // Software interrupts & hardware interrupts are handled in software.
119 // So if any interrupt that isn't masked is detected, jump to interrupt
120 // handler
122 uint8_t InterruptMask = bits(status, Status_IM7, Status_IM0);
123 uint8_t InterruptPending = getCauseIP(tc);
124 // InterruptMask and InterruptPending are already correctly aligned
125 if (InterruptMask && InterruptPending){
121 CauseReg cause = tc->readMiscRegNoEffect(Cause);
122 if (status.im && cause.ip) {
126 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
123 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
127 InterruptMask, InterruptPending);
124 (unsigned)status.im, (unsigned)cause.ip);
128 return new InterruptFault;
129 }
130 }
131
132 return NoFault;
133}
134
135bool
136Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
137{
125 return new InterruptFault;
126 }
127 }
128
129 return NoFault;
130}
131
132bool
133Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
134{
138 MiscReg compare = tc->readMiscRegNoEffect(MipsISA::Compare);
139 MiscReg count = tc->readMiscRegNoEffect(MipsISA::Count);
135 MiscReg compare = tc->readMiscRegNoEffect(Compare);
136 MiscReg count = tc->readMiscRegNoEffect(Count);
140 if (compare == count && count != 0)
141 return true;
142 return false;
143}
144
145void
146Interrupts::updateIntrInfo(ThreadContext *tc) const
147{
148 //Nothing needs to be done.
149}
150
151bool
152Interrupts::interruptsPending(ThreadContext *tc) const
153{
154 //if there is a on cpu timer interrupt (i.e. Compare == Count)
155 //update CauseIP before proceeding to interrupt
156 if (onCpuTimerInterrupt(tc)) {
157 DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
158 //determine timer interrupt IP #
137 if (compare == count && count != 0)
138 return true;
139 return false;
140}
141
142void
143Interrupts::updateIntrInfo(ThreadContext *tc) const
144{
145 //Nothing needs to be done.
146}
147
148bool
149Interrupts::interruptsPending(ThreadContext *tc) const
150{
151 //if there is a on cpu timer interrupt (i.e. Compare == Count)
152 //update CauseIP before proceeding to interrupt
153 if (onCpuTimerInterrupt(tc)) {
154 DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
155 //determine timer interrupt IP #
159 MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);
160 uint8_t IPTI = bits(intctl, IntCtl_IPTI_HI, IntCtl_IPTI_LO);
161 //set intstatus to correspond
162 //post(IPTI, tc);
163 uint8_t intstatus = getCauseIP(tc);
164 intstatus |= 1 << IPTI;
165 setCauseIP(tc, intstatus);
156 IntCtlReg intCtl = tc->readMiscRegNoEffect(IntCtl);
157 uint8_t intStatus = getCauseIP(tc);
158 intStatus |= 1 << intCtl.ipti;
159 setCauseIP(tc, intStatus);
166 }
167
168 return (getCauseIP(tc) != 0);
169
170}
171
172}
160 }
161
162 return (getCauseIP(tc) != 0);
163
164}
165
166}
167
168MipsISA::Interrupts *
169MipsInterruptsParams::create()
170{
171 return new MipsISA::Interrupts(this);
172}